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| author | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-04-28 18:21:00 -0700 |
|---|---|---|
| committer | Faraz Shahbazker <fshahbazker@wavecomp.com> | 2019-05-06 06:43:32 -0700 |
| commit | 41cee0897b670168e0d6f455c9bc45c73f8023df (patch) | |
| tree | 90f15ebdf438ae1956dc5a3d7eea35c64ae41a10 /include | |
| parent | be0d3bbbcdbdba83f74d8ad1be6c4c759255af0b (diff) | |
| download | gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.zip gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.tar.gz gdb-41cee0897b670168e0d6f455c9bc45c73f8023df.tar.bz2 | |
Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1]. These instructions are optional within
the EVA ASE. Their presence is indicated by the XNP bit in the
Config5 register.
[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
Instruction Set Manual", Imagination Technologies Ltd., Document
Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
"Alphabetical List of Instructions", pp. 230-231, pp. 357-360.
gas/
* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
(mips_after_parse_args): Translate EVA to EVA_R6.
* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
* testsuite/gas/mips/eva.s: Likewise.
* testsuite/gas/mips/ase-errors-1.l: Check errors for
new instructions.
* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.
include/
* opcode/mips.h (ASE_EVA_R6): New macro.
(M_LLWPE_AB, M_SCWPE_AB): New enum values.
opcodes/
* mips-dis.c (mips_calculate_combination_ases): Add ISA
argument and set ASE_EVA_R6 appropriately.
(set_default_mips_dis_options): Pass ISA to above.
(parse_mips_dis_option): Likewise.
* mips-opc.c (EVAR6): New macro.
(mips_builtin_opcodes): Add llwpe, scwpe.
Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/mips.h | 5 |
2 files changed, 11 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 1aab82a..cab6418 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> + Faraz Shahbazker <fshahbazker@wavecomp.com> + + * opcode/mips.h (ASE_EVA_R6): New macro. + (M_LLWPE_AB, M_SCWPE_AB): New enum values. + 2019-05-01 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_TME): New. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index bc7deec..5cba8fb 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1308,6 +1308,9 @@ static const unsigned int mips_isa_table[] = { #define ASE_LOONGSON_EXT 0x00800000 /* Loongson EXTensions R2 (EXT2) instructions. */ #define ASE_LOONGSON_EXT2 0x01000000 +/* The Enhanced VA Scheme (EVA) extension has instructions which are + only valid for the R6 ISA. */ +#define ASE_EVA_R6 0x02000000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ @@ -1631,6 +1634,7 @@ enum M_LLDP_AB, M_LLE_AB, M_LLWP_AB, + M_LLWPE_AB, M_LQ_AB, M_LW_AB, M_LWE_AB, @@ -1684,6 +1688,7 @@ enum M_SCDP_AB, M_SCE_AB, M_SCWP_AB, + M_SCWPE_AB, M_SD_AB, M_SDC1_AB, M_SDC2_AB, |