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| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:22 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:22 +0100 |
| commit | 3c17238bc9fe8a078a6199470291f07bab9c64c8 (patch) | |
| tree | 31443cb03fc7932249004d085552ab29ab5a9556 /include | |
| parent | cd50a87ae29f163e7d254729a902a5e51fcccbbc (diff) | |
| download | gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.zip gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.tar.gz gdb-3c17238bc9fe8a078a6199470291f07bab9c64c8.tar.bz2 | |
[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
Include a new iclass to extract the variant from the most significant 3
bits of this operand.
Instructions such as rshrnb include a constant shift amount as an
operand, where the most significant three bits of this operand determine
what size elements the instruction is operating on.
The new SVE_SHRIMM_UNPRED_22 operand denotes this constant encoded in
bits 22:20-19:18-16 while the new sve_shift_tsz_hsd iclass denotes that
the SVE qualifier is encoded in bits 22:20-19.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (parse_operands): Handle new SVE_SHRIMM_UNPRED_22
operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22
operand.
(enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-asm.c (aarch64_ins_sve_shrimm):
(aarch64_encode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass encode.
* aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
sve_shift_tsz_hsd iclass decode.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_SHRIMM_UNPRED_22.
(aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
operand.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/aarch64.h | 2 |
2 files changed, 8 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 600e753..3b389d5 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * opcode/aarch64.h (enum aarch64_opnd): New SVE_SHRIMM_UNPRED_22 + operand. + (enum aarch64_insn_class): Add sve_shift_tsz_hsd iclass. + +2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> + * opcode/aarch64.h (enum aarch64_insn_class): Add sve_size_013 iclass. 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 9cc73ca..bd6b845 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -394,6 +394,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */ AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */ AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */ + AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */ AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */ AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */ AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */ @@ -597,6 +598,7 @@ enum aarch64_insn_class sve_size_bh, sve_size_sd2, sve_size_013, + sve_shift_tsz_hsd, testbranch, cryptosm3, cryptosm4, |