Add macros to get opcode of instructions approriately

LoongArch: Add macros to get opcode and register of instructions appropriately

Currently, we get opcode of an instruction by manipulate the binary with
it's mask, it's a bit of a pain. Now a macro is defined to do this and a
macro to get the RD and RJ registers which is applicable to most instructions
of LoongArch are added.

1 files changed, 65 insertions, 5 deletions

diff --git a/include/opcode/loongarch.h b/include/opcode/loongarch.h
index 965a164..5425eaf 100644
--- a/include/opcode/loongarch.h
+++ b/include/opcode/loongarch.h
@@ -31,22 +31,82 @@ extern "C"
   #define LARCH_NOP 0x03400000
   #define LARCH_B 0x50000000
   /* BCEQZ/BCNEZ.  */
-  #define LARCH_FLOAT_BRANCH 0x48000000
-  #define LARCH_BRANCH_OPCODE_MASK 0xfc000000
   #define LARCH_BRANCH_INVERT_BIT 0x04000000
   #define LARCH_FLOAT_BRANCH_INVERT_BIT 0x00000100
 
+  #define LARCH_MK_ADDI_D 0xffc00000
+  #define LARCH_OP_ADDI_D 0x02c00000
+  #define LARCH_MK_PCADDI 0xfe000000
+  #define LARCH_OP_PCADDI 0x18000000
+  #define LARCH_MK_B 0xfc000000
+  #define LARCH_OP_B 0x50000000
+  #define LARCH_MK_BL 0xfc000000
+  #define LARCH_OP_BL 0x54000000
+  #define LARCH_MK_ORI 0xffc00000
+  #define LARCH_OP_ORI 0x03800000
+  #define LARCH_MK_LU12I_W 0xfe000000
+  #define LARCH_OP_LU12I_W 0x14000000
+  #define LARCH_MK_LD_D 0xffc00000
+  #define LARCH_OP_LD_D 0x28c00000
+  #define LARCH_MK_JIRL 0xfc000000
+  #define LARCH_OP_JIRL 0x4c000000
+  #define LARCH_MK_BCEQZ 0xfc000300
+  #define LARCH_OP_BCEQZ 0x48000000
+  #define LARCH_MK_BCNEZ 0xfc000300
+  #define LARCH_OP_BCNEZ 0x48000100
+  #define LARCH_MK_ATOMIC_MEM 0xffff8000
+  #define LARCH_MK_BSTRINS_W 0xffe08000
+  #define LARCH_OP_BSTRINS_W 0x00600000
+  #define LARCH_MK_BSTRPICK_W 0xffe08000
+  #define LARCH_OP_BSTRPICK_W 0x00608000
+  #define LARCH_MK_BSTRINS_D 0xffc00000
+  #define LARCH_OP_BSTRINS_D 0x00800000
+  #define LARCH_MK_BSTRPICK_D 0xffc00000
+  #define LARCH_OP_BSTRPICK_D 0x00c00000
+  #define LARCH_MK_CSRRD 0xff0003e0
+  #define LARCH_OP_CSRRD 0x04000000
+  #define LARCH_MK_CSRWR 0xff0003e0
+  #define LARCH_OP_CSRWR 0x04000020
+  #define LARCH_MK_CSRXCHG 0xff000000
+  #define LARCH_OP_CSRXCHG 0x04000000
+  #define LARCH_MK_GCSRXCHG 0xff000000
+  #define LARCH_OP_GCSRXCHG 0x05000000
+
+  #define LARCH_INSN_OPS(insn, op) ((insn & LARCH_MK_##op) == LARCH_OP_##op)
+  #define LARCH_INSN_ADDI_D(insn) LARCH_INSN_OPS((insn), ADDI_D)
+  #define LARCH_INSN_PCADDI(insn) LARCH_INSN_OPS((insn), PCADDI)
+  #define LARCH_INSN_B(insn) LARCH_INSN_OPS((insn), B)
+  #define LARCH_INSN_BL(insn) LARCH_INSN_OPS((insn), BL)
+  #define LARCH_INSN_ORI(insn) LARCH_INSN_OPS((insn), ORI)
+  #define LARCH_INSN_LU12I_W(insn) LARCH_INSN_OPS((insn), LU12I_W)
+  #define LARCH_INSN_LD_D(insn) LARCH_INSN_OPS((insn), LD_D)
+  #define LARCH_INSN_JIRL(insn) LARCH_INSN_OPS((insn), JIRL)
+  #define LARCH_INSN_BCEQZ(insn) LARCH_INSN_OPS((insn), BCEQZ)
+  #define LARCH_INSN_BCNEZ(insn) LARCH_INSN_OPS((insn), BCNEZ)
+  #define LARCH_INSN_FLOAT_BRANCH(insn) (LARCH_INSN_BCEQZ(insn) || LARCH_INSN_BCNEZ(insn))
+  #define LARCH_INSN_BSTRINS_W(insn) LARCH_INSN_OPS((insn), BSTRINS_W)
+  #define LARCH_INSN_BSTRPICK_W(insn) LARCH_INSN_OPS((insn), BSTRPICK_W)
+  #define LARCH_INSN_BSTRINS_D(insn) LARCH_INSN_OPS((insn), BSTRINS_D)
+  #define LARCH_INSN_BSTRPICK_D(insn) LARCH_INSN_OPS((insn), BSTRPICK_D)
+  #define LARCH_INSN_CSRXCHG(insn) LARCH_INSN_OPS((insn), CSRXCHG)
+  #define LARCH_INSN_GCSRXCHG(insn) LARCH_INSN_OPS((insn), GCSRXCHG)
+
+  #define LARCH_INSN_ATOMIC_MEM(insn)			\
+	((insn & 0xfff80000) == 0x38580000	\
+	 || (insn & 0xfff00000) == 0x38600000	\
+	 || (insn & 0xffff0000) == 0x38700000	\
+	 || (insn & 0xffff0000) == 0x38710000)
+
   #define ENCODE_BRANCH16_IMM(x) (((x) >> 2) << 10)
 
   #define OUT_OF_RANGE(value, bits, align)	\
     ((value) < (-(1 << ((bits) - 1) << align)) 	\
       || (value) > ((((1 << ((bits) - 1)) - 1) << align)))
 
-  #define LARCH_LU12I_W 0x14000000
-  #define LARCH_ORI 0x03800000
-  #define LARCH_LD_D 0x28c00000
   #define LARCH_RD_A0 0x04
   #define LARCH_RD_RJ_A0 0x084
+  #define LARCH_GET_RD(insn) (insn & 0x1f)
+  #define LARCH_GET_RJ(insn) ((insn >> 5) & 0x1f)
 
   typedef uint32_t insn_t;