aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorNick Clifton <nickc@redhat.com>2006-09-16 23:51:50 +0000
committerNick Clifton <nickc@redhat.com>2006-09-16 23:51:50 +0000
commit1c0d3aa6ae7db5d61f1166cf907ed034d0ac4980 (patch)
tree649703aa90d3ccbe80e1442bfbb36380db2c7edd /include
parent0112cd268b205d8176b8b4d00988a334822956cf (diff)
downloadgdb-1c0d3aa6ae7db5d61f1166cf907ed034d0ac4980.zip
gdb-1c0d3aa6ae7db5d61f1166cf907ed034d0ac4980.tar.gz
gdb-1c0d3aa6ae7db5d61f1166cf907ed034d0ac4980.tar.bz2
Add support for Score target.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog4
-rw-r--r--include/dis-asm.h82
-rw-r--r--include/elf/ChangeLog5
-rw-r--r--include/elf/common.h1
-rw-r--r--include/elf/score.h124
-rw-r--r--include/opcode/ChangeLog5
-rw-r--r--include/opcode/score-datadep.h282
-rw-r--r--include/opcode/score-inst.h506
8 files changed, 970 insertions, 39 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index b072b52..6c09101 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * dis-asm.h: Add prototypes for Score disassembler routines.
+
2006-09-07 H.J. Lu <hongjiu.lu@intel.com>
* bfdlink.h (bfd_elf_dynamic_list): New.
diff --git a/include/dis-asm.h b/include/dis-asm.h
index bdbf9f8..d6f0374 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -1,6 +1,6 @@
/* Interface between the opcode library and its callers.
- Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
@@ -37,7 +37,8 @@ extern "C" {
typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2;
-enum dis_insn_type {
+enum dis_insn_type
+{
dis_noninsn, /* Not a valid instruction */
dis_nonbranch, /* Not a branch instruction */
dis_branch, /* Unconditional branch */
@@ -58,7 +59,8 @@ enum dis_insn_type {
It must be initialized before it is first passed; this can be done
by hand, or using one of the initialization macros below. */
-typedef struct disassemble_info {
+typedef struct disassemble_info
+{
fprintf_ftype fprintf_func;
void *stream;
void *application_data;
@@ -201,59 +203,63 @@ typedef struct disassemble_info {
target address. Return number of octets processed. */
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
-extern int print_insn_big_mips (bfd_vma, disassemble_info *);
-extern int print_insn_little_mips (bfd_vma, disassemble_info *);
-extern int print_insn_i386 (bfd_vma, disassemble_info *);
-extern int print_insn_i386_att (bfd_vma, disassemble_info *);
-extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
-extern int print_insn_ia64 (bfd_vma, disassemble_info *);
-extern int print_insn_i370 (bfd_vma, disassemble_info *);
-extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
-extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
-extern int print_insn_m68k (bfd_vma, disassemble_info *);
-extern int print_insn_z80 (bfd_vma, disassemble_info *);
-extern int print_insn_z8001 (bfd_vma, disassemble_info *);
-extern int print_insn_z8002 (bfd_vma, disassemble_info *);
-extern int print_insn_h8300 (bfd_vma, disassemble_info *);
-extern int print_insn_h8300h (bfd_vma, disassemble_info *);
-extern int print_insn_h8300s (bfd_vma, disassemble_info *);
-extern int print_insn_h8500 (bfd_vma, disassemble_info *);
extern int print_insn_alpha (bfd_vma, disassemble_info *);
-extern int print_insn_big_arm (bfd_vma, disassemble_info *);
-extern int print_insn_little_arm (bfd_vma, disassemble_info *);
-extern int print_insn_sparc (bfd_vma, disassemble_info *);
extern int print_insn_avr (bfd_vma, disassemble_info *);
extern int print_insn_bfin (bfd_vma, disassemble_info *);
+extern int print_insn_big_arm (bfd_vma, disassemble_info *);
+extern int print_insn_big_mips (bfd_vma, disassemble_info *);
+extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
+extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
+extern int print_insn_big_score (bfd_vma, disassemble_info *);
+extern int print_insn_crx (bfd_vma, disassemble_info *);
extern int print_insn_d10v (bfd_vma, disassemble_info *);
extern int print_insn_d30v (bfd_vma, disassemble_info *);
extern int print_insn_dlx (bfd_vma, disassemble_info *);
extern int print_insn_fr30 (bfd_vma, disassemble_info *);
+extern int print_insn_frv (bfd_vma, disassemble_info *);
+extern int print_insn_h8300 (bfd_vma, disassemble_info *);
+extern int print_insn_h8300h (bfd_vma, disassemble_info *);
+extern int print_insn_h8300s (bfd_vma, disassemble_info *);
+extern int print_insn_h8500 (bfd_vma, disassemble_info *);
extern int print_insn_hppa (bfd_vma, disassemble_info *);
+extern int print_insn_i370 (bfd_vma, disassemble_info *);
+extern int print_insn_i386 (bfd_vma, disassemble_info *);
+extern int print_insn_i386_att (bfd_vma, disassemble_info *);
+extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
extern int print_insn_i860 (bfd_vma, disassemble_info *);
extern int print_insn_i960 (bfd_vma, disassemble_info *);
+extern int print_insn_ia64 (bfd_vma, disassemble_info *);
extern int print_insn_ip2k (bfd_vma, disassemble_info *);
+extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
+extern int print_insn_little_arm (bfd_vma, disassemble_info *);
+extern int print_insn_little_mips (bfd_vma, disassemble_info *);
+extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
+extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
+extern int print_insn_little_score (bfd_vma, disassemble_info *);
+extern int print_insn_m32c (bfd_vma, disassemble_info *);
extern int print_insn_m32r (bfd_vma, disassemble_info *);
+extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
+extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
+extern int print_insn_m68k (bfd_vma, disassemble_info *);
extern int print_insn_m88k (bfd_vma, disassemble_info *);
-extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
+extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
extern int print_insn_mcore (bfd_vma, disassemble_info *);
extern int print_insn_mmix (bfd_vma, disassemble_info *);
extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
-extern int print_insn_mt (bfd_vma, disassemble_info *);
extern int print_insn_msp430 (bfd_vma, disassemble_info *);
+extern int print_insn_mt (bfd_vma, disassemble_info *);
extern int print_insn_ns32k (bfd_vma, disassemble_info *);
-extern int print_insn_crx (bfd_vma, disassemble_info *);
extern int print_insn_openrisc (bfd_vma, disassemble_info *);
-extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
-extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
extern int print_insn_pdp11 (bfd_vma, disassemble_info *);
extern int print_insn_pj (bfd_vma, disassemble_info *);
-extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
-extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
extern int print_insn_rs6000 (bfd_vma, disassemble_info *);
extern int print_insn_s390 (bfd_vma, disassemble_info *);
extern int print_insn_sh (bfd_vma, disassemble_info *);
+extern int print_insn_sh64 (bfd_vma, disassemble_info *);
+extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
+extern int print_insn_sparc (bfd_vma, disassemble_info *);
extern int print_insn_tic30 (bfd_vma, disassemble_info *);
extern int print_insn_tic4x (bfd_vma, disassemble_info *);
extern int print_insn_tic54x (bfd_vma, disassemble_info *);
@@ -261,14 +267,12 @@ extern int print_insn_tic80 (bfd_vma, disassemble_info *);
extern int print_insn_v850 (bfd_vma, disassemble_info *);
extern int print_insn_vax (bfd_vma, disassemble_info *);
extern int print_insn_w65 (bfd_vma, disassemble_info *);
+extern int print_insn_xc16x (bfd_vma, disassemble_info *);
extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
extern int print_insn_xtensa (bfd_vma, disassemble_info *);
-extern int print_insn_sh64 (bfd_vma, disassemble_info *);
-extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
-extern int print_insn_frv (bfd_vma, disassemble_info *);
-extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
-extern int print_insn_xc16x (bfd_vma, disassemble_info *);
-extern int print_insn_m32c (bfd_vma, disassemble_info *);
+extern int print_insn_z80 (bfd_vma, disassemble_info *);
+extern int print_insn_z8001 (bfd_vma, disassemble_info *);
+extern int print_insn_z8002 (bfd_vma, disassemble_info *);
extern disassembler_ftype arc_get_disassembler (void *);
extern disassembler_ftype cris_get_disassembler (bfd *);
@@ -277,9 +281,9 @@ extern void print_mips_disassembler_options (FILE *);
extern void print_ppc_disassembler_options (FILE *);
extern void print_arm_disassembler_options (FILE *);
extern void parse_arm_disassembler_option (char *);
-extern int get_arm_regname_num_options (void);
-extern int set_arm_regname_option (int);
-extern int get_arm_regnames (int, const char **, const char **, const char *const **);
+extern int get_arm_regname_num_options (void);
+extern int set_arm_regname_option (int);
+extern int get_arm_regnames (int, const char **, const char **, const char *const **);
extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
/* Fetch the disassembler for a given BFD, if that support is available. */
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index f1c15b5..c9914d9 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score.h: New file.
+ * common.h: Add Score machine number.
+
2006-07-10 Jakub Jelinek <jakub@redhat.com>
* common.h (SHT_GNU_HASH, DT_GNU_HASH): Define.
diff --git a/include/elf/common.h b/include/elf/common.h
index 0380a8f..f041ecb 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -185,6 +185,7 @@
#define EM_BLACKFIN 106 /* ADI Blackfin */
#define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */
#define EM_CRX 114 /* National Semiconductor CRX */
+#define EM_SCORE 135 /* Sunplus Score */
/* If it is necessary to assign new unofficial EM_* values, please pick large
random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision
diff --git a/include/elf/score.h b/include/elf/score.h
new file mode 100644
index 0000000..8eb69a7
--- /dev/null
+++ b/include/elf/score.h
@@ -0,0 +1,124 @@
+/* Score ELF support for BFD.
+ Copyright 2006 Free Software Foundation, Inc.
+ Contributed by
+ Mei Ligang (ligang@sunnorth.com.cn)
+ Pei-Lin Tsai (pltsai@sunplus.com)
+
+ This file is part of BFD, the Binary File Descriptor library.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software Foundation,
+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
+
+#ifndef _ELF_SCORE_H
+#define _ELF_SCORE_H
+
+#include "elf/reloc-macros.h"
+
+#define SCORE_SIMULATOR_ACTIVE 1
+#define OPC_PTMASK 0xc0000000 /* Parity-bit Mask */
+#define OPC16_PTMASK 0x00008000
+/* The parity-bit denotes. */
+#define OPC_32 0xc0000000 /* denotes 32b instruction, (default) */
+#define OPC_16 0x00000000 /* denotes 16b instruction */
+#define OPC_PE 0x8000 /* denotes parallel-execution instructions */
+#define EF_SCORE_HASENTRY 0x02
+#define GP_DISP_LABEL "_gp_disp"
+
+/* Processor specific flags for the ELF header e_flags field. */
+
+/* Fix data dependency. */
+#define EF_SCORE_FIXDEP 0x00000001
+
+/* File contains position independent code. */
+#define EF_SCORE_PIC 0x00000002
+
+/* Defined and allocated common symbol. Value is virtual address. If
+ relocated, alignment must be preserved. */
+#define SHN_SCORE_TEXT 0xff01
+#define SHN_SCORE_DATA 0xff02
+/* Small common symbol. */
+#define SHN_SCORE_SCOMMON 0xff03
+
+/* Processor specific section flags. */
+
+/* This section must be in the global data area. */
+#define SHF_SCORE_GPREL 0x10000000
+
+/* This section should be merged. */
+#define SHF_SCORE_MERGE 0x20000000
+
+/* This section contains address data of size implied by section
+ element size. */
+#define SHF_SCORE_ADDR 0x40000000
+
+/* This section contains string data. */
+#define SHF_SCORE_STRING 0x80000000
+
+/* This section may not be stripped. */
+#define SHF_SCORE_NOSTRIP 0x08000000
+
+/* This section is local to threads. */
+#define SHF_SCORE_LOCAL 0x04000000
+
+/* Linker should generate implicit weak names for this section. */
+#define SHF_SCORE_NAMES 0x02000000
+
+/* Section contais text/data which may be replicated in other sections.
+ Linker should retain only one copy. */
+#define SHF_SCORE_NODUPES 0x01000000
+
+/* Processor specific dynamic array tags. */
+
+/* Base address of the segment. */
+#define DT_SCORE_BASE_ADDRESS 0x70000001
+/* Number of local global offset table entries. */
+#define DT_SCORE_LOCAL_GOTNO 0x70000002
+/* Number of entries in the .dynsym section. */
+#define DT_SCORE_SYMTABNO 0x70000003
+/* Index of first dynamic symbol in global offset table. */
+#define DT_SCORE_GOTSYM 0x70000004
+/* Index of first external dynamic symbol not referenced locally. */
+#define DT_SCORE_UNREFEXTNO 0x70000005
+/* Number of page table entries in global offset table. */
+#define DT_SCORE_HIPAGENO 0x70000006
+
+
+/* Processor specific section types. */
+
+
+/* Relocation types. */
+START_RELOC_NUMBERS (elf_score_reloc_type)
+ RELOC_NUMBER (R_SCORE_NONE, 0)
+ RELOC_NUMBER (R_SCORE_HI16, 1)
+ RELOC_NUMBER (R_SCORE_LO16, 2)
+ RELOC_NUMBER (R_SCORE_DUMMY1, 3)
+ RELOC_NUMBER (R_SCORE_24, 4)
+ RELOC_NUMBER (R_SCORE_PC19, 5)
+ RELOC_NUMBER (R_SCORE16_11, 6)
+ RELOC_NUMBER (R_SCORE16_PC8, 7)
+ RELOC_NUMBER (R_SCORE_ABS32, 8)
+ RELOC_NUMBER (R_SCORE_ABS16, 9)
+ RELOC_NUMBER (R_SCORE_DUMMY2, 10)
+ RELOC_NUMBER (R_SCORE_GP15, 11)
+ RELOC_NUMBER (R_SCORE_GNU_VTINHERIT, 12)
+ RELOC_NUMBER (R_SCORE_GNU_VTENTRY, 13)
+ RELOC_NUMBER (R_SCORE_GOT15, 14)
+ RELOC_NUMBER (R_SCORE_GOT_LO16, 15)
+ RELOC_NUMBER (R_SCORE_CALL15, 16)
+ RELOC_NUMBER (R_SCORE_GPREL32, 17)
+ RELOC_NUMBER (R_SCORE_REL32, 18)
+ RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19)
+END_RELOC_NUMBERS (R_SCORE_max)
+
+#endif /* _ELF_SCORE_H */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 5170514..26df6fe 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
+
+ * score-datadep.h: New file.
+ * score-inst.h: New file.
+
2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
* i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
diff --git a/include/opcode/score-datadep.h b/include/opcode/score-datadep.h
new file mode 100644
index 0000000..8ef35ad
--- /dev/null
+++ b/include/opcode/score-datadep.h
@@ -0,0 +1,282 @@
+/* score-datadep.h -- Score Instructions data dependency table
+ Copyright 2006 Free Software Foundation, Inc.
+ Contributed by:
+ Mei Ligang (ligang@sunnorth.com.cn)
+ Pei-Lin Tsai (pltsai@sunplus.com)
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+#ifndef SCORE_DATA_DEPENDENCY_H
+#define SCORE_DATA_DEPENDENCY_H
+
+#define INSN_NAME_LEN 16
+
+enum insn_type_for_dependency
+{
+ D_pce,
+ D_cond_br,
+ D_cond_mv,
+ D_cached,
+ D_cachei,
+ D_ldst,
+ D_ldcombine,
+ D_mtcr,
+ D_mfcr,
+ D_mfsr,
+ D_mftlb,
+ D_mtptlb,
+ D_mtrtlb,
+ D_stlb,
+ D_all_insn
+};
+
+struct insn_to_dependency
+{
+ char *insn_name;
+ enum insn_type_for_dependency type;
+};
+
+struct data_dependency
+{
+ enum insn_type_for_dependency pre_insn_type;
+ char pre_reg[6];
+ enum insn_type_for_dependency cur_insn_type;
+ char cur_reg[6];
+ int bubblenum_7;
+ int bubblenum_5;
+ int warn_or_error; /* warning - 0; error - 1 */
+};
+
+static const struct insn_to_dependency insn_to_dependency_table[] =
+{
+ /* pce instruction. */
+ {"pce", D_pce},
+ /* conditional branch instruction. */
+ {"bcs", D_cond_br},
+ {"bcc", D_cond_br},
+ {"bgtu", D_cond_br},
+ {"bleu", D_cond_br},
+ {"beq", D_cond_br},
+ {"bne", D_cond_br},
+ {"bgt", D_cond_br},
+ {"ble", D_cond_br},
+ {"bge", D_cond_br},
+ {"blt", D_cond_br},
+ {"bmi", D_cond_br},
+ {"bpl", D_cond_br},
+ {"bvs", D_cond_br},
+ {"bvc", D_cond_br},
+ {"bcsl", D_cond_br},
+ {"bccl", D_cond_br},
+ {"bgtul", D_cond_br},
+ {"bleul", D_cond_br},
+ {"beql", D_cond_br},
+ {"bnel", D_cond_br},
+ {"bgtl", D_cond_br},
+ {"blel", D_cond_br},
+ {"bgel", D_cond_br},
+ {"bltl", D_cond_br},
+ {"bmil", D_cond_br},
+ {"bpll", D_cond_br},
+ {"bvsl", D_cond_br},
+ {"bvcl", D_cond_br},
+ {"bcs!", D_cond_br},
+ {"bcc!", D_cond_br},
+ {"bgtu!", D_cond_br},
+ {"bleu!", D_cond_br},
+ {"beq!", D_cond_br},
+ {"bne!", D_cond_br},
+ {"bgt!", D_cond_br},
+ {"ble!", D_cond_br},
+ {"bge!", D_cond_br},
+ {"blt!", D_cond_br},
+ {"bmi!", D_cond_br},
+ {"bpl!", D_cond_br},
+ {"bvs!", D_cond_br},
+ {"bvc!", D_cond_br},
+ {"brcs", D_cond_br},
+ {"brcc", D_cond_br},
+ {"brgtu", D_cond_br},
+ {"brleu", D_cond_br},
+ {"breq", D_cond_br},
+ {"brne", D_cond_br},
+ {"brgt", D_cond_br},
+ {"brle", D_cond_br},
+ {"brge", D_cond_br},
+ {"brlt", D_cond_br},
+ {"brmi", D_cond_br},
+ {"brpl", D_cond_br},
+ {"brvs", D_cond_br},
+ {"brvc", D_cond_br},
+ {"brcsl", D_cond_br},
+ {"brccl", D_cond_br},
+ {"brgtul", D_cond_br},
+ {"brleul", D_cond_br},
+ {"breql", D_cond_br},
+ {"brnel", D_cond_br},
+ {"brgtl", D_cond_br},
+ {"brlel", D_cond_br},
+ {"brgel", D_cond_br},
+ {"brltl", D_cond_br},
+ {"brmil", D_cond_br},
+ {"brpll", D_cond_br},
+ {"brvsl", D_cond_br},
+ {"brvcl", D_cond_br},
+ {"brcs!", D_cond_br},
+ {"brcc!", D_cond_br},
+ {"brgtu!", D_cond_br},
+ {"brleu!", D_cond_br},
+ {"breq!", D_cond_br},
+ {"brne!", D_cond_br},
+ {"brgt!", D_cond_br},
+ {"brle!", D_cond_br},
+ {"brge!", D_cond_br},
+ {"brlt!", D_cond_br},
+ {"brmi!", D_cond_br},
+ {"brpl!", D_cond_br},
+ {"brvs!", D_cond_br},
+ {"brvc!", D_cond_br},
+ {"brcsl!", D_cond_br},
+ {"brccl!", D_cond_br},
+ {"brgtul!", D_cond_br},
+ {"brleul!", D_cond_br},
+ {"breql!", D_cond_br},
+ {"brnel!", D_cond_br},
+ {"brgtl!", D_cond_br},
+ {"brlel!", D_cond_br},
+ {"brgel!", D_cond_br},
+ {"brltl!", D_cond_br},
+ {"brmil!", D_cond_br},
+ {"brpll!", D_cond_br},
+ {"brvsl!", D_cond_br},
+ {"brvcl!", D_cond_br},
+ /* conditional move instruction. */
+ {"mvcs", D_cond_mv},
+ {"mvcc", D_cond_mv},
+ {"mvgtu", D_cond_mv},
+ {"mvleu", D_cond_mv},
+ {"mveq", D_cond_mv},
+ {"mvne", D_cond_mv},
+ {"mvgt", D_cond_mv},
+ {"mvle", D_cond_mv},
+ {"mvge", D_cond_mv},
+ {"mvlt", D_cond_mv},
+ {"mvmi", D_cond_mv},
+ {"mvpl", D_cond_mv},
+ {"mvvs", D_cond_mv},
+ {"mvvc", D_cond_mv},
+ /* move spectial instruction. */
+ {"mtcr", D_mtcr},
+ {"mftlb", D_mftlb},
+ {"mtptlb", D_mtptlb},
+ {"mtrtlb", D_mtrtlb},
+ {"stlb", D_stlb},
+ {"mfcr", D_mfcr},
+ {"mfsr", D_mfsr},
+ /* cache instruction. */
+ {"cache 8", D_cached},
+ {"cache 9", D_cached},
+ {"cache 10", D_cached},
+ {"cache 11", D_cached},
+ {"cache 12", D_cached},
+ {"cache 13", D_cached},
+ {"cache 14", D_cached},
+ {"cache 24", D_cached},
+ {"cache 26", D_cached},
+ {"cache 27", D_cached},
+ {"cache 29", D_cached},
+ {"cache 30", D_cached},
+ {"cache 31", D_cached},
+ {"cache 0", D_cachei},
+ {"cache 1", D_cachei},
+ {"cache 2", D_cachei},
+ {"cache 3", D_cachei},
+ {"cache 4", D_cachei},
+ {"cache 16", D_cachei},
+ {"cache 17", D_cachei},
+ /* load/store instruction. */
+ {"lb", D_ldst},
+ {"lbu", D_ldst},
+ {"lbu!", D_ldst},
+ {"lbup!", D_ldst},
+ {"lh", D_ldst},
+ {"lhu", D_ldst},
+ {"lh!", D_ldst},
+ {"lhp!", D_ldst},
+ {"lw", D_ldst},
+ {"lw!", D_ldst},
+ {"lwp!", D_ldst},
+ {"sb", D_ldst},
+ {"sb!", D_ldst},
+ {"sbp!", D_ldst},
+ {"sh", D_ldst},
+ {"sh!", D_ldst},
+ {"shp!", D_ldst},
+ {"sw", D_ldst},
+ {"sw!", D_ldst},
+ {"swp!", D_ldst},
+ {"alw", D_ldst},
+ {"asw", D_ldst},
+ {"push!", D_ldst},
+ {"pushhi!", D_ldst},
+ {"pop!", D_ldst},
+ {"pophi!", D_ldst},
+ {"ldc1", D_ldst},
+ {"ldc2", D_ldst},
+ {"ldc3", D_ldst},
+ {"stc1", D_ldst},
+ {"stc2", D_ldst},
+ {"stc3", D_ldst},
+ {"scb", D_ldst},
+ {"scw", D_ldst},
+ {"sce", D_ldst},
+ /* load combine instruction. */
+ {"lcb", D_ldcombine},
+ {"lcw", D_ldcombine},
+ {"lce", D_ldcombine},
+};
+
+static const struct data_dependency data_dependency_table[] =
+{
+ /* Condition register. */
+ {D_mtcr, "cr1", D_pce, "", 2, 1, 1},
+ {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1},
+ {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1},
+ /* Status regiser. */
+ {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0},
+ /* CCR regiser. */
+ {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0},
+ /* EntryHi/EntryLo register. */
+ {D_mftlb, "", D_mtptlb, "", 1, 1, 1},
+ {D_mftlb, "", D_mtrtlb, "", 1, 1, 1},
+ {D_mftlb, "", D_stlb, "", 1, 1,1},
+ {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1},
+ {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1},
+ /* Index register. */
+ {D_stlb, "", D_mtptlb, "", 1, 1, 1},
+ {D_stlb, "", D_mftlb, "", 1, 1, 1},
+ {D_stlb, "", D_mfcr, "cr8", 2, 2, 1},
+ /* Cache. */
+ {D_cached, "", D_ldst, "", 1, 1, 0},
+ {D_cached, "", D_ldcombine, "", 1, 1, 0},
+ {D_cachei, "", D_all_insn, "", 5, 4, 0},
+ /* Load combine. */
+ {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1},
+};
+
+#endif
diff --git a/include/opcode/score-inst.h b/include/opcode/score-inst.h
new file mode 100644
index 0000000..56ceca4
--- /dev/null
+++ b/include/opcode/score-inst.h
@@ -0,0 +1,506 @@
+/* score-inst.h -- Score Instructions Table
+ Copyright 2006 Free Software Foundation, Inc.
+ Contributed by:
+ Mei Ligang (ligang@sunnorth.com.cn)
+ Pei-Lin Tsai (pltsai@sunplus.com)
+
+ This file is part of GAS, the GNU Assembler.
+
+ GAS is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ GAS is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with GAS; see the file COPYING. If not, write to the Free
+ Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
+ 02110-1301, USA. */
+
+#ifndef SCORE_INST_H
+#define SCORE_INST_H
+
+#define LDST_UNALIGN_MASK 0x0000007f
+#define UA_LCB 0x00000060
+#define UA_LCW 0x00000062
+#define UA_LCE 0x00000066
+#define UA_SCB 0x00000068
+#define UA_SCW 0x0000006a
+#define UA_SCE 0x0000006e
+#define UA_LL 0x0000000c
+#define UA_SC 0x0000000e
+#define LDST16_RR_MASK 0x0000000f
+#define N16_LW 8
+#define N16_LH 9
+#define N16_POP 10
+#define N16_LBU 11
+#define N16_SW 12
+#define N16_SH 13
+#define N16_PUSH 14
+#define N16_SB 15
+#define LDST16_RI_MASK 0x7007
+#define N16_LWP 0x7000
+#define N16_LHP 0x7001
+#define N16_LBUP 0x7003
+#define N16_SWP 0x7004
+#define N16_SHP 0x7005
+#define N16_SBP 0x7007
+#define N16_LIU 0x5000
+
+#define OPC_PSEUDOLDST_MASK 0x00000007
+
+enum
+{
+ INSN_LW = 0,
+ INSN_LH = 1,
+ INSN_LHU = 2,
+ INSN_LB = 3,
+ INSN_SW = 4,
+ INSN_SH = 5,
+ INSN_LBU = 6,
+ INSN_SB = 7,
+};
+
+/* Sub opcdoe opcode. */
+enum
+{
+ INSN16_LBU = 11,
+ INSN16_LH = 9,
+ INSN16_LW = 8,
+ INSN16_SB = 15,
+ INSN16_SH = 13,
+ INSN16_SW = 12,
+};
+
+enum
+{
+ LDST_NOUPDATE = 0,
+ LDST_PRE = 1,
+ LDST_POST = 2,
+};
+
+enum score_insn_type
+{
+ Rd_I4,
+ Rd_I5,
+ Rd_rvalueBP_I5,
+ Rd_lvalueBP_I5,
+ Rd_Rs_I5,
+ x_Rs_I5,
+ x_I5_x,
+ Rd_I8,
+ Rd_Rs_I14,
+ I15,
+ Rd_I16,
+ Rd_rvalueRs_SI10,
+ Rd_lvalueRs_SI10,
+ Rd_rvalueRs_preSI12,
+ Rd_rvalueRs_postSI12,
+ Rd_lvalueRs_preSI12,
+ Rd_lvalueRs_postSI12,
+ Rd_Rs_SI14,
+ Rd_rvalueRs_SI15,
+ Rd_lvalueRs_SI15,
+ Rd_SI16,
+ PC_DISP8div2,
+ PC_DISP11div2,
+ PC_DISP19div2,
+ PC_DISP24div2,
+ Rd_Rs_Rs,
+ x_Rs_x,
+ x_Rs_Rs,
+ Rd_Rs_x,
+ Rd_x_Rs,
+ Rd_x_x,
+ Rd_Rs,
+ Rd_HighRs,
+ Rd_lvalueRs,
+ Rd_rvalueRs,
+ Rd_lvalue32Rs,
+ Rd_rvalue32Rs,
+ x_Rs,
+ NO_OPD,
+ NO16_OPD,
+ OP5_rvalueRs_SI15,
+ I5_Rs_Rs_I5_OP5,
+ x_rvalueRs_post4,
+ Rd_rvalueRs_post4,
+ Rd_x_I5,
+ Rd_lvalueRs_post4,
+ x_lvalueRs_post4,
+ Rd_LowRs,
+ Rd_Rs_Rs_imm,
+ Insn_Type_PCE,
+ Insn_Type_SYN,
+ Insn_GP,
+ Insn_PIC,
+};
+
+enum score_data_type
+{
+ _IMM4 = 0,
+ _IMM5,
+ _IMM8,
+ _IMM14,
+ _IMM15,
+ _IMM16,
+ _SIMM10 = 6,
+ _SIMM12,
+ _SIMM14,
+ _SIMM15,
+ _SIMM16,
+ _SIMM14_NEG = 11,
+ _IMM16_NEG,
+ _SIMM16_NEG,
+ _IMM20,
+ _IMM25,
+ _DISP8div2 = 16,
+ _DISP11div2,
+ _DISP19div2,
+ _DISP24div2,
+ _VALUE,
+ _VALUE_HI16,
+ _VALUE_LO16,
+ _VALUE_LDST_LO16 = 23,
+ _SIMM16_LA,
+ _IMM5_RSHIFT_1,
+ _IMM5_RSHIFT_2,
+ _SIMM16_LA_POS,
+ _IMM5_RANGE_8_31,
+ _IMM10_RSHIFT_2,
+ _GP_IMM15 = 30,
+ _GP_IMM14 = 31,
+ _SIMM16_pic = 42, /* Index in score_df_range. */
+ _IMM16_LO16_pic = 43,
+ _IMM16_pic = 44,
+};
+
+#define REG_TMP 1
+
+#define OP_REG_TYPE (1 << 6)
+#define OP_IMM_TYPE (1 << 7)
+#define OP_SH_REGD (OP_REG_TYPE |20)
+#define OP_SH_REGS1 (OP_REG_TYPE |15)
+#define OP_SH_REGS2 (OP_REG_TYPE |10)
+#define OP_SH_I (OP_IMM_TYPE | 1)
+#define OP_SH_RI15 (OP_IMM_TYPE | 0)
+#define OP_SH_I12 (OP_IMM_TYPE | 3)
+#define OP_SH_DISP24 (OP_IMM_TYPE | 1)
+#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15)
+#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1)
+#define OP_SH_I5 (OP_IMM_TYPE |10)
+#define OP_SH_I10 (OP_IMM_TYPE | 5)
+#define OP_SH_COPID (OP_IMM_TYPE | 5)
+#define OP_SH_TRAPI5 (OP_IMM_TYPE |15)
+#define OP_SH_I15 (OP_IMM_TYPE |10)
+
+#define OP16_SH_REGD (OP_REG_TYPE | 8)
+#define OP16_SH_REGS1 (OP_REG_TYPE | 4)
+#define OP16_SH_I45 (OP_IMM_TYPE | 3)
+#define OP16_SH_I8 (OP_IMM_TYPE | 0)
+#define OP16_SH_DISP8 (OP_IMM_TYPE | 0)
+#define OP16_SH_DISP11 (OP_IMM_TYPE | 1)
+
+struct datafield_range
+{
+ int data_type;
+ int bits;
+ int range[2];
+};
+
+struct datafield_range score_df_range[] =
+{
+ {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */
+ {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */
+ {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */
+ {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */
+ {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
+ {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
+ {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */
+ {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */
+ {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */
+ {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */
+ {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
+ {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */
+ {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */
+ {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
+ {_IMM20, 20, {0, (1 << 20) - 1}},
+ {_IMM25, 25, {0, (1 << 25) - 1}},
+ {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */
+ {_DISP11div2, 11, {0, 0}},
+ {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */
+ {_DISP24div2, 24, {0, 0}},
+ {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}},
+ {_VALUE_HI16, 16, {0, (1 << 16) - 1}},
+ {_VALUE_LO16, 16, {0, (1 << 16) - 1}},
+ {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}},
+ {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
+ {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */
+ {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */
+ {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */
+ {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */
+ {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */
+ {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */
+ {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */
+ {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */
+ {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */
+ {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */
+ {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */
+ {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
+ {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
+ {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */
+ {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */
+ {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */
+ {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */
+ {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */
+ {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */
+ {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */
+};
+
+struct shift_bitmask
+{
+ int opd_type;
+ int opd_num;
+ struct datafield_range *df_range;
+ int sh[4];
+ long fieldbits[4];
+};
+
+struct shift_bitmask score_sh_bits_map[] =
+{
+ {
+ Rd_I4, 2, &score_df_range[_IMM4],
+ {OP16_SH_REGD, OP16_SH_I45, 0, 0},
+ {0xf, 0xf, 0, 0},
+ },
+ {
+ Rd_I5, 2, &score_df_range[_IMM5],
+ {OP16_SH_REGD, OP16_SH_I45, 0, 0},
+ {0xf, 0x1f, 0, 0},
+ },
+ {
+ Rd_rvalueBP_I5, 2, &score_df_range[_IMM5],
+ {OP16_SH_REGD, OP16_SH_I45, 0, 0},
+ {0xf, 0x1f, 0, 0},
+ },
+ {
+ Rd_lvalueBP_I5, 2, &score_df_range[_IMM5],
+ {OP16_SH_REGD, OP16_SH_I45, 0, 0},
+ {0xf, 0x1f, 0, 0},
+ },
+ {
+ Rd_Rs_I5, 3, &score_df_range[_IMM5],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0},
+ {0x1f, 0x1f, 0x1f, 0},
+ },
+ {
+ x_Rs_I5, 2, &score_df_range[_IMM5],
+ {OP_SH_REGS1, OP_SH_I5, 0, 0},
+ {0x1f, 0x1f, 0, 0},
+ },
+ {
+ x_I5_x, 1, &score_df_range[_IMM5],
+ {OP_SH_TRAPI5, 0, 0, 0},
+ {0x1f, 0, 0, 0},
+ },
+ {
+ Rd_I8, 2, &score_df_range[_IMM8],
+ {OP16_SH_REGD, OP16_SH_I8, 0, 0},
+ {0xf, 0xff, 0, 0},
+ },
+ {
+ Rd_Rs_I14, 3, &score_df_range[_IMM14],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
+ {0x1f, 0x1f, 0x3fff, 0},
+ },
+ {
+ I15, 1, &score_df_range[_IMM15],
+ {OP_SH_I15, 0, 0, 0},
+ {0x7fff, 0, 0, 0},
+ },
+ {
+ Rd_I16, 2, &score_df_range[_IMM16],
+ {OP_SH_REGD, OP_SH_I, 0, 0},
+ {0x1f, 0xffff, 0, 0},
+ },
+ {
+ Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
+ {0x1f, 0x1f, 0x3ff, 0},
+ },
+ {
+ Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0},
+ {0x1f, 0x1f, 0x3ff, 0},
+ },
+ {
+ Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
+ {0xf, 0xf, 0xfff, 0},
+ },
+ {
+ Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
+ {0xf, 0xf, 0xfff, 0},
+ },
+ {
+ Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
+ {0xf, 0xf, 0xfff, 0},
+ },
+ {
+ Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0},
+ {0xf, 0xf, 0xfff, 0},
+ },
+ {
+ Rd_Rs_SI14, 3, &score_df_range[_SIMM14],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0},
+ {0x1f, 0x1f, 0x3fff, 0},
+ },
+ {
+ Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
+ {0x1f, 0x1f, 0x7fff, 0},
+ },
+ {
+ Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15],
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0},
+ {0x1f, 0x1f, 0x7fff, 0},
+ },
+ {
+ Rd_SI16, 2, &score_df_range[_SIMM16],
+ {OP_SH_REGD, OP_SH_I, 0, 0},
+ {0x1f, 0xffff, 0, 0},
+ },
+ {
+ PC_DISP8div2, 1, &score_df_range[_DISP8div2],
+ {OP16_SH_DISP8, 0, 0, 0},
+ {0xff, 0, 0, 0},
+ },
+ {
+ PC_DISP11div2, 1, &score_df_range[_DISP11div2],
+ {OP16_SH_DISP11, 0, 0, 0},
+ {0x7ff, 0, 0, 0},
+ },
+ {
+ PC_DISP19div2, 2, &score_df_range[_DISP19div2],
+ {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0},
+ {0x3ff, 0x1ff, 0, 0},
+ },
+ {
+ PC_DISP24div2, 1, &score_df_range[_DISP24div2],
+ {OP_SH_DISP24, 0, 0, 0},
+ {0xffffff, 0, 0, 0},
+ },
+ {
+ Rd_Rs_Rs, 3, NULL,
+ {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0},
+ {0x1f, 0x1f, 0x1f, 0}
+ },
+ {
+ Rd_Rs_x, 2, NULL,
+ {OP_SH_REGD, OP_SH_REGS1, 0, 0},
+ {0x1f, 0x1f, 0, 0},
+ },
+ {
+ Rd_x_Rs, 2, NULL,
+ {OP_SH_REGD, OP_SH_REGS2, 0, 0},
+ {0x1f, 0x1f, 0, 0},
+ },
+ {
+ Rd_x_x, 1, NULL,
+ {OP_SH_REGD, 0, 0, 0},
+ {0x1f, 0, 0, 0},
+ },
+ {
+ x_Rs_Rs, 2, NULL,
+ {OP_SH_REGS1, OP_SH_REGS2, 0, 0},
+ {0x1f, 0x1f, 0, 0},
+ },
+ {
+ x_Rs_x, 1, NULL,
+ {OP_SH_REGS1, 0, 0, 0},
+ {0x1f, 0, 0, 0},
+ },
+ {
+ Rd_Rs, 2, NULL,
+ {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
+ {0xf, 0xf, 0, 0},
+ },
+ {
+ Rd_HighRs, 2, NULL,
+ {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
+ {0xf, 0xf, 0x1f, 0},
+ },
+ {
+ Rd_rvalueRs, 2, NULL,
+ {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
+ {0xf, 0xf, 0, 0},
+ },
+ {
+ Rd_lvalueRs, 2, NULL,
+ {OP16_SH_REGD, OP16_SH_REGS1, 0, 0},
+ {0xf, 0xf, 0, 0}
+ },
+ {
+ Rd_lvalue32Rs, 2, NULL,
+ {OP_SH_REGD, OP_SH_REGS1, 0, 0},
+ {0x1f, 0x1f, 0, 0},
+ },
+ {
+ Rd_rvalue32Rs, 2, NULL,
+ {OP_SH_REGD, OP_SH_REGS1, 0, 0},
+ {0x1f, 0x1f, 0, 0},
+ },
+ {
+ x_Rs, 1, NULL,
+ {OP16_SH_REGS1, 0, 0, 0},
+ {0xf, 0, 0, 0},
+ },
+ {
+ NO_OPD, 0, NULL,
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ },
+ {
+ NO16_OPD, 0, NULL,
+ {0, 0, 0, 0},
+ {0, 0, 0, 0},
+ },
+};
+
+struct asm_opcode
+{
+ /* Instruction name. */
+ const char *template;
+
+ /* Instruction Opcode. */
+ unsigned long value;
+
+ /* Instruction bit mask. */
+ unsigned long bitmask;
+
+ /* Relax instruction opcode. 0x8000 imply no relaxation. */
+ unsigned long relax_value;
+
+ /* Instruction type. */
+ enum score_insn_type type;
+
+ /* Function to call to parse args. */
+ void (*parms) (char *);
+};
+
+enum insn_class
+{
+ INSN_CLASS_16,
+ INSN_CLASS_32,
+ INSN_CLASS_PCE,
+ INSN_CLASS_SYN
+};
+
+#endif