diff options
| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-11-06 13:22:42 -0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2017-11-07 09:00:37 -0800 |
| commit | 1270b047fdc68d89f05668ed919d17f5fceeba2a (patch) | |
| tree | a8164ba6096eb6012fb6cc642f4aacd5a579049a /include | |
| parent | a02b41a7e604471e584dc2151fbd36714842710e (diff) | |
| download | gdb-1270b047fdc68d89f05668ed919d17f5fceeba2a.zip gdb-1270b047fdc68d89f05668ed919d17f5fceeba2a.tar.gz gdb-1270b047fdc68d89f05668ed919d17f5fceeba2a.tar.bz2 | |
RISC-V: Add satp as an alias for sptbr
The RISC-V privileged ISA changed the name of sptbr (Supervisor Page
Table Base Register) to satp (Supervisor Address Translation and
Protection) to reflect the fact it could be used for more than just
paging. This patch adds an alias, as they're the same register.
include/ChangeLog
2017-11-06 Palmer Dabbelt <palmer@dabbelt.com>
* opcode/riscv-opc.h (sptbr): Rename to satp.
(CSR_SPTBR): Rename to CSR_SATP.
(sptbr): Alias to CSR_SATP.
gas/ChangeLog
2017-11-06 Palmer Dabbelt <palmer@dabbelt.com>
* testsuite/gas/riscv/satp.d: New test.
testsuite/gas/riscv/satp.s: Likewise.
testsuite/gas/riscv/riscv.exp: Likewise.
config/tc-riscv.c (md_begin): Handle CSR aliases.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 7 |
2 files changed, 11 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 40dfb45..beb08bb 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2017-11-07 Palmer Dabbelt <palmer@dabbelt.com> + + * opcode/riscv-opc.h (sptbr): Rename to satp. + (CSR_SPTBR): Rename to CSR_SATP. + (sptbr): Alias to CSR_SATP. + 2017-11-07 Tamar Christina <tamar.christina@arm.com> * opcode/arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD): diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index b203a6a..ee37d3f 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -611,7 +611,7 @@ #define CSR_SCAUSE 0x142 #define CSR_SBADADDR 0x143 #define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 +#define CSR_SATP 0x180 #define CSR_MSTATUS 0x300 #define CSR_MISA 0x301 #define CSR_MEDELEG 0x302 @@ -1123,7 +1123,7 @@ DECLARE_CSR(sepc, CSR_SEPC) DECLARE_CSR(scause, CSR_SCAUSE) DECLARE_CSR(sbadaddr, CSR_SBADADDR) DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) +DECLARE_CSR(satp, CSR_SATP) DECLARE_CSR(mstatus, CSR_MSTATUS) DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(medeleg, CSR_MEDELEG) @@ -1293,6 +1293,9 @@ DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) #endif +#ifdef DECLARE_CSR_ALIAS +DECLARE_CSR_ALIAS(sptbr, CSR_SATP) +#endif #ifdef DECLARE_CAUSE DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) |