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authorMaciej W. Rozycki <macro@linux-mips.org>2012-07-31 21:38:54 +0000
committerMaciej W. Rozycki <macro@linux-mips.org>2012-07-31 21:38:54 +0000
commit03f66e8a8f77e2df4ecdc9b32bcc96ab5cb0e85e (patch)
tree43c7deebce70b9219edc9a020fe1a9bfbd086a41 /include
parent33fee3c9c6498755cc187bc912a9e69de5fd9e7d (diff)
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include/opcode/
* mips.h: Document microMIPS DSP ASE usage. (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for microMIPS DSP ASE support. (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise. (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise. (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise. (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise. (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise. (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise. (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise. gas/ * config/tc-mips.c (macro_build) <'2'>: Handle microMIPS. (macro) <M_BALIGN>: Update error handling. (validate_micromips_insn) <'2', '3', '4', '5', '6'>: New cases. <'7', '8', '0', '@', '^'>: Likewise. (mips_ip) <'2', '3', '4', '5', '6', '7', '8'>: Handle microMIPS. <'9'>: Fix formatting. <'0', '@'>: Handle microMIPS. <'^'>: New case. gas/testsuite/ * gas/mips/micromips@mips32-dsp.d: New. * gas/mips/micromips@mips32-dspr2.d: New. * gas/mips/mips32-dsp.d: Remove -mips32r2. * gas/mips/mips32-dspr2.d: Likewise. * gas/mips/mips.exp: (mips_create_arch): Use -mips64r2 for micromips. Use run_dump_test_arches to run dsp tests. opcodes/ * micromips-opc.c (WR_a, RD_a, MOD_a): New macros. (DSP_VOLA): Likewise. (D32, D33): Likewise. (micromips_opcodes): Add DSP ASE instructions. * micromips-dis.c (print_insn_micromips) <'2', '3'>: New cases. <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
Diffstat (limited to 'include')
-rw-r--r--include/opcode/ChangeLog15
-rw-r--r--include/opcode/mips.h50
2 files changed, 47 insertions, 18 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 4b8d300..1091973 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,18 @@
+2012-07-31 Chao-Ying Fu <fu@mips.com>
+ Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Document microMIPS DSP ASE usage.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
+ microMIPS DSP ASE support.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+
2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
* mips.h: Fix a typo in description.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 9232508..857fc71 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1494,6 +1494,24 @@ extern const int bfd_mips16_num_opcodes;
#define MICROMIPSOP_MASK_IMMY 0x1ff
#define MICROMIPSOP_SH_IMMY 1
+/* MIPS DSP ASE */
+#define MICROMIPSOP_MASK_DSPACC 0x3
+#define MICROMIPSOP_SH_DSPACC 14
+#define MICROMIPSOP_MASK_DSPSFT 0x3f
+#define MICROMIPSOP_SH_DSPSFT 16
+#define MICROMIPSOP_MASK_SA3 0x7
+#define MICROMIPSOP_SH_SA3 13
+#define MICROMIPSOP_MASK_SA4 0xf
+#define MICROMIPSOP_SH_SA4 12
+#define MICROMIPSOP_MASK_IMM8 0xff
+#define MICROMIPSOP_SH_IMM8 13
+#define MICROMIPSOP_MASK_IMM10 0x3ff
+#define MICROMIPSOP_SH_IMM10 16
+#define MICROMIPSOP_MASK_WRDSP 0x3f
+#define MICROMIPSOP_SH_WRDSP 14
+#define MICROMIPSOP_MASK_BP 0x3
+#define MICROMIPSOP_SH_BP 14
+
/* Placeholders for fields that only exist in the traditional 32-bit
instruction encoding; see the comment above for details. */
#define MICROMIPSOP_MASK_CODE20 0
@@ -1508,28 +1526,12 @@ extern const int bfd_mips16_num_opcodes;
#define MICROMIPSOP_SH_VECBYTE 0
#define MICROMIPSOP_MASK_VECALIGN 0
#define MICROMIPSOP_SH_VECALIGN 0
-#define MICROMIPSOP_MASK_DSPACC 0
-#define MICROMIPSOP_SH_DSPACC 0
#define MICROMIPSOP_MASK_DSPACC_S 0
#define MICROMIPSOP_SH_DSPACC_S 0
-#define MICROMIPSOP_MASK_DSPSFT 0
-#define MICROMIPSOP_SH_DSPSFT 0
#define MICROMIPSOP_MASK_DSPSFT_7 0
#define MICROMIPSOP_SH_DSPSFT_7 0
-#define MICROMIPSOP_MASK_SA3 0
-#define MICROMIPSOP_SH_SA3 0
-#define MICROMIPSOP_MASK_SA4 0
-#define MICROMIPSOP_SH_SA4 0
-#define MICROMIPSOP_MASK_IMM8 0
-#define MICROMIPSOP_SH_IMM8 0
-#define MICROMIPSOP_MASK_IMM10 0
-#define MICROMIPSOP_SH_IMM10 0
-#define MICROMIPSOP_MASK_WRDSP 0
-#define MICROMIPSOP_SH_WRDSP 0
#define MICROMIPSOP_MASK_RDDSP 0
#define MICROMIPSOP_SH_RDDSP 0
-#define MICROMIPSOP_MASK_BP 0
-#define MICROMIPSOP_SH_BP 0
#define MICROMIPSOP_MASK_MT_U 0
#define MICROMIPSOP_SH_MT_U 0
#define MICROMIPSOP_MASK_MT_H 0
@@ -1702,6 +1704,18 @@ extern const int bfd_mips16_num_opcodes;
"f" 32-bit floating point constant
"l" 32-bit floating point constant in .lit4
+ DSP ASE usage:
+ "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP)
+ "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3)
+ "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4)
+ "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8)
+ "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS)
+ "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC)
+ "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP)
+ "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT)
+ "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
+ "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -1709,8 +1723,8 @@ extern const int bfd_mips16_num_opcodes;
"m" start of microMIPS extension sequence
Characters used so far, for quick reference when adding more:
- "1234567890"
- "<>(),+.\|~"
+ "12345678 0"
+ "<>(),+.@\^|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"