AArch64: Add SVE constraints verifier.

This patch adds the verification rules for move prefix constraints.

The Arm SVE instruction MOVPRFX introduces[1] constraints on the instruction at
PC+4. Particularly the following constraints are handled by this patch

* MOVPRFX must be followed by an instruction.
* MOVPRFX can only be followed by non-layout altering directives.
* MOVPRFX destination register MUST be used as the destination register in the
  instruction at PC+4, and is not allowed to be used in any other position other than
  destructive input.  This includes registers that architecturally overlap. e.g. x1
  should be treated as z1.
* MOVPRFX must be followed by a restricted set of SVE instructions.
* The size of the destination register of MOVPRFX must be equal to that of
  the operation at PC+4.
* The predicate register and operation of MOVPRFX must match that of the instruction
  at PC+4
* The predicated instruction at PC+4 must use the merging predicate.
* Architectural aliases and pseudo-instructions need to be supported as well.
* MOVPRFX cannot be the last instruction in a sequence

Any failure to adhere to any of these constrains will emit an assembly warning
and a disassembly note.

[1] https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a

include/

	* opcode/aarch64.h (aarch64_inst): Remove.
	(enum err_type): Add ERR_VFI.
	(aarch64_is_destructive_by_operands): New.
	(init_insn_sequence): New.
	(aarch64_decode_insn): Remove param name.

opcodes/

	* aarch64-opc.c (init_insn_block): New.
	(verify_constraints, aarch64_is_destructive_by_operands): New.
	* aarch64-opc.h (verify_constraints): New.

gas/

        * config/tc-aarch64.c (output_operand_error_report): Order warnings.

0 files changed, 0 insertions, 0 deletions