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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-05-19 12:19:32 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-05-23 17:41:54 +0200 |
| commit | d9eca1df01c0e6f7f22566c154e63b1df9315790 (patch) | |
| tree | 62db0f1f82fd7eee47f44d2fbff0174895096100 /include/opcode/arc.h | |
| parent | 87789e08e5cb2191af1122ed98af2d6c023b3a0a (diff) | |
| download | gdb-d9eca1df01c0e6f7f22566c154e63b1df9315790.zip gdb-d9eca1df01c0e6f7f22566c154e63b1df9315790.tar.gz gdb-d9eca1df01c0e6f7f22566c154e63b1df9315790.tar.bz2 | |
[ARC] Update instruction type and delay slot info.
This patch corrects the instructioninformation passed into the
disassebler_info structure.
include/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_subclass_t): Add COND.
(flag_class_t): Add F_CLASS_EXTEND.
opcodes/
2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
* arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
information.
(print_insn_arc): Set insn_type information.
* arc-opc.c (C_CC): Add F_CLASS_COND.
* arc-tbl.h (bbit0, bbit1): Update subclass to COND.
(beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
(ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
(breq, breq_s, brge, brhs, brlo, brlt): Likewise.
(brne, brne_s, jeq_s, jne_s): Likewise.
Diffstat (limited to 'include/opcode/arc.h')
| -rw-r--r-- | include/opcode/arc.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 2e5de9c..444341a 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -59,6 +59,7 @@ typedef enum BTSCN, CD1, CD2, + COND, DIV, DP, DPA, @@ -91,7 +92,10 @@ typedef enum /* The conditional code can be extended over the standard variants via .extCondCode pseudo-op. */ - F_CLASS_EXTEND = (1 << 2) + F_CLASS_EXTEND = (1 << 2), + + /* Condition code flag. */ + F_CLASS_COND = (1 << 3) } flag_class_t; /* The opcode table is an array of struct arc_opcode. */ |