From d9eca1df01c0e6f7f22566c154e63b1df9315790 Mon Sep 17 00:00:00 2001 From: Claudiu Zissulescu Date: Thu, 19 May 2016 12:19:32 +0200 Subject: [ARC] Update instruction type and delay slot info. This patch corrects the instructioninformation passed into the disassebler_info structure. include/ 2016-05-23 Claudiu Zissulescu * opcode/arc.h (insn_subclass_t): Add COND. (flag_class_t): Add F_CLASS_EXTEND. opcodes/ 2016-05-23 Claudiu Zissulescu * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type information. (print_insn_arc): Set insn_type information. * arc-opc.c (C_CC): Add F_CLASS_COND. * arc-tbl.h (bbit0, bbit1): Update subclass to COND. (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise. (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise. (breq, breq_s, brge, brhs, brlo, brlt): Likewise. (brne, brne_s, jeq_s, jne_s): Likewise. --- include/opcode/arc.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'include/opcode/arc.h') diff --git a/include/opcode/arc.h b/include/opcode/arc.h index 2e5de9c..444341a 100644 --- a/include/opcode/arc.h +++ b/include/opcode/arc.h @@ -59,6 +59,7 @@ typedef enum BTSCN, CD1, CD2, + COND, DIV, DP, DPA, @@ -91,7 +92,10 @@ typedef enum /* The conditional code can be extended over the standard variants via .extCondCode pseudo-op. */ - F_CLASS_EXTEND = (1 << 2) + F_CLASS_EXTEND = (1 << 2), + + /* Condition code flag. */ + F_CLASS_COND = (1 << 3) } flag_class_t; /* The opcode table is an array of struct arc_opcode. */ -- cgit v1.1