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| author | Yixuan Chen <chenyixuan@iscas.ac.cn> | 2024-07-04 17:16:59 +0800 |
|---|---|---|
| committer | Vladimir Mezentsev <vladimir.mezentsev@oracle.com> | 2024-07-10 15:16:03 -0700 |
| commit | 762c38d552abbfed97c349c5e7c8ef34119b2f5e (patch) | |
| tree | f0b1d2e5cf0b78204d6ab4d0f8c7dd8c9512a5b7 /gprofng/common/gp-defs.h | |
| parent | 479edf0a6a61159486f14d5e62403f8769cc591d (diff) | |
| download | gdb-762c38d552abbfed97c349c5e7c8ef34119b2f5e.zip gdb-762c38d552abbfed97c349c5e7c8ef34119b2f5e.tar.gz gdb-762c38d552abbfed97c349c5e7c8ef34119b2f5e.tar.bz2 | |
RISC-V:[gprofng] Minimal support gprofng for riscv.
ChangeLog: Add target riscv to --enable-gprofng.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* configure: Add riscv.
* configure.ac: Add riscv.
gprofng/ChangeLog: Minimal support gprofng for riscv.
2024-07-04 Yixuan Chen <chenyixuan@iscas.ac.cn>
* gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.
(defined): Add riscv.
* gprofng/common/cpuid.c (defined): Add risc-v hwprobe.
* gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.
(defined): Add riscv.
(ARCH_RISCV): Add riscv.
* gprofng/common/hwc_cpus.h: Add RISC-V vendor.
* gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.
* gprofng/configure: Add riscv.
* gprofng/configure.ac: Add riscv.
* gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.
(CONTEXT_PC): Add RISC-V register.
(CONTEXT_FP): Add RISC-V register.
(CONTEXT_SP): Add RISC-V register.
(SETFUNCTIONCONTEXT):
* gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.
* gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.
* gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.
(GET_PC): Add RISC-V register.
(GET_SP): Add RISC-V register.
(GET_FP): Add RISC-V register.
(FILL_CONTEXT):
* gprofng/src/DbeSession.cc (ARCH): Add RISC-V.
* gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.
* gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.
* gprofng/src/checks.cc (ARCH): Add RISC-V.
* gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.
(read_cpuinfo): Add "mvendorid" condition according to risc-v /proc/cpuinfo file content.
* gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.
Diffstat (limited to 'gprofng/common/gp-defs.h')
| -rw-r--r-- | gprofng/common/gp-defs.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/gprofng/common/gp-defs.h b/gprofng/common/gp-defs.h index a1c1f05..e0471f3 100644 --- a/gprofng/common/gp-defs.h +++ b/gprofng/common/gp-defs.h @@ -32,6 +32,7 @@ */ #define ARCH(x) TOK_A_##x(ARCH) #define TOK_A_Aarch64(x) x##_Aarch64 +#define TOK_A_RISCV(x) x##_RISCV #define TOK_A_SPARC(x) x##_SPARC #define TOK_A_Intel(x) x##_Intel @@ -45,11 +46,13 @@ #define ARCH_Intel 1 #elif defined(__aarch64__) #define ARCH_Aarch64 1 +#elif defined(__riscv) +#define ARCH_RISCV 1 #else #error "Undefined platform" #endif -#if defined(__sparcv9) || defined(__x86_64) || defined(__aarch64__) +#if defined(__sparcv9) || defined(__x86_64) || defined(__aarch64__) || defined(__riscv) #define WSIZE_64 1 #else #define WSIZE_32 1 |