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| author | Alan Hayward <alan.hayward@arm.com> | 2018-06-01 16:02:37 +0100 |
|---|---|---|
| committer | Alan Hayward <alan.hayward@arm.com> | 2018-06-01 16:35:18 +0100 |
| commit | 739e8682ff1cffc2809c91853efeef232d29e582 (patch) | |
| tree | bc11c803c5d43c2c0bdaeab1413fd45a31c0c7e9 /gdb/arch | |
| parent | 3a00b02d277023ccfc5ccba3fcd4bae7aa485a49 (diff) | |
| download | gdb-739e8682ff1cffc2809c91853efeef232d29e582.zip gdb-739e8682ff1cffc2809c91853efeef232d29e582.tar.gz gdb-739e8682ff1cffc2809c91853efeef232d29e582.tar.bz2 | |
Add SVE register defines
In order to prevent gaps in the register numbering, the Z registers
reuse the V register numbers (which become pseudos on SVE).
2018-06-01 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (aarch64_sve_register_names): New const
var.
* arch/aarch64.h (enum aarch64_regnum): Add SVE entries.
(AARCH64_SVE_Z_REGS_NUM): New define.
(AARCH64_SVE_P_REGS_NUM): Likewise.
(AARCH64_SVE_NUM_REGS): Likewise.
Diffstat (limited to 'gdb/arch')
| -rw-r--r-- | gdb/arch/aarch64.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h index 2f80a29..30f5360 100644 --- a/gdb/arch/aarch64.h +++ b/gdb/arch/aarch64.h @@ -28,7 +28,9 @@ target_desc *aarch64_create_target_description (long vq); -/* Register numbers of various important registers. */ +/* Register numbers of various important registers. + Note that on SVE, the Z registers reuse the V register numbers and the V + registers become pseudo registers. */ enum aarch64_regnum { AARCH64_X0_REGNUM, /* First integer register. */ @@ -39,8 +41,15 @@ enum aarch64_regnum AARCH64_CPSR_REGNUM, /* Current Program Status Register. */ AARCH64_V0_REGNUM, /* First fp/vec register. */ AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */ + AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */ + AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */ AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */ AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */ + AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */ + AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate + register. */ + AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */ + AARCH64_SVE_VG_REGNUM, /* SVE Vector Gradient. */ /* Other useful registers. */ AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7, @@ -50,7 +59,11 @@ enum aarch64_regnum #define AARCH64_X_REGS_NUM 31 #define AARCH64_V_REGS_NUM 32 +#define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM +#define AARCH64_SVE_P_REGS_NUM 16 #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1 +#define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1 + /* There are a number of ways of expressing the current SVE vector size: |