diff options
| -rw-r--r-- | gdb/ChangeLog | 9 | ||||
| -rw-r--r-- | gdb/aarch64-tdep.c | 21 | ||||
| -rw-r--r-- | gdb/arch/aarch64.h | 15 |
3 files changed, 44 insertions, 1 deletions
diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 8af7e67..37656ad 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,12 @@ +2018-06-01 Alan Hayward <alan.hayward@arm.com> + + * aarch64-tdep.c (aarch64_sve_register_names): New const + var. + * arch/aarch64.h (enum aarch64_regnum): Add SVE entries. + (AARCH64_SVE_Z_REGS_NUM): New define. + (AARCH64_SVE_P_REGS_NUM): Likewise. + (AARCH64_SVE_NUM_REGS): Likewise. + 2018-05-31 Uros Bizjak <ubizjak@gmail.com> * nat/linux-ptrace.h [__alpha__] diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 793b42a..1cd2015 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -156,6 +156,27 @@ static const char *const aarch64_v_register_names[] = "fpcr" }; +/* The SVE 'Z' and 'P' registers. */ +static const char *const aarch64_sve_register_names[] = +{ + /* These registers must appear in consecutive RAW register number + order and they must begin with AARCH64_SVE_Z0_REGNUM! */ + "z0", "z1", "z2", "z3", + "z4", "z5", "z6", "z7", + "z8", "z9", "z10", "z11", + "z12", "z13", "z14", "z15", + "z16", "z17", "z18", "z19", + "z20", "z21", "z22", "z23", + "z24", "z25", "z26", "z27", + "z28", "z29", "z30", "z31", + "fpsr", "fpcr", + "p0", "p1", "p2", "p3", + "p4", "p5", "p6", "p7", + "p8", "p9", "p10", "p11", + "p12", "p13", "p14", "p15", + "ffr", "vg" +}; + /* AArch64 prologue cache structure. */ struct aarch64_prologue_cache { diff --git a/gdb/arch/aarch64.h b/gdb/arch/aarch64.h index 2f80a29..30f5360 100644 --- a/gdb/arch/aarch64.h +++ b/gdb/arch/aarch64.h @@ -28,7 +28,9 @@ target_desc *aarch64_create_target_description (long vq); -/* Register numbers of various important registers. */ +/* Register numbers of various important registers. + Note that on SVE, the Z registers reuse the V register numbers and the V + registers become pseudo registers. */ enum aarch64_regnum { AARCH64_X0_REGNUM, /* First integer register. */ @@ -39,8 +41,15 @@ enum aarch64_regnum AARCH64_CPSR_REGNUM, /* Current Program Status Register. */ AARCH64_V0_REGNUM, /* First fp/vec register. */ AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */ + AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */ + AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */ AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */ AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */ + AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */ + AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate + register. */ + AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */ + AARCH64_SVE_VG_REGNUM, /* SVE Vector Gradient. */ /* Other useful registers. */ AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7, @@ -50,7 +59,11 @@ enum aarch64_regnum #define AARCH64_X_REGS_NUM 31 #define AARCH64_V_REGS_NUM 32 +#define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM +#define AARCH64_SVE_P_REGS_NUM 16 #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1 +#define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1 + /* There are a number of ways of expressing the current SVE vector size: |