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| author | Alan Hayward <alan.hayward@arm.com> | 2018-06-01 16:02:37 +0100 |
|---|---|---|
| committer | Alan Hayward <alan.hayward@arm.com> | 2018-06-01 16:35:18 +0100 |
| commit | 739e8682ff1cffc2809c91853efeef232d29e582 (patch) | |
| tree | bc11c803c5d43c2c0bdaeab1413fd45a31c0c7e9 /gdb/aarch64-tdep.c | |
| parent | 3a00b02d277023ccfc5ccba3fcd4bae7aa485a49 (diff) | |
| download | gdb-739e8682ff1cffc2809c91853efeef232d29e582.zip gdb-739e8682ff1cffc2809c91853efeef232d29e582.tar.gz gdb-739e8682ff1cffc2809c91853efeef232d29e582.tar.bz2 | |
Add SVE register defines
In order to prevent gaps in the register numbering, the Z registers
reuse the V register numbers (which become pseudos on SVE).
2018-06-01 Alan Hayward <alan.hayward@arm.com>
* aarch64-tdep.c (aarch64_sve_register_names): New const
var.
* arch/aarch64.h (enum aarch64_regnum): Add SVE entries.
(AARCH64_SVE_Z_REGS_NUM): New define.
(AARCH64_SVE_P_REGS_NUM): Likewise.
(AARCH64_SVE_NUM_REGS): Likewise.
Diffstat (limited to 'gdb/aarch64-tdep.c')
| -rw-r--r-- | gdb/aarch64-tdep.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 793b42a..1cd2015 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -156,6 +156,27 @@ static const char *const aarch64_v_register_names[] = "fpcr" }; +/* The SVE 'Z' and 'P' registers. */ +static const char *const aarch64_sve_register_names[] = +{ + /* These registers must appear in consecutive RAW register number + order and they must begin with AARCH64_SVE_Z0_REGNUM! */ + "z0", "z1", "z2", "z3", + "z4", "z5", "z6", "z7", + "z8", "z9", "z10", "z11", + "z12", "z13", "z14", "z15", + "z16", "z17", "z18", "z19", + "z20", "z21", "z22", "z23", + "z24", "z25", "z26", "z27", + "z28", "z29", "z30", "z31", + "fpsr", "fpcr", + "p0", "p1", "p2", "p3", + "p4", "p5", "p6", "p7", + "p8", "p9", "p10", "p11", + "p12", "p13", "p14", "p15", + "ffr", "vg" +}; + /* AArch64 prologue cache structure. */ struct aarch64_prologue_cache { |