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authorNick Clifton <nickc@redhat.com>2009-12-17 09:52:18 +0000
committerNick Clifton <nickc@redhat.com>2009-12-17 09:52:18 +0000
commitff4a8d2b939133ea12e8994ff1f83d3a8e17baa2 (patch)
tree8c2067c8669ec9c306998941830cb370617d77ad /gas
parent32af9f6e558c4f6bb55d36a317d2ec43b29d4bb6 (diff)
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PR binutils/10924
* config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.
Diffstat (limited to 'gas')
-rw-r--r--gas/ChangeLog8
-rw-r--r--gas/config/tc-arm.c4
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/arm/unpredictable.d10
-rw-r--r--gas/testsuite/gas/arm/unpredictable.s48
5 files changed, 47 insertions, 29 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index c6b68fd..73d5f21 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,11 @@
+2009-12-17 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/10924
+ * config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination
+ register.
+ (do_mrs): Likewise.
+ (do_mul): Likewise.
+
2009-12-16 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (process_suffix): Set i.suffix to 0 in
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 65d81a9..c88e5f8 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -7506,6 +7506,7 @@ do_ldstt (void)
static void
do_ldstv4 (void)
{
+ constraint (inst.operands[0].reg == REG_PC, BAD_PC);
inst.instruction |= inst.operands[0].reg << 12;
if (!inst.operands[1].isreg)
if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
@@ -7671,6 +7672,7 @@ do_mrs (void)
constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
!= (PSR_c|PSR_f),
_("'CPSR' or 'SPSR' expected"));
+ constraint (inst.operands[0].reg == REG_PC, BAD_PC);
inst.instruction |= inst.operands[0].reg << 12;
inst.instruction |= (inst.operands[1].imm & SPSR_BIT);
}
@@ -7699,6 +7701,8 @@ do_msr (void)
static void
do_mul (void)
{
+ constraint (inst.operands[2].reg == REG_PC, BAD_PC);
+
if (!inst.operands[2].present)
inst.operands[2].reg = inst.operands[0].reg;
inst.instruction |= inst.operands[0].reg << 16;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e8b4372..bad0ab9 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2009-12-17 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/10924
+ * gas/arm/unpredictable.s: Add more unpredictable instructions.
+ * gas/arm/unpredictable.d: Add expected disassemblies.
+
2009-12-14 Nick Clifton <nickc@redhat.com>
PR binutils/10924
diff --git a/gas/testsuite/gas/arm/unpredictable.d b/gas/testsuite/gas/arm/unpredictable.d
index 4b7e801..8cba074 100644
--- a/gas/testsuite/gas/arm/unpredictable.d
+++ b/gas/testsuite/gas/arm/unpredictable.d
@@ -64,5 +64,13 @@ Disassembly of section .text:
0+0e4 <[^>]+> [^<]+<UNPREDICTABLE>
0+0e8 <[^>]+> [^<]+<UNPREDICTABLE>
0+0ec <[^>]+> [^<]+<UNPREDICTABLE>
+0+0f0 <[^>]+> [^<]+<UNPREDICTABLE>
+0+0f4 <[^>]+> [^<]+<UNPREDICTABLE>
+0+0f8 <[^>]+> [^<]+<UNPREDICTABLE>
+0+0fc <[^>]+> [^<]+<UNPREDICTABLE>
+0+100 <[^>]+> [^<]+<UNPREDICTABLE>
+0+104 <[^>]+> [^<]+<UNPREDICTABLE>
+0+108 <[^>]+> [^<]+<UNPREDICTABLE>
+0+10c <[^>]+> [^<]+<UNPREDICTABLE>
+0+110 <[^>]+> e1a00000[ ]+nop[ ]+; \(mov r0, r0\)
#pass
-
diff --git a/gas/testsuite/gas/arm/unpredictable.s b/gas/testsuite/gas/arm/unpredictable.s
index 36cfce9..7849676 100644
--- a/gas/testsuite/gas/arm/unpredictable.s
+++ b/gas/testsuite/gas/arm/unpredictable.s
@@ -19,42 +19,36 @@ unpredictable:
.word 0xe93f0004 @ ldmdb r15!, { r2 }
.word 0xe83f0008 @ ldmda pc!, { r3 }
- ldrb pc, [r0, r1]
- ldrbt pc, [r0], r1
- ldrh pc, [r0, r1]
- ldrsb pc, [r0, r1]
- ldrsb pc, [r0], -r0
- ldrsh pc, [r0, r1]
- ldrt pc, [r0], r1
+ .word 0xe7d0f001 @ ldrb pc, [r0, r1]
+ .word 0xe6f0f001 @ ldrbt pc, [r0], r1
+ .word 0xe190f0b1 @ ldrh pc, [r0, r1]
+ .word 0xe190f0d1 @ ldrsb pc, [r0, r1]
+ .word 0xe010f0d0 @ ldrsb pc, [r0], -r0
+ .word 0xe190f0f1 @ ldrsh pc, [r0, r1]
+ .word 0xe6b0f001 @ ldrt pc, [r0], r1
.word 0xe020f291 @ mla r0, r1, r2, pc
.word 0xe0202f91 @ mla r0, r1, pc, r2
.word 0xe020219f @ mla r0, pc, r1, r2
.word 0xe02f2190 @ mla pc, r0, r1, r2
- @ .word 0xe0202190 @ mla r0, r0, r1, r2
- mrs pc, cpsr
+ .word 0xe10ff000 @ mrs pc, cpsr
- mul r0, r1, pc
+ .word 0xe0000f91 @ mul r0, r1, pc
.word 0xe001009f @ mul r0, pc, r1
.word 0xe00f0091 @ mul pc, r1, r0
- @ .word 0xe0010091 @ mul r1, r1, r0
.word 0xe0e21f93 @ smlal r1, r2, r3, pc
.word 0xe0e2149f @ smlal r1, r2, pc, r4
.word 0xe0ef1493 @ smlal r1, pc, r3, r4
.word 0xe0e2f493 @ smlal pc, r2, r3, r4
- @ .word 0xe0e11493 @ smlal r1, r1, r3, r4
- @ .word 0xe0e21492 @ smlal r1, r2, r2, r4
- @ .word 0xe0e21491 @ smlal r1, r2, r1, r4
+ .word 0xe0e11493 @ smlal r1, r1, r3, r4
.word 0xe0c21f93 @ smull r1, r2, r3, pc
.word 0xe0c2149f @ smull r1, r2, pc, r4
.word 0xe0cf1493 @ smull r1, pc, r3, r4
.word 0xe0c2f493 @ smull pc, r2, r3, r4
- @ .word 0xe0c11493 @ smull r1, r1, r3, r4
- @ .word 0xe0c21492 @ smull r1, r2, r2, r4
- @ .word 0xe0c21491 @ smull r1, r2, r1, r4
+ .word 0xe0c11493 @ smull r1, r1, r3, r4
.word 0xe98f0004 @ stmib r15, { r2 }
.word 0xe88f0008 @ stmia r15, { r3 }
@@ -63,32 +57,30 @@ unpredictable:
strb pc, [r0, r1]
strbt pc, [r0], r1
- strh pc, [r0, r1]
+ .word 0xe180f0b1 @ strh pc, [r0, r1]
.word 0xe103f092 @ swp r15, r2, [r3]
.word 0xe103109f @ swp r1, r15, [r3]
.word 0xe10f1092 @ swp r1, r2, [r15]
- @ .word 0xe1031093 @ swp r1, r3, [r3]
- @ .word 0xe1033092 @ swp r3, r2, [r3]
+ .word 0xe1031093 @ swp r1, r3, [r3]
+ .word 0xe1033092 @ swp r3, r2, [r3]
.word 0xe143f092 @ swpb r15, r2, [r3]
.word 0xe143109f @ swpb r1, r15, [r3]
.word 0xe14f1092 @ swpb r1, r2, [r15]
- @ .word 0xe1431093 @ swpb r1, r3, [r3]
- @ .word 0xe1433092 @ swpb r3, r2, [r3]
+ .word 0xe1431093 @ swpb r1, r3, [r3]
+ .word 0xe1433092 @ swpb r3, r2, [r3]
.word 0xe0a21f93 @ umlal r1, r2, r3, r15
.word 0xe0a2149f @ umlal r1, r2, r15, r4
.word 0xe0af1493 @ umlal r1, r15, r3, r4
.word 0xe0a2f493 @ umlal r15, r2, r3, r4
- @ .word 0xe0a11493 @ umlal r1, r1, r3, r4
- @ .word 0xe0a21491 @ umlal r1, r2, r1, r4
- @ .word 0xe0a21492 @ umlal r1, r2, r2, r4
+ .word 0xe0a11493 @ umlal r1, r1, r3, r4
.word 0xe0821f93 @ umull r1, r2, r3, r15
.word 0xe082149f @ umull r1, r2, r15, r4
.word 0xe08f1493 @ umull r1, r15, r3, r4
.word 0xe082f493 @ umull r15, r2, r3, r4
- @ .word 0xe0811493 @ umull r1, r1, r3, r4
- @ .word 0xe0821491 @ umull r1, r2, r1, r4
- @ .word 0xe0821492 @ umull r1, r2, r2, r4
+ .word 0xe0811493 @ umull r1, r1, r3, r4
+
+ nop @ Marker to indicated end of unpredictable insns.
generated by cgit v1.1 at 2024-08-09 02:29:46 +0000