aboutsummaryrefslogtreecommitdiff
path: root/gas
diff options
context:
space:
mode:
authorRenlin Li <renlin.li@arm.com>2015-04-15 17:44:03 +0100
committerJiong Wang <jiong.wang@arm.com>2015-04-15 17:44:03 +0100
commitf0fba320ab5effaff5255b5526a37f0987637e3e (patch)
treee4ab43f2d1f1ddf54122d348fe41d343fa6b79d3 /gas
parent6282837972a5c7b89968319caf821fcbd2a166bb (diff)
downloadgdb-f0fba320ab5effaff5255b5526a37f0987637e3e.zip
gdb-f0fba320ab5effaff5255b5526a37f0987637e3e.tar.gz
gdb-f0fba320ab5effaff5255b5526a37f0987637e3e.tar.bz2
[ARM] Disassembles SSAT and SSAT16 instructions incorrectly for Thumb-2
2015-04-15 Renlin Li <renlin.li@arm.com> opcodes/: * arm-dis.c (thumb32_opcodes): Define 'D' format control code, use it for ssat and ssat16. (print_insn_thumb32): Add handle case for 'D' control code. gas/testsuite/: * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field. * gas/arm/thumb32.d: Likewise.
Diffstat (limited to 'gas')
-rw-r--r--gas/testsuite/ChangeLog5
-rw-r--r--gas/testsuite/gas/arm/arch7em.d8
-rw-r--r--gas/testsuite/gas/arm/thumb32.d24
3 files changed, 21 insertions, 16 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 6076b89..ea6a87a 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2015-04-15 Renlin Li <renlin.li@arm.com>
+
+ * gas/arm/arch7em.d: Adjust required ssat and ssat16 immediate field.
+ * gas/arm/thumb32.d: Likewise.
+
2015-04-14 Nick Clifton <nickc@redhat.com>
* gas/lns/lns.exp: Add RL78 to list of targets using
diff --git a/gas/testsuite/gas/arm/arch7em.d b/gas/testsuite/gas/arm/arch7em.d
index cd1f939..9e3e286 100644
--- a/gas/testsuite/gas/arm/arch7em.d
+++ b/gas/testsuite/gas/arm/arch7em.d
@@ -115,10 +115,10 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0
0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0
0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0
-0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0
-0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9
+0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #10, r0
+0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #1, r9
0[0-9a-f]+ <[^>]+> f3a0 0000 usat16 r0, #0, r0
0[0-9a-f]+ <[^>]+> f3a0 0900 usat16 r9, #0, r0
0[0-9a-f]+ <[^>]+> f3a0 0009 usat16 r0, #9, r0
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 9fd5f24..8e593a5 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -895,18 +895,18 @@ Disassembly of section .text:
0[0-9a-f]+ <[^>]+> fb40 f000 smusd r0, r0, r0
0[0-9a-f]+ <[^>]+> fb40 f010 smusdx r0, r0, r0
0[0-9a-f]+ <[^>]+> fb70 f000 usad8 r0, r0, r0
-0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0900 ssat r9, #0, r0
-0[0-9a-f]+ <[^>]+> f300 0011 ssat r0, #17, r0
-0[0-9a-f]+ <[^>]+> f309 0000 ssat r0, #0, r9
-0[0-9a-f]+ <[^>]+> f300 7000 ssat r0, #0, r0, lsl #28
-0[0-9a-f]+ <[^>]+> f320 00c0 ssat r0, #0, r0, asr #3
-0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #0, r0
-0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #9, r0
-0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #0, r9
+0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0000 ssat r0, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0900 ssat r9, #1, r0
+0[0-9a-f]+ <[^>]+> f300 0011 ssat r0, #18, r0
+0[0-9a-f]+ <[^>]+> f309 0000 ssat r0, #1, r9
+0[0-9a-f]+ <[^>]+> f300 7000 ssat r0, #1, r0, lsl #28
+0[0-9a-f]+ <[^>]+> f320 00c0 ssat r0, #1, r0, asr #3
+0[0-9a-f]+ <[^>]+> f320 0000 ssat16 r0, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0900 ssat16 r9, #1, r0
+0[0-9a-f]+ <[^>]+> f320 0009 ssat16 r0, #10, r0
+0[0-9a-f]+ <[^>]+> f329 0000 ssat16 r0, #1, r9
0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0
0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0
0[0-9a-f]+ <[^>]+> f380 0000 usat r0, #0, r0