[BINUTILS, AARCH64, 5/8] Add Tag getting instruction in Memory Tagging Extension

This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions which is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.

This patch add support to the Tag Getting instruction from Memory Tagging
Extension.
- LDG <Xt>, [<Xn|SP>, #<simm>]

where
<Xt> : Is the 64-bit destination GPR.
<Xn|SP> : Is the 64-bit first source GPR or Stack pointer.
<simm> : Is the optional signed immediate offset, a multiple of 16
in the range of -4096 and 4080, defaulting to 0.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (QL_LDG): New.
	(aarch64_opcode_table): Add ldg.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.

5 files changed, 33 insertions, 1 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 57a3c38..eead118 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,12 @@
 2018-11-12  Sudakshina Das  <sudi.das@arm.com>
 
+	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Add tests for ldg.
+	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Likewise.
+	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
+	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
+
+2018-11-12  Sudakshina Das  <sudi.das@arm.com>
+
 	* config/tc-aarch64.c (parse_operands): Add switch case for
 	AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
 	(fix_insn): Likewise.
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
index 4140646..363bbe2 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d
@@ -113,3 +113,11 @@ Disassembly of section \.text:
 .*:	69207c00 	stgp	x0, xzr, \[x0, #-1024\]
 .*:	699f83e0 	stgp	x0, x0, \[sp, #1008\]!
 .*:	68a003e0 	stgp	x0, x0, \[sp\], #-1024
+.*:	d9600000 	ldg	x0, \[x0\]
+.*:	d960001b 	ldg	x27, \[x0\]
+.*:	d9600360 	ldg	x0, \[x27\]
+.*:	d960037b 	ldg	x27, \[x27\]
+.*:	d96003e0 	ldg	x0, \[sp\]
+.*:	d960001f 	ldg	xzr, \[x0\]
+.*:	d96ff000 	ldg	x0, \[x0, #4080\]
+.*:	d9700000 	ldg	x0, \[x0, #-4096\]
diff --git a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
index 729dae6..62c9436 100644
--- a/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
+++ b/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s
@@ -89,3 +89,12 @@ func:
 	stgp x0, xzr, [x0, #-1024]
 	stgp x0, x0, [sp, #1008]!
 	stgp x0, x0, [sp], #-1024
+
+	ldg x0, [x0, #0]
+	ldg x27, [x0, #0]
+	ldg x0, [x27, #0]
+	ldg x27, [x27, #0]
+	ldg x0, [sp, #0]
+	ldg xzr, [x0, #0]
+	ldg x0, [x0, #4080]
+	ldg x0, [x0, #-4096]
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index dd568cc..dfdf00a 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -7,6 +7,8 @@
 [^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 1 -- `stg \[x1,#15\]'
 [^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `stzg \[x1,#-4097]!'
 [^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 1 -- `st2g \[x1],#4096'
+[^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 2 -- `ldg x1,\[x2,#33\]'
+[^:]*:[0-9]+: Error: immediate offset out of range -4096 to 4080 at operand 2 -- `ldg x1,\[x2,#4112\]'
 [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#1009\]'
 [^:]*:[0-9]+: Error: immediate value must be a multiple of 16 at operand 3 -- `stgp x1,x2,\[x3,#33\]'
 [^:]*:[0-9]+: Error: immediate offset out of range -1024 to 1008 at operand 3 -- `stgp x1,x2,\[x3,#-1025\]'
@@ -33,3 +35,5 @@
 [^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
 [^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
 [^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 3 -- `stgp x0,x0,\[xzr\]'
+[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
+[^:]*:[0-9]+: Error: 64-bit integer or SP register expected at operand 2 -- `ldg x0,\[xzr,#16\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.s b/gas/testsuite/gas/aarch64/illegal-memtag.s
index 2a66366..35d1b12 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.s
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.s
@@ -8,10 +8,12 @@ func:
 	addg x1, x2, #0x3f0, #0x10
 	subg x1, x2, #0x3f0, -4
 
-	# STG/STZG/ST2G : Fail imm
+	# STG/STZG/ST2G/LDG : Fail imm
 	stg [x1, #15]
 	stzg [x1, #-4097]!
 	st2g [x1], #4096
+	ldg x1, [x2, #33]
+	ldg x1, [x2, #4112]
 
 	# STGP : Fail imm
 	stgp x1, x2, [x3, #1009]
@@ -42,3 +44,5 @@ func:
 	stgp sp, x2, [x3]
 	stgp x1, sp, [x3]
 	stgp x0, x0, [xzr]
+	ldg sp, [x0, #16]
+	ldg x0, [xzr, #16]