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| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:36:23 +0800 |
|---|---|---|
| committer | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-08-29 20:43:19 +0800 |
| commit | bd782c07b914f28fd927cec42eacd8adcf556dca (patch) | |
| tree | 5fe589fdb8177e2471661eca4f913e6a9616630c /gas | |
| parent | ac8cb70f3690b4eace1325c7ff918dce9073da7c (diff) | |
| download | gdb-bd782c07b914f28fd927cec42eacd8adcf556dca.zip gdb-bd782c07b914f28fd927cec42eacd8adcf556dca.tar.gz gdb-bd782c07b914f28fd927cec42eacd8adcf556dca.tar.bz2 | |
[MIPS] Add Loongson 3A2000/3A3000 proccessor support.
bfd/
* archures.c (bfd_architecture): New machine
bfd_mach_mips_gs464e.
* bfd-in2.h (bfd_architecture): Likewise.
* cpu-mips.c (enum I_xxx): Likewise.
(arch_info_struct): Likewise.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle
E_MIPS_MACH_GS464E.
(mips_set_isa_flags): Likewise.
(mips_mach_extensions): Map bfd_mach_mips_gs464e to
bfd_mach_mips_gs464 extension.
binutils/
* NEWS: Mention Loongson 3A2000/3A3000 proccessor support.
* readelf.c (get_machine_flags): Handle gs464e.
elfcpp/
* mips.c (EF_MIPS_MACH): New E_MIPS_MACH_GS464E.
gas/
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E.
(mips_cpu_info_table): Add gs464e descriptors.
* doc/as.texi (march table): Add gs464e.
include/
* elf/mips.h (E_MIPS_MACH_XXX): New E_MIPS_MACH_GS464E.
* opcode/mips.h (CPU_XXX): New CPU_GS464E.
ld/
* testsuite/ld-mips-elf/mips-elf-flags.exp: Run good_combination
gs464e and gs464.
opcodes/
* mips-dis.c (mips_arch_choices): Add gs464e descriptors.
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/ChangeLog | 6 | ||||
| -rw-r--r-- | gas/config/tc-mips.c | 5 | ||||
| -rw-r--r-- | gas/doc/c-mips.texi | 1 |
3 files changed, 11 insertions, 1 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index f5e0bad..a9413fa 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Exclude CPU_GS464E. + (mips_cpu_info_table): Add gs464e descriptors. + * doc/as.texi (march table): Add gs464e. + +2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com> + * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 0847875..9c0a1fd 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -422,7 +422,8 @@ static int mips_32bitmode = 0; || (ISA) == ISA_MIPS64R5 \ || (ISA) == ISA_MIPS64R6 \ || (CPU) == CPU_R5900) \ - && (CPU) != CPU_GS464) + && ((CPU) != CPU_GS464 \ + || (CPU) != CPU_GS464E)) /* Return true if ISA supports move to/from high part of a 64-bit floating-point register. */ @@ -19814,6 +19815,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] = ISA_MIPS64R2, CPU_GS464 }, { "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT, ISA_MIPS64R2, CPU_GS464 }, + { "gs464e", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT + | ASE_LOONGSON_EXT2, ISA_MIPS64R2, CPU_GS464E }, /* Cavium Networks Octeon CPU core */ { "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON }, diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 2152164..2682e36 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -438,6 +438,7 @@ p6600, loongson2e, loongson2f, gs464, +gs464e, octeon, octeon+, octeon2, |