Add support for .extInstruction pseudo-op.

gas/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* testsuite/gas/arc/textinsn-errors.d: New File.
	* testsuite/gas/arc/textinsn-errors.err: Likewise.
	* testsuite/gas/arc/textinsn-errors.s: Likewise.
	* testsuite/gas/arc/textinsn2op.d: Likewise.
	* testsuite/gas/arc/textinsn2op.s: Likewise.
	* testsuite/gas/arc/textinsn2op01.d: Likewise.
	* testsuite/gas/arc/textinsn2op01.s: Likewise.
	* testsuite/gas/arc/textinsn3op.d: Likewise.
	* testsuite/gas/arc/textinsn3op.s: Likewise.
	* doc/c-arc.texi (ARC Directives): Add .extInstruction
	documentation.
	* config/tc-arc.c (arcext_section): New variable.
	(arc_extinsn): New function.
	(md_pseudo_table): Add .extInstruction pseudo op.
	(attributes_t): New type.
	(suffixclass, syntaxclass, syntaxclassmod): New constant
	structures.
	(find_opcode_match): Remove arc_num_opcodes.
	(md_begin): Likewise.
	(tokenize_extinsn): New function.
	(arc_set_ext_seg): Likewise.
	(create_extinst_section): Likewise.

include/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* opcode/arc.h (arc_num_opcodes): Remove.
	(ARC_SYNTAX_3OP, ARC_SYNTAX_2OP, ARC_OP1_MUST_BE_IMM)
	(ARC_OP1_IMM_IMPLIED, ARC_SUFFIX_NONE, ARC_SUFFIX_COND)
	(ARC_SUFFIX_FLAG): Define.
	(flags_none, flags_f, flags_cc, flags_ccf): Declare.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.

opcodes/
2016-04-04  Claudiu Zissulescu  <claziss@synopsys.com>

	* arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
	Initialize.
	(arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
	(arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
	(arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
	(arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
	(arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
	(arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
	(arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
	(arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
	(arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
	(arc_opcode arc_opcodes): Null terminate the array.
	(arc_num_opcodes): Remove.
	* arc-ext.h (INSERT_XOP): Define.
	(extInstruction_t): Likewise.
	(arcExtMap_instName): Delete.
	(arcExtMap_insn): New function.
	(arcExtMap_genOpcode): Likewise.
	* arc-ext.c (ExtInstruction): Remove.
	(create_map): Zero initialize instruction fields.
	(arcExtMap_instName): Remove.
	(arcExtMap_insn): New function.
	(dump_ARC_extmap): More info while debuging.
	(arcExtMap_genOpcode): New function.
	* arc-dis.c (find_format): New function.
	(print_insn_arc): Use find_format.
	(arc_get_disassembler): Enable dump_ARC_extmap only when
	debugging.

Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>

12 files changed, 699 insertions, 36 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5173312..688ffde 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,30 @@
 2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
 
+	* testsuite/gas/arc/textinsn-errors.d: New File.
+	* testsuite/gas/arc/textinsn-errors.err: Likewise.
+	* testsuite/gas/arc/textinsn-errors.s: Likewise.
+	* testsuite/gas/arc/textinsn2op.d: Likewise.
+	* testsuite/gas/arc/textinsn2op.s: Likewise.
+	* testsuite/gas/arc/textinsn2op01.d: Likewise.
+	* testsuite/gas/arc/textinsn2op01.s: Likewise.
+	* testsuite/gas/arc/textinsn3op.d: Likewise.
+	* testsuite/gas/arc/textinsn3op.s: Likewise.
+	* doc/c-arc.texi (ARC Directives): Add .extInstruction
+	documentation.
+	* config/tc-arc.c (arcext_section): New variable.
+	(arc_extinsn): New function.
+	(md_pseudo_table): Add .extInstruction pseudo op.
+	(attributes_t): New type.
+	(suffixclass, syntaxclass, syntaxclassmod): New constant
+	structures.
+	(find_opcode_match): Remove arc_num_opcodes.
+	(md_begin): Likewise.
+	(tokenize_extinsn): New function.
+	(arc_set_ext_seg): Likewise.
+	(create_extinst_section): Likewise.
+
+2016-04-12  Claudiu Zissulescu  <claziss@synopsys.com>
+
 	* config/tc-arc.c (preprocess_operands): Mark AUX symbol.
 	(arc_adjust_symtab): New function.
 	* config/tc-arc.h (ARC_FLAG_AUX): Define.
diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c
index 98cac6a..3aeedb1 100644
--- a/gas/config/tc-arc.c
+++ b/gas/config/tc-arc.c
@@ -29,6 +29,7 @@
 
 #include "opcode/arc.h"
 #include "elf/arc.h"
+#include "../opcodes/arc-ext.h"
 
 /* Defines section.  */
 
@@ -126,6 +127,9 @@ extern int target_big_endian;
 const char *arc_target_format = DEFAULT_TARGET_FORMAT;
 static int byte_order = DEFAULT_BYTE_ORDER;
 
+/* Arc extension section.  */
+static segT arcext_section;
+
 /* By default relaxation is disabled.  */
 static int relaxation_state = 0;
 
@@ -135,7 +139,7 @@ extern int arc_get_mach (char *);
 static void arc_lcomm (int);
 static void arc_option (int);
 static void arc_extra_reloc (int);
-
+static void arc_extinsn (int);
 
 const pseudo_typeS md_pseudo_table[] =
 {
@@ -147,6 +151,8 @@ const pseudo_typeS md_pseudo_table[] =
   { "lcommon", arc_lcomm, 0 },
   { "cpu",     arc_option, 0 },
 
+  { "extinstruction", arc_extinsn, 0 },
+
   { "tls_gd_ld",   arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_LD },
   { "tls_gd_call", arc_extra_reloc, BFD_RELOC_ARC_TLS_GD_CALL },
 
@@ -308,6 +314,35 @@ static struct arc_last_insn
   bfd_boolean has_delay_slot;
 } arc_last_insns[2];
 
+/* Extension instruction suffix classes.  */
+typedef struct
+{
+  const char *name;
+  int  len;
+  int  class;
+} attributes_t;
+
+static const attributes_t suffixclass[] =
+{
+  { "SUFFIX_FLAG", 11, ARC_SUFFIX_FLAG },
+  { "SUFFIX_COND", 11, ARC_SUFFIX_COND },
+  { "SUFFIX_NONE", 11, ARC_SUFFIX_NONE }
+};
+
+/* Extension instruction syntax classes.  */
+static const attributes_t syntaxclass[] =
+{
+  { "SYNTAX_3OP", 10, ARC_SYNTAX_3OP },
+  { "SYNTAX_2OP", 10, ARC_SYNTAX_2OP }
+};
+
+/* Extension instruction syntax classes modifiers.  */
+static const attributes_t syntaxclassmod[] =
+{
+  { "OP1_IMM_IMPLIED" , 15, ARC_OP1_IMM_IMPLIED },
+  { "OP1_MUST_BE_IMM" , 15, ARC_OP1_MUST_BE_IMM }
+};
+
 /* Structure to hold an entry in ARC_OPCODE_HASH.  */
 struct arc_opcode_hash_entry
 {
@@ -615,8 +650,8 @@ arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
       const char *old_name = iter->opcode->name;
 
       iter->opcode++;
-      if ((iter->opcode - arc_opcodes >= (int) arc_num_opcodes)
-	  || (strcmp (old_name, iter->opcode->name) != 0))
+      if (iter->opcode->name
+	  && (strcmp (old_name, iter->opcode->name) != 0))
 	{
 	  iter->index++;
 	  if (iter->index == entry->count)
@@ -629,6 +664,40 @@ arc_opcode_hash_entry_iterator_next (const struct arc_opcode_hash_entry *entry,
   return iter->opcode;
 }
 
+/* Insert an opcode into opcode hash structure.  */
+
+static void
+arc_insert_opcode (const struct arc_opcode *opcode)
+{
+  const char *name, *retval;
+  struct arc_opcode_hash_entry *entry;
+  name = opcode->name;
+
+  entry = hash_find (arc_opcode_hash, name);
+  if (entry == NULL)
+    {
+      entry = xmalloc (sizeof (*entry));
+      entry->count = 0;
+      entry->opcode = NULL;
+
+      retval = hash_insert (arc_opcode_hash, name, (void *) entry);
+      if (retval)
+	as_fatal (_("internal error: can't hash opcode '%s': %s"),
+		  name, retval);
+    }
+
+  entry->opcode = xrealloc (entry->opcode,
+			    sizeof (const struct arc_opcode *)
+			    * (entry->count + 1));
+
+  if (entry->opcode == NULL)
+    as_fatal (_("Virtual memory exhausted"));
+
+  entry->opcode[entry->count] = opcode;
+  entry->count++;
+}
+
+
 /* Like md_number_to_chars but used for limms.  The 4-byte limm value,
    is encoded as 'middle-endian' for a little-endian target.  FIXME!
    this function is used for regular 4 byte instructions as well.  */
@@ -1611,7 +1680,7 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
 			     from BKTOK.  */
 			  tok[tokidx].X_op = O_constant;
 			  tok[tokidx].X_add_number = auxr->address;
-			  ARC_SET_FLAG (tok[i].X_add_symbol, ARC_FLAG_AUX);
+			  ARC_SET_FLAG (tok[tokidx].X_add_symbol, ARC_FLAG_AUX);
 			  break;
 			}
 
@@ -2218,7 +2287,7 @@ declare_register_set (void)
 void
 md_begin (void)
 {
-  unsigned int i;
+  const struct arc_opcode *opcode = arc_opcodes;
 
   if (!mach_type_specified_p)
     arc_select_cpu ("arc700");
@@ -2238,37 +2307,17 @@ md_begin (void)
     as_fatal (_("Virtual memory exhausted"));
 
   /* Initialize the hash table with the insns.  */
-  for (i = 0; i < arc_num_opcodes;)
+  do
     {
-      const char *name, *retval;
-      struct arc_opcode_hash_entry *entry;
-
-      name = arc_opcodes[i].name;
-
-      entry = hash_find (arc_opcode_hash, name);
-      if (entry == NULL)
-        {
-          entry = xmalloc (sizeof (*entry));
-          entry->count = 0;
-          entry->opcode = NULL;
-
-          retval = hash_insert (arc_opcode_hash, name, (void *) entry);
-          if (retval)
-            as_fatal (_("internal error: can't hash opcode '%s': %s"),
-                      name, retval);
-        }
+      const char *name = opcode->name;
 
-      entry->opcode = xrealloc (entry->opcode,
-                                sizeof (const struct arc_opcode *)
-                                * entry->count + 1);
-      entry->opcode [entry->count] = &arc_opcodes[i];
-      entry->count++;
+      arc_insert_opcode (opcode);
 
-      while (++i < arc_num_opcodes
-	     && (arc_opcodes[i].name == name
-		 || !strcmp (arc_opcodes[i].name, name)))
+      while (++opcode && opcode->name
+	     && (opcode->name == name
+		 || !strcmp (opcode->name, name)))
 	continue;
-    }
+    }while (opcode->name);
 
   /* Register declaration.  */
   arc_reg_hash = hash_new ();
@@ -3877,3 +3926,275 @@ arc_adjust_symtab (void)
   /* Now do generic ELF adjustments.  */
   elf_adjust_symtab ();
 }
+
+static void
+tokenize_extinsn (extInstruction_t *einsn)
+{
+  char *p, c;
+  char *insn_name;
+  unsigned char major_opcode;
+  unsigned char sub_opcode;
+  unsigned char syntax_class = 0;
+  unsigned char syntax_class_modifiers = 0;
+  unsigned char suffix_class = 0;
+  unsigned int i;
+
+  SKIP_WHITESPACE ();
+
+  /* 1st: get instruction name.  */
+  p = input_line_pointer;
+  c = get_symbol_name (&p);
+
+  insn_name = xstrdup (p);
+  restore_line_pointer (c);
+
+  /* 2nd: get major opcode.  */
+  if (*input_line_pointer != ',')
+    {
+      as_bad (_("expected comma after instruction name"));
+      ignore_rest_of_line ();
+      return;
+    }
+  input_line_pointer++;
+  major_opcode = get_absolute_expression ();
+
+  /* 3rd: get sub-opcode.  */
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
+    {
+      as_bad (_("expected comma after major opcode"));
+      ignore_rest_of_line ();
+      return;
+    }
+  input_line_pointer++;
+  sub_opcode = get_absolute_expression ();
+
+  /* 4th: get suffix class.  */
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer != ',')
+    {
+      as_bad ("expected comma after sub opcode");
+      ignore_rest_of_line ();
+      return;
+    }
+  input_line_pointer++;
+
+  while (1)
+    {
+      SKIP_WHITESPACE ();
+
+      for (i = 0; i < ARRAY_SIZE (suffixclass); i++)
+	{
+	  if (!strncmp (suffixclass[i].name, input_line_pointer,
+			suffixclass[i].len))
+	    {
+	      suffix_class |= suffixclass[i].class;
+	      input_line_pointer += suffixclass[i].len;
+	      break;
+	    }
+	}
+
+      if (i == ARRAY_SIZE (suffixclass))
+	{
+	  as_bad ("invalid suffix class");
+	  ignore_rest_of_line ();
+	  return;
+	}
+
+      SKIP_WHITESPACE ();
+
+      if (*input_line_pointer == '|')
+	input_line_pointer++;
+      else
+	break;
+    }
+
+  /* 5th: get syntax class and syntax class modifiers.  */
+  if (*input_line_pointer != ',')
+    {
+      as_bad ("expected comma after suffix class");
+      ignore_rest_of_line ();
+      return;
+    }
+  input_line_pointer++;
+
+  while (1)
+    {
+      SKIP_WHITESPACE ();
+
+      for (i = 0; i < ARRAY_SIZE (syntaxclassmod); i++)
+	{
+	  if (!strncmp (syntaxclassmod[i].name,
+			input_line_pointer,
+			syntaxclassmod[i].len))
+	    {
+	      syntax_class_modifiers |= syntaxclassmod[i].class;
+	      input_line_pointer += syntaxclassmod[i].len;
+	      break;
+	    }
+	}
+
+      if (i == ARRAY_SIZE (syntaxclassmod))
+	{
+	  for (i = 0; i < ARRAY_SIZE (syntaxclass); i++)
+	    {
+	      if (!strncmp (syntaxclass[i].name,
+			    input_line_pointer,
+			    syntaxclass[i].len))
+		{
+		  syntax_class |= syntaxclass[i].class;
+		  input_line_pointer += syntaxclass[i].len;
+		  break;
+		}
+	    }
+
+	  if (i == ARRAY_SIZE (syntaxclass))
+	    {
+	      as_bad ("missing syntax class");
+	      ignore_rest_of_line ();
+	      return;
+	    }
+	}
+
+      SKIP_WHITESPACE ();
+
+      if (*input_line_pointer == '|')
+	input_line_pointer++;
+      else
+	break;
+    }
+
+  demand_empty_rest_of_line ();
+
+  einsn->name   = insn_name;
+  einsn->major  = major_opcode;
+  einsn->minor  = sub_opcode;
+  einsn->syntax = syntax_class;
+  einsn->modsyn = syntax_class_modifiers;
+  einsn->suffix = suffix_class;
+  einsn->flags  = syntax_class
+    | (syntax_class_modifiers & ARC_OP1_IMM_IMPLIED ? 0x10 : 0);
+}
+
+/* Generate an extension section.  */
+
+static int
+arc_set_ext_seg (void)
+{
+  if (!arcext_section)
+    {
+      arcext_section = subseg_new (".arcextmap", 0);
+      bfd_set_section_flags (stdoutput, arcext_section,
+			     SEC_READONLY | SEC_HAS_CONTENTS);
+    }
+  else
+    subseg_set (arcext_section, 0);
+  return 1;
+}
+
+/* Create an extension instruction description in the arc extension
+   section of the output file.
+   The structure for an instruction is like this:
+   [0]: Length of the record.
+   [1]: Type of the record.
+
+   [2]: Major opcode.
+   [3]: Sub-opcode.
+   [4]: Syntax (flags).
+   [5]+ Name instruction.
+
+   The sequence is terminated by an empty entry.  */
+
+static void
+create_extinst_section (extInstruction_t *einsn)
+{
+
+  segT old_sec    = now_seg;
+  int old_subsec  = now_subseg;
+  char *p;
+  int name_len    = strlen (einsn->name);
+
+  arc_set_ext_seg ();
+
+  p = frag_more (1);
+  *p = 5 + name_len + 1;
+  p = frag_more (1);
+  *p = EXT_INSTRUCTION;
+  p = frag_more (1);
+  *p = einsn->major;
+  p = frag_more (1);
+  *p = einsn->minor;
+  p = frag_more (1);
+  *p = einsn->flags;
+  p = frag_more (name_len + 1);
+  strcpy (p, einsn->name);
+
+  subseg_set (old_sec, old_subsec);
+}
+
+/* Handler .extinstruction pseudo-op.  */
+
+static void
+arc_extinsn (int ignore ATTRIBUTE_UNUSED)
+{
+  extInstruction_t einsn;
+  struct arc_opcode *arc_ext_opcodes;
+  const char *errmsg = NULL;
+  unsigned char moplow, mophigh;
+
+  memset (&einsn, 0, sizeof (einsn));
+  tokenize_extinsn (&einsn);
+
+  /* Check if the name is already used.  */
+  if (arc_find_opcode (einsn.name))
+    as_warn (_("Pseudocode already used %s"), einsn.name);
+
+  /* Check the opcode ranges.  */
+  moplow = 0x05;
+  mophigh = (arc_target & (ARC_OPCODE_ARCv2EM
+			   | ARC_OPCODE_ARCv2HS)) ? 0x07 : 0x0a;
+
+  if ((einsn.major > mophigh) || (einsn.major < moplow))
+    as_fatal (_("major opcode not in range [0x%02x - 0x%02x]"), moplow, mophigh);
+
+  if ((einsn.minor > 0x3f) && (einsn.major != 0x0a)
+      && (einsn.major != 5) && (einsn.major != 9))
+    as_fatal (_("minor opcode not in range [0x00 - 0x3f]"));
+
+  switch (einsn.syntax & (ARC_SYNTAX_3OP | ARC_SYNTAX_2OP))
+    {
+    case ARC_SYNTAX_3OP:
+      if (einsn.modsyn & ARC_OP1_IMM_IMPLIED)
+	as_fatal (_("Improper use of OP1_IMM_IMPLIED"));
+      break;
+    case ARC_SYNTAX_2OP:
+      if (einsn.modsyn & ARC_OP1_MUST_BE_IMM)
+	as_fatal (_("Improper use of OP1_MUST_BE_IMM"));
+      break;
+    default:
+      break;
+    }
+
+  arc_ext_opcodes = arcExtMap_genOpcode (&einsn, arc_target, &errmsg);
+  if (arc_ext_opcodes == NULL)
+    {
+      if (errmsg)
+	as_fatal ("%s", errmsg);
+      else
+	as_fatal (_("Couldn't generate extension instruction opcodes"));
+    }
+  else if (errmsg)
+    as_warn ("%s", errmsg);
+
+  /* Insert the extension instruction.  */
+  arc_insert_opcode ((const struct arc_opcode *) arc_ext_opcodes);
+
+  create_extinst_section (&einsn);
+}
+
+/* Local variables:
+   eval: (c-set-style "gnu")
+   indent-tabs-mode: t
+   End:  */
diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi
index 4824027..a237285 100644
--- a/gas/doc/c-arc.texi
+++ b/gas/doc/c-arc.texi
@@ -320,7 +320,7 @@ machine directives:
 @table @code
 
 @cindex @code{lcomm} directive
-@item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
+@item .lcomm @var{symbol}, @var{length}[, @var{alignment}]
 Reserve @var{length} (an absolute expression) bytes for a local common
 denoted by @var{symbol}.  The section and value of @var{symbol} are
 those of the new local common.  The addresses are allocated in the bss
@@ -336,11 +336,11 @@ largest power of two less than or equal to the size of the symbol, up
 to a maximum of 16.
 
 @cindex @code{lcommon} directive
-@item .lcommon @var{symbol} , @var{length}[, @var{alignment}]
+@item .lcommon @var{symbol}, @var{length}[, @var{alignment}]
 The same as @code{lcomm} directive.
 
-@cindex @code{cpu} directive, ARC
-@cindex @code{cpu} directive, ARC
+@cindex @code{cpu} directive
+@item .cpu @var{cpu}
 The @code{.cpu} directive must be followed by the desired core
 version.  Permitted values for CPU are:
 @table @code
@@ -361,6 +361,93 @@ Assemble for the ARC HS instruction set.
 Note: the @code{.cpu} directive overrides the command line option
 @code{-mcpu=@var{cpu}}; a warning is emitted when the version is not
 consistent between the two.
+
+@item .extInstruction @var{name}, @var{opcode}, @var{subopcode}, @var{suffixclass}, @var{syntaxclass}
+@cindex @code{extInstruction} directive
+ARC allows the user to specify extension instructions.  These
+extension instructions are not macros; the assembler creates encodings
+for use of these instructions according to the specification by the
+user.
+
+The first argument, @var{name}, gives the name of the instruction.
+
+The second argument, @var{opcode}, is the opcode to be used (bits 31:27
+in the encoding).
+
+The third argument, @var{subopcode}, is the sub-opcode to be used, but
+the correct value also depends on the fifth argument,
+@var{syntaxclass}
+
+The fourth argument, @var{suffixclass}, determines the kinds of
+suffixes to be allowed.  Valid values are:
+@table @code
+@item SUFFIX_NONE
+No suffixes are permitted;
+
+@item SUFFIX_COND
+Conditional suffixes are permitted;
+
+@item SUFFIX_FLAG
+Flag setting suffixes are permitted.
+
+@item SUFFIX_COND|SUFFIX_FLAG
+Both conditional and flag setting suffices are permitted.
+
+@end table
+
+The fifth and final argument, @var{syntaxclass}, determines the syntax
+class for the instruction.  It can have the following values:
+@table @code
+@item SYNTAX_2OP
+Two Operand Instruction;
+
+@item SYNTAX_3OP
+Three Operand Instruction.
+@end table
+
+The syntax class may be followed by @samp{|} and one of the following
+modifiers.
+@table @code
+
+@item OP1_MUST_BE_IMM
+Modifies syntax class @code{SYNTAX_3OP}, specifying that the first
+operand of a three-operand instruction must be an immediate (i.e., the
+result is discarded).  This is usually used to set the flags using
+specific instructions and not retain results.
+
+@item OP1_IMM_IMPLIED
+Modifies syntax class @code{SYNTAX_20P}, specifying that there is an
+implied immediate destination operand which does not appear in the
+syntax.
+
+For example, if the source code contains an instruction like:
+@example
+inst r1,r2
+@end example
+the first argument is an implied immediate (that is, the result is
+discarded).  This is the same as though the source code were: inst
+0,r1,r2.
+
+@end table
+
+For example, defining a 64-bit multiplier with immediate operands:
+@example
+	.extInstruction  mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
+			 SYNTAX_3OP|OP1_MUST_BE_IMM
+@end example
+which specifies an extension instruction named @code{mp64} with 3
+operands.  It sets the flags and can be used with a condition code,
+for which the first operand is an immediate, i.e. equivalent to
+discarding the result of the operation.
+
+A two operands instruction variant would be:
+@example
+	.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
+	SYNTAX_2OP|OP1_IMM_IMPLIED
+@end example
+which describes a two operand instruction with an implicit first
+immediate operand.  The result of this operation would be discarded.
+
 @end table
 
 @node ARC Modifiers
diff --git a/gas/testsuite/gas/arc/textinsn-errors.d b/gas/testsuite/gas/arc/textinsn-errors.d
new file mode 100644
index 0000000..b2f4a71
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn-errors.d
@@ -0,0 +1 @@
+#error-output: textinsn-errors.err
diff --git a/gas/testsuite/gas/arc/textinsn-errors.err b/gas/testsuite/gas/arc/textinsn-errors.err
new file mode 100644
index 0000000..2d99325
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn-errors.err
@@ -0,0 +1,2 @@
+[^:]*: Assembler messages:
+[^:]*:1: Warning: Suffix SUFFIX_COND ignored
diff --git a/gas/testsuite/gas/arc/textinsn-errors.s b/gas/testsuite/gas/arc/textinsn-errors.s
new file mode 100644
index 0000000..87417f2
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn-errors.s
@@ -0,0 +1 @@
+        .extInstruction myinsn0, 0x07, 0x2d, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_2OP
diff --git a/gas/testsuite/gas/arc/textinsn2op.d b/gas/testsuite/gas/arc/textinsn2op.d
new file mode 100644
index 0000000..52d52ce
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn2op.d
@@ -0,0 +1,24 @@
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	382f 006d           	myinsn	r0,r1
+   4:	3b2f 372d           	myinsn	fp,sp
+   8:	386f 002d           	myinsn	r0,0
+   c:	392f 0fad ffff ffff 	myinsn	r1,0xffffffff
+  14:	3e2f 70ad           	myinsn	0,r2
+  18:	3c2f 0fad 0000 00ff 	myinsn	r4,0xff
+  20:	3e2f 0fad ffff ff00 	myinsn	r6,0xffffff00
+  28:	382f 1fad 0000 0100 	myinsn	r8,0x100
+  30:	392f 1fad ffff feff 	myinsn	r9,0xfffffeff
+  38:	3b2f 1fad 4242 4242 	myinsn	r11,0x42424242
+  40:	382f 0fad 0000 0000 	myinsn	r0,0
+			44: R_ARC_32_ME	foo
+  48:	382f 806d           	myinsn.f	r0,r1
+  4c:	3a6f 806d           	myinsn.f	r2,0x1
+  50:	3e2f f12d           	myinsn.f	0,r4
+  54:	3d2f 8fad 0000 0200 	myinsn.f	r5,0x200
diff --git a/gas/testsuite/gas/arc/textinsn2op.s b/gas/testsuite/gas/arc/textinsn2op.s
new file mode 100644
index 0000000..ec96c70
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn2op.s
@@ -0,0 +1,22 @@
+# Insn 3 .extInstruction test
+	.extInstruction myinsn, 0x07, 0x2d, SUFFIX_FLAG, SYNTAX_2OP
+
+        myinsn r0,r1
+        myinsn fp,sp
+
+        myinsn r0,0
+        myinsn r1,-1
+        myinsn 0,r2
+        myinsn r4,255
+        myinsn r6,-256
+
+        myinsn r8,256
+        myinsn r9,-257
+        myinsn r11,0x42424242
+
+        myinsn r0,foo
+
+        myinsn.f r0,r1
+        myinsn.f r2,1
+        myinsn.f 0,r4
+        myinsn.f r5,512
diff --git a/gas/testsuite/gas/arc/textinsn2op01.d b/gas/testsuite/gas/arc/textinsn2op01.d
new file mode 100644
index 0000000..ea14df7
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn2op01.d
@@ -0,0 +1,27 @@
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	382d 007e           	myinsn	r0,r1
+   4:	3b2d 373e           	myinsn	fp,sp
+   8:	386d 003e           	myinsn	r0,0
+   c:	392d 0fbe ffff ffff 	myinsn	r1,0xffffffff
+  14:	3eed 7080 0000 0000 	myinsn	0,r2
+  1c:	3c2d 0fbe 0000 00ff 	myinsn	r4,0xff
+  24:	3e2d 0fbe ffff ff00 	myinsn	r6,0xffffff00
+  2c:	382d 1fbe 0000 0100 	myinsn	r8,0x100
+  34:	392d 1fbe ffff feff 	myinsn	r9,0xfffffeff
+  3c:	3b2d 1fbe 4242 4242 	myinsn	r11,0x42424242
+  44:	382d 0fbe 0000 0000 	myinsn	r0,0
+			48: R_ARC_32_ME	foo
+  4c:	382d 807e           	myinsn.f	r0,r1
+  50:	3a6d 807e           	myinsn.f	r2,0x1
+  54:	3eed f100 0000 0000 	myinsn.f	0,r4
+  5c:	3d2d 8fbe 0000 0200 	myinsn.f	r5,0x200
+  64:	3eed f102 0000 0000 	myinsn.ne.f	0,r4
+  6c:	3eed ff85 dead beef 	myinsn.c.f	0xdeadbeef,0xdeadbeef
+  74:	3eed f0a6 dead beef 	myinsn.nc.f	0xdeadbeef,0x2
diff --git a/gas/testsuite/gas/arc/textinsn2op01.s b/gas/testsuite/gas/arc/textinsn2op01.s
new file mode 100644
index 0000000..dbd5b24
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn2op01.s
@@ -0,0 +1,26 @@
+# Insn 2op .extInstruction test
+	.extInstruction myinsn, 0x07, 0x2d, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED
+
+        myinsn r0,r1
+        myinsn fp,sp
+
+        myinsn r0,0
+        myinsn r1,-1
+        myinsn 0,r2
+        myinsn r4,255
+        myinsn r6,-256
+
+        myinsn r8,256
+        myinsn r9,-257
+        myinsn r11,0x42424242
+
+        myinsn r0,foo
+
+        myinsn.f r0,r1
+        myinsn.f r2,1
+        myinsn.f 0,r4
+        myinsn.f r5,512
+
+	myinsn.ne.f 0,r4
+	myinsn.c.f  0xdeadbeef, 0xdeadbeef
+	myinsn.nc.f 0xdeadbeef, 0x02
diff --git a/gas/testsuite/gas/arc/textinsn3op.d b/gas/testsuite/gas/arc/textinsn3op.d
new file mode 100644
index 0000000..abf69ff
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn3op.d
@@ -0,0 +1,63 @@
+#objdump: -dr
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+
+[0-9a-f]+ <.text>:
+   0:	392d 0080           	myinsn	r0,r1,r2
+   4:	3b2d 371a           	myinsn	gp,fp,sp
+   8:	3e2d 37dd           	myinsn	ilink,r30,blink
+   c:	396d 0000           	myinsn	r0,r1,0
+  10:	3e2d 7080 0000 0000 	myinsn	r0,0,r2
+  18:	392d 00be           	myinsn	0,r1,r2
+  1c:	392d 0f80 ffff ffff 	myinsn	r0,r1,0xffffffff
+  24:	3e2d 7080 ffff ffff 	myinsn	r0,0xffffffff,r2
+  2c:	392d 0f80 0000 00ff 	myinsn	r0,r1,0xff
+  34:	3e2d 7080 0000 00ff 	myinsn	r0,0xff,r2
+  3c:	392d 0f80 ffff ff00 	myinsn	r0,r1,0xffffff00
+  44:	3e2d 7080 ffff ff00 	myinsn	r0,0xffffff00,r2
+  4c:	392d 0f80 0000 0100 	myinsn	r0,r1,0x100
+  54:	3e2d 7080 ffff feff 	myinsn	r0,0xfffffeff,r2
+  5c:	3e2d 7f80 0000 0100 	myinsn	r0,0x100,0x100
+  64:	392d 0f80 0000 0000 	myinsn	r0,r1,0
+			68: R_ARC_32_ME	foo
+  6c:	38ed 0080           	myinsn	r0,r0,r2
+  70:	3bed 0140           	myinsn	r3,r3,r5
+  74:	3eed 0201           	myinsn.eq	r6,r6,r8
+  78:	39ed 12c1           	myinsn.eq	r9,r9,r11
+  7c:	3ced 1382           	myinsn.ne	r12,r12,r14
+  80:	3fed 1442           	myinsn.ne	r15,r15,r17
+  84:	3aed 2503           	myinsn.p	r18,r18,r20
+  88:	3ded 25c3           	myinsn.p	r21,r21,r23
+  8c:	38ed 3684           	myinsn.n	r24,r24,gp
+  90:	3bed 3744           	myinsn.n	fp,fp,ilink
+  94:	3eed 37c5           	myinsn.c	r30,r30,blink
+  98:	3bed 00c5           	myinsn.c	r3,r3,r3
+  9c:	3bed 0205           	myinsn.c	r3,r3,r8
+  a0:	3bed 0106           	myinsn.nc	r3,r3,r4
+  a4:	3ced 0106           	myinsn.nc	r4,r4,r4
+  a8:	3ced 01c6           	myinsn.nc	r4,r4,r7
+  ac:	3ced 0147           	myinsn.v	r4,r4,r5
+  b0:	3ded 0147           	myinsn.v	r5,r5,r5
+  b4:	3ded 0148           	myinsn.nv	r5,r5,r5
+  b8:	3ded 0148           	myinsn.nv	r5,r5,r5
+  bc:	3eed 0009           	myinsn.gt	r6,r6,r0
+  c0:	38ed 002a           	myinsn.ge	r0,r0,0
+  c4:	39ed 006b           	myinsn.lt	r1,r1,0x1
+  c8:	3bed 00ed           	myinsn.hi	r3,r3,0x3
+  cc:	3ced 012e           	myinsn.ls	r4,r4,0x4
+  d0:	3ded 016f           	myinsn.pnz	r5,r5,0x5
+  d4:	392d 8080           	myinsn.f	r0,r1,r2
+  d8:	396d 8040           	myinsn.f	r0,r1,0x1
+  dc:	3e2d f080 0000 0001 	myinsn.f	r0,0x1,r2
+  e4:	392d 80be           	myinsn.f	0,r1,r2
+  e8:	392d 8f80 0000 0200 	myinsn.f	r0,r1,0x200
+  f0:	3e2d f080 0000 0200 	myinsn.f	r0,0x200,r2
+  f8:	39ed 8081           	myinsn.eq.f	r1,r1,r2
+  fc:	38ed 8022           	myinsn.ne.f	r0,r0,0
+ 100:	3aed 808b           	myinsn.lt.f	r2,r2,r2
+ 104:	3eed f0a9 0000 0001 	myinsn.gt.f	0,0x1,0x2
+ 10c:	3eed ff8c 0000 0200 	myinsn.le.f	0,0x200,0x200
+ 114:	3eed f0aa 0000 0200 	myinsn.ge.f	0,0x200,0x2
diff --git a/gas/testsuite/gas/arc/textinsn3op.s b/gas/testsuite/gas/arc/textinsn3op.s
new file mode 100644
index 0000000..a07aa9d
--- /dev/null
+++ b/gas/testsuite/gas/arc/textinsn3op.s
@@ -0,0 +1,64 @@
+# Insn 3op .extInstruction test
+	.extInstruction myinsn, 0x07, 0x2d, SUFFIX_FLAG|SUFFIX_COND, SYNTAX_3OP
+
+	myinsn r0,r1,r2
+	myinsn r26,fp,sp
+	myinsn ilink1,ilink2,blink
+
+	myinsn r0,r1,0
+	myinsn r0,0,r2
+	myinsn 0,r1,r2
+	myinsn r0,r1,-1
+	myinsn r0,-1,r2
+	myinsn r0,r1,255
+	myinsn r0,255,r2
+	myinsn r0,r1,-256
+	myinsn r0,-256,r2
+
+	myinsn r0,r1,256
+	myinsn r0,-257,r2
+
+	myinsn r0,256,256
+
+	myinsn r0,r1,foo
+
+	myinsn.al r0,r0,r2
+	myinsn.ra r3,r3,r5
+	myinsn.eq r6,r6,r8
+	myinsn.z  r9,r9,r11
+	myinsn.ne r12,r12,r14
+	myinsn.nz r15,r15,r17
+	myinsn.pl r18,r18,r20
+	myinsn.p  r21,r21,r23
+	myinsn.mi r24,r24,r26
+	myinsn.n  r27,r27,r29
+	myinsn.cs r30,r30,r31
+	myinsn.c  r3,r3,r3
+	myinsn.lo r3,r3,r8
+	myinsn.cc r3,r3,r4
+	myinsn.nc r4,r4,r4
+	myinsn.hs r4,r4,r7
+	myinsn.vs r4,r4,r5
+	myinsn.v  r5,r5,r5
+	myinsn.vc r5,r5,r5
+	myinsn.nv r5,r5,r5
+	myinsn.gt r6,r6,r0
+	myinsn.ge r0,r0,0
+	myinsn.lt r1,r1,1
+	myinsn.hi r3,r3,3
+	myinsn.ls r4,r4,4
+	myinsn.pnz r5,r5,5
+
+	myinsn.f r0,r1,r2
+	myinsn.f r0,r1,1
+	myinsn.f r0,1,r2
+	myinsn.f 0,r1,r2
+	myinsn.f r0,r1,512
+	myinsn.f r0,512,r2
+
+	myinsn.eq.f r1,r1,r2
+	myinsn.ne.f r0,r0,0
+	myinsn.lt.f r2,r2,r2
+	myinsn.gt.f 0,1,2
+	myinsn.le.f 0,512,512
+	myinsn.ge.f 0,512,2