gas/

	* config/tc-arm.c (do_t_nop): Correct check for Thumb-2 NOP.

	gas/testsuite/
	* gas/arm/thumb-nop.d, gas/arm/thumb-nop.s: New test.
	* gas/arm/relax_branch_align.d: Expect a default NOP instruction.
	* gas/arm/vfp1_t2.d, gas/arm/vfp1xD_t2.d: Specify a CPU with
	Thumb-2.

	ld/testsuite/
	* ld-arm/arm-elf.exp (armelftests): Assemble Cortex-A8 tests with
	-mcpu=cortex-a8.

8 files changed, 34 insertions, 7 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index f899ae9..8ae07df 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2010-01-13  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* config/tc-arm.c (do_t_nop): Correct check for Thumb-2 NOP.
+
 2010-01-13  Nick Clifton  <nickc@redhat.com>
 
 	* config/tc-h8300.c (h8300_elf_section): New function - issue a
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index b0184a5..d5a0ec4 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -10623,7 +10623,7 @@ do_t_nop (void)
 	{
 	  /* PR9722: Check for Thumb2 availability before
 	     generating a thumb2 nop instruction.  */
-	  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
+	  if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
 	    {
 	      inst.instruction = THUMB_OP16 (inst.instruction);
 	      inst.instruction |= inst.operands[0].imm << 4;
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 2fafd11..64d3cc7 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2010-01-13  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* gas/arm/thumb-nop.d, gas/arm/thumb-nop.s: New test.
+	* gas/arm/relax_branch_align.d: Expect a default NOP instruction.
+	* gas/arm/vfp1_t2.d, gas/arm/vfp1xD_t2.d: Specify a CPU with
+	Thumb-2.
+
 2010-01-13  Nick Clifton  <nickc@redhat.com>
 
 	* gas/elf/section0.d: Skip this test for the h8300.
diff --git a/gas/testsuite/gas/arm/relax_branch_align.d b/gas/testsuite/gas/arm/relax_branch_align.d
index e23b095..e19857a 100644
--- a/gas/testsuite/gas/arm/relax_branch_align.d
+++ b/gas/testsuite/gas/arm/relax_branch_align.d
@@ -4,10 +4,10 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]+> bf00      	nop
+0+000 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
 0+002 <[^>]+> f000 8080 	beq.w	0+106 <[^>]*>
-0+006 <[^>]+> bf00      	nop
+0+006 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
 #...
-0+100 <[^>]+> bf00      	nop
+0+100 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
 0+102 <[^>]+> f47f af80 	bne.w	0+006 <[^>]*>
-0+106 <[^>]+> bf00      	nop
+0+106 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumb-nop.d b/gas/testsuite/gas/arm/thumb-nop.d
new file mode 100644
index 0000000..648ed98
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb-nop.d
@@ -0,0 +1,11 @@
+# name: Thumb NOP
+# objdump: -dr --prefix-addresses --show-raw-insn
+#
+# Both explicit nop and padding should not use Thumb-2 NOP for the
+# default CPU.
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
+0+002 <[^>]+> 46c0      	nop			; \(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumb-nop.s b/gas/testsuite/gas/arm/thumb-nop.s
new file mode 100644
index 0000000..55b7b6c
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb-nop.s
@@ -0,0 +1,5 @@
+	.text
+	.code 16
+	.p2align 2
+.foo:	
+	nop
diff --git a/gas/testsuite/gas/arm/vfp1_t2.d b/gas/testsuite/gas/arm/vfp1_t2.d
index 2ff52fd..757bf10 100644
--- a/gas/testsuite/gas/arm/vfp1_t2.d
+++ b/gas/testsuite/gas/arm/vfp1_t2.d
@@ -1,6 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: Thumb-2 VFP Double-precision instructions
-#as: -mfpu=vfp
+#as: -mfpu=vfp -mcpu=arm1156t2f-s
 
 # Test the ARM VFP Double Precision instructions
 
diff --git a/gas/testsuite/gas/arm/vfp1xD_t2.d b/gas/testsuite/gas/arm/vfp1xD_t2.d
index 4cbadec..7dd5030 100644
--- a/gas/testsuite/gas/arm/vfp1xD_t2.d
+++ b/gas/testsuite/gas/arm/vfp1xD_t2.d
@@ -1,6 +1,6 @@
 #objdump: -dr --prefix-addresses --show-raw-insn
 #name: Thumb-2 VFP Single-precision instructions
-#as: -mfpu=vfpxd
+#as: -mfpu=vfpxd -mcpu=arm1156t2f-s
 
 # Test the ARM VFP Single Precision instructions