* config/tc-ms1.c: New.

	* config/tc-ms1.h: New.
	* testsuite/gas/ms1/allinsn.d: New.
	* testsuite/gas/ms1/allinsn.s: New.
	* testsuite/gas/ms1/badinsn.s: New.
	* testsuite/gas/ms1/badinsn1.s: New.
	* testsuite/gas/ms1/badoffsethigh.s: New.
	* testsuite/gas/ms1/badoffsetlow.s: New.
	* testsuite/gas/ms1/badorder.s: New.
	* testsuite/gas/ms1/badreg.s: New.
	* testsuite/gas/ms1/badsignedimmhigh.s: New.
	* testsuite/gas/ms1/badsignedimmlow.s: New.
	* testsuite/gas/ms1/badsyntax.s: New.
	* testsuite/gas/ms1/badsyntax1.s: New.
	* testsuite/gas/ms1/badunsignedimmhigh.s: New.
	* testsuite/gas/ms1/badunsignedimmlow.s: New.
	* testsuite/gas/ms1/errors.exp: New.
	* testsuite/gas/ms1/ldst.s: New.
	* testsuite/gas/ms1/misc.d: New.
	* testsuite/gas/ms1/misc.s: New.
	* testsuite/gas/ms1/ms1-16-003.d: New.
	* testsuite/gas/ms1/ms1-16-003.s: New.
	* testsuite/gas/ms1/ms1.exp: New.
	* testsuite/gas/ms1/msys.d: New.
	* testsuite/gas/ms1/msys.s: New.
	* testsuite/gas/ms1/relocs.d: New.
	* testsuite/gas/ms1/relocs.exp: New.
	* testsuite/gas/ms1/relocs1.s: New.
	* testsuite/gas/ms1/relocs2.s: New.

31 files changed, 1552 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 07b9374..127c24d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,35 @@
+2005-07-05  Aldy Hernandez  <aldyh@redhat.com>
+
+	* config/tc-ms1.c: New.
+	* config/tc-ms1.h: New.
+	* testsuite/gas/ms1/allinsn.d: New.
+	* testsuite/gas/ms1/allinsn.s: New.
+	* testsuite/gas/ms1/badinsn.s: New.
+	* testsuite/gas/ms1/badinsn1.s: New.
+	* testsuite/gas/ms1/badoffsethigh.s: New.
+	* testsuite/gas/ms1/badoffsetlow.s: New.
+	* testsuite/gas/ms1/badorder.s: New.
+	* testsuite/gas/ms1/badreg.s: New.
+	* testsuite/gas/ms1/badsignedimmhigh.s: New.
+	* testsuite/gas/ms1/badsignedimmlow.s: New.
+	* testsuite/gas/ms1/badsyntax.s: New.
+	* testsuite/gas/ms1/badsyntax1.s: New.
+	* testsuite/gas/ms1/badunsignedimmhigh.s: New.
+	* testsuite/gas/ms1/badunsignedimmlow.s: New.
+	* testsuite/gas/ms1/errors.exp: New.
+	* testsuite/gas/ms1/ldst.s: New.
+	* testsuite/gas/ms1/misc.d: New.
+	* testsuite/gas/ms1/misc.s: New.
+	* testsuite/gas/ms1/ms1-16-003.d: New.
+	* testsuite/gas/ms1/ms1-16-003.s: New.
+	* testsuite/gas/ms1/ms1.exp: New.
+	* testsuite/gas/ms1/msys.d: New.
+	* testsuite/gas/ms1/msys.s: New.
+	* testsuite/gas/ms1/relocs.d: New.
+	* testsuite/gas/ms1/relocs.exp: New.
+	* testsuite/gas/ms1/relocs1.s: New.
+	* testsuite/gas/ms1/relocs2.s: New.
+
 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 
 	* config/tc-i386.h (CpuSVME): New.
diff --git a/gas/config/tc-ms1.c b/gas/config/tc-ms1.c
new file mode 100644
index 0000000..3c60474
--- /dev/null
+++ b/gas/config/tc-ms1.c
@@ -0,0 +1,504 @@
+/* tc-ms1.c -- Assembler for the Morpho Technologies ms-I.
+   Copyright (C) 2005 Free Software Foundation.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#include <stdio.h>
+#include "as.h"
+#include "dwarf2dbg.h"
+#include "subsegs.h"     
+#include "symcat.h"
+#include "opcodes/ms1-desc.h"
+#include "opcodes/ms1-opc.h"
+#include "cgen.h"
+#include "elf/common.h"
+#include "elf/ms1.h"
+#include "libbfd.h"
+
+/* Structure to hold all of the different components
+   describing an individual instruction.  */
+typedef struct
+{
+  const CGEN_INSN *	insn;
+  const CGEN_INSN *	orig_insn;
+  CGEN_FIELDS		fields;
+#if CGEN_INT_INSN_P
+  CGEN_INSN_INT         buffer [1];
+#define INSN_VALUE(buf) (*(buf))
+#else
+  unsigned char         buffer [CGEN_MAX_INSN_SIZE];
+#define INSN_VALUE(buf) (buf)
+#endif
+  char *		addr;
+  fragS *		frag;
+  int                   num_fixups;
+  fixS *                fixups [GAS_CGEN_MAX_FIXUPS];
+  int                   indices [MAX_OPERAND_INSTANCES];
+}
+ms1_insn;
+
+
+const char comment_chars[]        = ";";
+const char line_comment_chars[]   = "#";
+const char line_separator_chars[] = ""; 
+const char EXP_CHARS[]            = "eE";
+const char FLT_CHARS[]            = "dD";
+
+/* The target specific pseudo-ops which we support.  */
+const pseudo_typeS md_pseudo_table[] =
+{
+    { "word",   cons,                   4 }, 
+    { "file",	(void (*) (int)) dwarf2_directive_file, 0 },
+    { "loc",	dwarf2_directive_loc,	0 },
+    { NULL, 	NULL,			0 }
+};
+
+
+
+static int no_scheduling_restrictions = 0;
+
+struct option md_longopts[] = 
+{
+#define OPTION_NO_SCHED_REST	(OPTION_MD_BASE)
+  { "nosched",	   no_argument, NULL, OPTION_NO_SCHED_REST },
+#define OPTION_MARCH		(OPTION_MD_BASE + 1)
+  { "march", required_argument, NULL, OPTION_MARCH},
+  { NULL,	   no_argument, NULL, 0 },
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+const char * md_shortopts = "";
+
+/* Mach selected from command line.  */
+static int ms1_mach = bfd_mach_ms1;
+static unsigned ms1_mach_bitmask = 0;
+
+/* Flags to set in the elf header */
+static flagword ms1_flags = EF_MS1_CPU_MRISC;
+
+/* The architecture to use.  */
+enum ms1_architectures
+  {
+    ms1_64_001,
+    ms1_16_002,
+    ms1_16_003
+  };
+
+/* MS1 architecture we are using for this output file.  */
+static enum ms1_architectures ms1_arch = ms1_64_001;
+
+int
+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg)
+{
+  switch (c)
+    {
+    case OPTION_MARCH:
+      if (strcasecmp (arg, "MS1-64-001") == 0)
+ 	{
+ 	  ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC;
+ 	  ms1_mach = bfd_mach_ms1;
+ 	  ms1_mach_bitmask = 1 << MACH_MS1;
+ 	  ms1_arch = ms1_64_001;
+ 	}
+      else if (strcasecmp (arg, "MS1-16-002") == 0)
+ 	{
+ 	  ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC;
+ 	  ms1_mach = bfd_mach_ms1;
+ 	  ms1_mach_bitmask = 1 << MACH_MS1;
+ 	  ms1_arch = ms1_16_002;
+ 	}
+      else if (strcasecmp (arg, "MS1-16-003") == 0)
+ 	{
+ 	  ms1_flags = (ms1_flags & ~EF_MS1_CPU_MASK) | EF_MS1_CPU_MRISC2;
+ 	  ms1_mach = bfd_mach_mrisc2;
+ 	  ms1_mach_bitmask = 1 << MACH_MS1_003;
+ 	  ms1_arch = ms1_16_003;
+ 	}
+    case OPTION_NO_SCHED_REST:
+      no_scheduling_restrictions = 1;
+      break;
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+
+void
+md_show_usage (FILE * stream)
+{
+  fprintf (stream, _("MS1 specific command line options:\n"));
+  fprintf (stream, _("  -march=ms1-64-001         allow ms1-64-001 instructions (default) \n"));
+  fprintf (stream, _("  -march=ms1-16-002         allow ms1-16-002 instructions \n"));
+  fprintf (stream, _("  -march=ms1-16-003         allow ms1-16-003 instructions \n"));
+  fprintf (stream, _("  -nosched                  disable scheduling restrictions \n"));
+}
+
+
+void
+md_begin (void)
+{
+  /* Initialize the `cgen' interface.  */
+  
+  /* Set the machine number and endian.  */
+  gas_cgen_cpu_desc = ms1_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, ms1_mach_bitmask,
+					   CGEN_CPU_OPEN_ENDIAN,
+					   CGEN_ENDIAN_BIG,
+					   CGEN_CPU_OPEN_END);
+  ms1_cgen_init_asm (gas_cgen_cpu_desc);
+
+  /* This is a callback from cgen to gas to parse operands.  */
+  cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand);
+
+  /* Set the ELF flags if desired. */
+  if (ms1_flags)
+    bfd_set_private_flags (stdoutput, ms1_flags);
+
+  /* Set the machine type.  */
+  bfd_default_set_arch_mach (stdoutput, bfd_arch_ms1, ms1_mach);
+}
+
+void
+md_assemble (char * str)
+{
+  static long delayed_load_register = 0;
+  static int last_insn_had_delay_slot = 0;
+  static int last_insn_in_noncond_delay_slot = 0;
+  static int last_insn_has_load_delay = 0;
+  static int last_insn_was_memory_access = 0;
+  static int last_insn_was_io_insn = 0;
+  static int last_insn_was_arithmetic_or_logic = 0;
+  static int last_insn_was_branch_insn = 0;
+  static int last_insn_was_conditional_branch_insn = 0;
+
+  ms1_insn insn;
+  char * errmsg;
+
+  /* Initialize GAS's cgen interface for a new instruction.  */
+  gas_cgen_init_parse ();
+
+  insn.insn = ms1_cgen_assemble_insn
+      (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg);
+
+  if (!insn.insn)
+    {
+      as_bad ("%s", errmsg);
+      return;
+    }
+
+  /* Doesn't really matter what we pass for RELAX_P here.  */
+  gas_cgen_finish_insn (insn.insn, insn.buffer,
+			CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL);
+
+
+  /* Handle Scheduling Restrictions.  */
+  if (!no_scheduling_restrictions)
+    {
+      /* Detect consecutive Memory Accesses.  */
+      if (last_insn_was_memory_access
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS)
+	  && ms1_mach == ms1_64_001)
+	as_warn (_("instruction %s may not follow another memory access instruction."),
+		 CGEN_INSN_NAME (insn.insn));
+
+      /* Detect consecutive I/O Instructions.  */
+      else if (last_insn_was_io_insn
+	       && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN))
+	as_warn (_("instruction %s may not follow another I/O instruction."),
+		 CGEN_INSN_NAME (insn.insn));
+
+      /* Detect consecutive branch instructions.  */
+      else if (last_insn_was_branch_insn
+	       && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN))
+	as_warn (_("%s may not occupy the delay slot of another branch insn."),
+		 CGEN_INSN_NAME (insn.insn));
+
+      /* Detect data dependencies on delayed loads: memory and input insns.  */
+      if (last_insn_has_load_delay && delayed_load_register)
+	{
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	      && insn.fields.f_sr1 == delayed_load_register)
+	    as_warn (_("operand references R%ld of previous load."),
+		     insn.fields.f_sr1);
+
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+	      && insn.fields.f_sr2 == delayed_load_register)
+	    as_warn (_("operand references R%ld of previous load."),
+		     insn.fields.f_sr2);
+	}
+
+      /* Detect data dependency between conditional branch instruction
+         and an immediately preceding arithmetic or logical instruction.  */
+      if (last_insn_was_arithmetic_or_logic
+	  && !last_insn_in_noncond_delay_slot
+	  && (delayed_load_register != 0)
+	  && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
+	  && ms1_arch == ms1_64_001)
+	{
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR1)
+	      && insn.fields.f_sr1 == delayed_load_register)
+	    as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."),
+		     insn.fields.f_sr1);
+
+	  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2)
+	      && insn.fields.f_sr2 == delayed_load_register)
+	    as_warn (_("conditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn."),
+		     insn.fields.f_sr2);
+	}
+    }
+
+  /* Keep track of details of this insn for processing next insn.  */
+  last_insn_in_noncond_delay_slot = last_insn_was_branch_insn
+    && !last_insn_was_conditional_branch_insn;
+
+  last_insn_had_delay_slot =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT);
+
+  last_insn_has_load_delay =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_LOAD_DELAY);
+
+  last_insn_was_memory_access =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS);
+
+  last_insn_was_io_insn =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN);
+
+  last_insn_was_arithmetic_or_logic =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_AL_INSN);
+
+  last_insn_was_branch_insn =
+    CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN);
+  
+  last_insn_was_conditional_branch_insn =
+  CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_BR_INSN)
+    && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRSR2);
+  
+  if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDR))
+     delayed_load_register = insn.fields.f_dr; 
+  else if (CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_USES_FRDRRR))
+     delayed_load_register = insn.fields.f_drrr; 
+  else  /* Insns has no destination register.  */
+     delayed_load_register = 0; 
+
+  /* Generate dwarf2 line numbers.  */
+  dwarf2_emit_insn (4); 
+}
+
+valueT
+md_section_align (segT segment, valueT size)
+{
+  int align = bfd_get_section_alignment (stdoutput, segment);
+
+  return ((size + (1 << align) - 1) & (-1 << align));
+}
+
+symbolS *
+md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
+{
+    return NULL;
+}
+
+int
+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+			       segT    segment ATTRIBUTE_UNUSED)
+{
+  as_fatal (_("md_estimate_size_before_relax\n"));
+  return 1;
+} 
+
+/* *fragP has been relaxed to its final size, and now needs to have
+   the bytes inside it modified to conform to the new size.
+
+   Called after relaxation is finished.
+   fragP->fr_type == rs_machine_dependent.
+   fragP->fr_subtype is the subtype of what the address relaxed to.  */
+
+void
+md_convert_frag (bfd   * abfd  ATTRIBUTE_UNUSED,
+		 segT    sec   ATTRIBUTE_UNUSED,
+		 fragS * fragP ATTRIBUTE_UNUSED)
+{
+}
+
+
+/* Functions concerning relocs.  */
+
+long
+md_pcrel_from_section (fixS *fixP, segT sec)
+{
+  if (fixP->fx_addsy != (symbolS *) NULL
+      && (!S_IS_DEFINED (fixP->fx_addsy)
+	  || S_GET_SEGMENT (fixP->fx_addsy) != sec))
+    /* The symbol is undefined (or is defined but not in this section).
+       Let the linker figure it out.  */
+    return 0;
+
+  /* Return the address of the opcode - cgen adjusts for opcode size
+     itself, to be consistent with the disassembler, which must do
+     so.  */
+  return fixP->fx_where + fixP->fx_frag->fr_address;
+}
+
+
+/* Return the bfd reloc type for OPERAND of INSN at fixup FIXP.
+   Returns BFD_RELOC_NONE if no reloc type can be found.
+   *FIXP may be modified if desired.  */
+
+bfd_reloc_code_real_type
+md_cgen_lookup_reloc (const CGEN_INSN *    insn     ATTRIBUTE_UNUSED,
+		      const CGEN_OPERAND * operand,
+		      fixS *               fixP     ATTRIBUTE_UNUSED)
+{
+  bfd_reloc_code_real_type result;
+
+  result = BFD_RELOC_NONE;
+
+  switch (operand->type)
+    {
+    case MS1_OPERAND_IMM16O:
+      result = BFD_RELOC_16_PCREL;
+      fixP->fx_pcrel = 1;
+      /* fixP->fx_no_overflow = 1; */
+      break;
+    case MS1_OPERAND_IMM16:
+    case MS1_OPERAND_IMM16Z:
+      /* These may have been processed at parse time.  */
+      if (fixP->fx_cgen.opinfo != 0)
+        result = fixP->fx_cgen.opinfo;
+      fixP->fx_no_overflow = 1;
+      break;
+    default:
+      result = BFD_RELOC_NONE;
+      break;
+    }
+
+  return result;
+}
+
+/* Write a value out to the object file, using the appropriate endianness.  */
+
+void
+md_number_to_chars (char * buf, valueT val, int n)
+{
+  number_to_chars_bigendian (buf, val, n);
+}
+
+/* Turn a string in input_line_pointer into a floating point constant of type
+   type, and store the appropriate bytes in *litP.  The number of LITTLENUMS
+   emitted is stored in *sizeP .  An error message is returned, or NULL on OK.  */
+
+/* Equal to MAX_PRECISION in atof-ieee.c.  */
+#define MAX_LITTLENUMS 6
+
+char *
+md_atof (type, litP, sizeP)
+     char   type;
+     char * litP;
+     int *  sizeP;
+{
+  int              prec;
+  LITTLENUM_TYPE   words [MAX_LITTLENUMS];
+  LITTLENUM_TYPE * wordP;
+  char *           t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+    case 's':
+    case 'S':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+    case 'r':
+    case 'R':
+      prec = 4;
+      break;
+
+   /* FIXME: Some targets allow other format chars for bigger sizes here.  */
+
+    default:
+      * sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+  * sizeP = prec * sizeof (LITTLENUM_TYPE);
+
+  /* This loops outputs the LITTLENUMs in REVERSE order;
+     in accord with the ms1 endianness.  */
+  for (wordP = words; prec--;)
+    {
+      md_number_to_chars (litP, (valueT) (*wordP++), sizeof (LITTLENUM_TYPE));
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+     
+  return 0;
+}
+
+/* See whether we need to force a relocation into the output file.  */
+
+int
+ms1_force_relocation (fixS * fixp ATTRIBUTE_UNUSED)
+{
+  return 0;
+}
+
+void
+ms1_apply_fix (fixS *fixP, valueT *valueP, segT seg)
+{
+  if ((fixP->fx_pcrel != 0) && (fixP->fx_r_type == BFD_RELOC_32))
+    fixP->fx_r_type = BFD_RELOC_32_PCREL;
+
+  gas_cgen_md_apply_fix (fixP, valueP, seg);
+}
+
+bfd_boolean
+ms1_fix_adjustable (fixS * fixP)
+{
+  bfd_reloc_code_real_type reloc_type;
+
+  if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED)
+    {
+      const CGEN_INSN *insn = NULL;
+      int opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED;
+      const CGEN_OPERAND *operand;
+
+      operand = cgen_operand_lookup_by_num(gas_cgen_cpu_desc, opindex);
+      reloc_type = md_cgen_lookup_reloc (insn, operand, fixP);
+    }
+  else
+    reloc_type = fixP->fx_r_type;
+
+  if (fixP->fx_addsy == NULL)
+    return TRUE;
+  
+  /* Prevent all adjustments to global symbols.  */
+  if (S_IS_EXTERNAL (fixP->fx_addsy))
+    return FALSE;
+  
+  if (S_IS_WEAK (fixP->fx_addsy))
+    return FALSE;
+  
+  return 1;
+}
diff --git a/gas/config/tc-ms1.h b/gas/config/tc-ms1.h
new file mode 100644
index 0000000..bc2b3f1
--- /dev/null
+++ b/gas/config/tc-ms1.h
@@ -0,0 +1,75 @@
+/* tc-ms1.h -- Header file for tc-ms1.c.
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+   This file is part of GAS, the GNU Assembler.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to
+   the Free Software Foundation, 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA. */
+
+#define TC_MS1
+
+#ifndef BFD_ASSEMBLER
+/* Leading space so will compile with cc.  */
+ #error MS1 support requires BFD_ASSEMBLER
+#endif
+
+#define LISTING_HEADER "MS1 GAS "
+
+/* The target BFD architecture.  */
+#define TARGET_ARCH bfd_arch_ms1
+
+#define TARGET_FORMAT "elf32-ms1"
+
+#define TARGET_BYTES_BIG_ENDIAN 1
+
+/* Permit temporary numeric labels.  */
+#define LOCAL_LABELS_FB 1
+
+/* .-foo gets turned into PC relative relocs.  */
+#define DIFF_EXPR_OK
+
+/* We don't need to handle .word strangely.  */
+#define WORKING_DOT_WORD
+
+/* All ms1 instructions are multiples of 32 bits.  */
+#define DWARF2_LINE_MIN_INSN_LENGTH 4
+
+#define LITERAL_PREFIXDOLLAR_HEX
+#define LITERAL_PREFIXPERCENT_BIN
+
+#define md_apply_fix ms1_apply_fix
+extern void ms1_apply_fix (struct fix *, valueT *, segT); 
+
+/* Call md_pcrel_from_section(), not md_pcrel_from().  */
+#define MD_PCREL_FROM_SECTION(FIXP, SEC) md_pcrel_from_section (FIXP, SEC)
+extern long md_pcrel_from_section (struct fix *, segT);
+
+#define obj_fix_adjustable(fixP) iq2000_fix_adjustable (fixP)
+extern bfd_boolean ms1_fix_adjustable (struct fix *);
+
+/* Values passed to md_apply_fix don't include the symbol value.  */
+#define MD_APPLY_SYM_VALUE(FIX) 0
+
+#define tc_gen_reloc gas_cgen_tc_gen_reloc
+
+#define md_operand(x) gas_cgen_md_operand (x)
+extern void gas_cgen_md_operand (expressionS *);
+
+#define TC_FORCE_RELOCATION(fixp) ms1_force_relocation (fixp)
+extern int ms1_force_relocation (struct fix *);
+
+#define tc_fix_adjustable(fixP) ms1_fix_adjustable (fixP)
+extern bfd_boolean ms1_fix_adjustable (struct fix *);
+
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 57fa47a..6babf43 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,34 @@
+2005-07-05  Aldy Hernandez  <aldyh@redhat.com>
+
+	* gas/ms1: New directory.
+	* gas/ms1/allinsn.d: New.
+	* gas/ms1/allinsn.s: New.
+	* gas/ms1/badinsn.s: New.
+	* gas/ms1/badinsn1.s: New.
+	* gas/ms1/badoffsethigh.s: New.
+	* gas/ms1/badoffsetlow.s: New.
+	* gas/ms1/badorder.s: New.
+	* gas/ms1/badreg.s: New.
+	* gas/ms1/badsignedimmhigh.s: New.
+	* gas/ms1/badsignedimmlow.s: New.
+	* gas/ms1/badsyntax.s: New.
+	* gas/ms1/badsyntax1.s: New.
+	* gas/ms1/badunsignedimmhigh.s: New.
+	* gas/ms1/badunsignedimmlow.s: New.
+	* gas/ms1/errors.exp: New.
+	* gas/ms1/ldst.s: New.
+	* gas/ms1/misc.d: New.
+	* gas/ms1/misc.s: New.
+	* gas/ms1/ms1-16-003.d: New.
+	* gas/ms1/ms1-16-003.s: New.
+	* gas/ms1/ms1.exp: New.
+	* gas/ms1/msys.d: New.
+	* gas/ms1/msys.s: New.
+	* gas/ms1/relocs.d: New.
+	* gas/ms1/relocs.exp: New.
+	* testsuite/gas/ms1/relocs1.s: New.
+	* testsuite/gas/ms1/relocs2.s: New.
+
 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 
 	* gas/i386/svme.d: New.
diff --git a/gas/testsuite/gas/ms1/allinsn.d b/gas/testsuite/gas/ms1/allinsn.d
new file mode 100644
index 0000000..d992c58
--- /dev/null
+++ b/gas/testsuite/gas/ms1/allinsn.d
@@ -0,0 +1,130 @@
+#as: -nosched
+#objdump: -dr
+#name: allinsn
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <add>:
+   0:	00 00 00 00 	add R0,R0,R0
+
+00000004 <addu>:
+   4:	02 00 00 00 	addu R0,R0,R0
+
+00000008 <addi>:
+   8:	01 00 00 00 	addi R0,R0,#\$0
+
+0000000c <addui>:
+   c:	03 00 00 00 	addui R0,R0,#\$0
+
+00000010 <sub>:
+  10:	04 00 00 00 	sub R0,R0,R0
+
+00000014 <subu>:
+  14:	06 00 00 00 	subu R0,R0,R0
+
+00000018 <subi>:
+  18:	05 00 00 00 	subi R0,R0,#\$0
+
+0000001c <subui>:
+  1c:	07 00 00 00 	subui R0,R0,#\$0
+
+00000020 <and>:
+  20:	10 00 00 00 	and R0,R0,R0
+
+00000024 <andi>:
+  24:	11 00 00 00 	andi R0,R0,#\$0
+
+00000028 <or>:
+  28:	12 01 00 00 	or R0,R0,R1
+
+0000002c <ori>:
+  2c:	13 00 00 00 	ori R0,R0,#\$0
+
+00000030 <xor>:
+  30:	14 00 00 00 	xor R0,R0,R0
+
+00000034 <xori>:
+  34:	15 00 00 00 	xori R0,R0,#\$0
+
+00000038 <nand>:
+  38:	16 00 00 00 	nand R0,R0,R0
+
+0000003c <nandi>:
+  3c:	17 00 00 00 	nandi R0,R0,#\$0
+
+00000040 <nor>:
+  40:	18 00 00 00 	nor R0,R0,R0
+
+00000044 <nori>:
+  44:	19 00 00 00 	nori R0,R0,#\$0
+
+00000048 <xnor>:
+  48:	1a 00 00 00 	xnor R0,R0,R0
+
+0000004c <xnori>:
+  4c:	1b 00 00 00 	xnori R0,R0,#\$0
+
+00000050 <ldui>:
+  50:	1d 00 00 00 	ldui R0,#\$0
+
+00000054 <lsl>:
+  54:	20 00 00 00 	lsl R0,R0,R0
+
+00000058 <lsli>:
+  58:	21 00 00 00 	lsli R0,R0,#\$0
+
+0000005c <lsr>:
+  5c:	22 00 00 00 	lsr R0,R0,R0
+
+00000060 <lsri>:
+  60:	23 00 00 00 	lsri R0,R0,#\$0
+
+00000064 <asr>:
+  64:	24 00 00 00 	asr R0,R0,R0
+
+00000068 <asri>:
+  68:	25 00 00 00 	asri R0,R0,#\$0
+
+0000006c <brlt>:
+  6c:	31 00 00 00 	brlt R0,R0,\$0
+
+00000070 <brle>:
+  70:	33 00 00 00 	brle R0,R0,\$0
+
+00000074 <breq>:
+  74:	35 00 00 00 	breq R0,R0,\$0
+
+00000078 <jmp>:
+  78:	37 00 00 00 	jmp \$0
+
+0000007c <jal>:
+  7c:	38 00 00 00 	jal R0,R0
+
+00000080 <ei>:
+  80:	60 00 00 00 	ei
+
+00000084 <di>:
+  84:	62 00 00 00 	di
+
+00000088 <reti>:
+  88:	66 00 00 00 	reti R0
+
+0000008c <ldw>:
+  8c:	41 00 00 00 	ldw R0,R0,#\$0
+
+00000090 <stw>:
+  90:	43 00 00 00 	stw R0,R0,#\$0
+
+00000094 <si>:
+  94:	64 00 00 00 	si R0
+
+00000098 <brne>:
+  98:	3b 00 00 00 	brne R0,R0,\$0
+
+0000009c <break>:
+  9c:	68 00 00 00 	break
+
+000000a0 <nop>:
+  a0:	12 00 00 00 	nop
diff --git a/gas/testsuite/gas/ms1/allinsn.s b/gas/testsuite/gas/ms1/allinsn.s
new file mode 100644
index 0000000..8d9050e
--- /dev/null
+++ b/gas/testsuite/gas/ms1/allinsn.s
@@ -0,0 +1,166 @@
+ .data
+foodata: .word 42
+ .text
+footext:
+	.text
+	.global add
+add:
+	add  R0,R0,R0
+	.text
+	.global addu
+addu:
+	addu R0,R0,R0
+	.text
+	.global addi
+addi:
+	addi R0,R0,#0
+	.text
+	.global addui
+addui:
+	addui R0,R0,#0
+	.text
+	.global sub
+sub:
+	sub R0,R0,R0
+	.text
+	.global subu
+subu:
+	subu R0,R0,R0
+	.text
+	.global subi
+subi:
+	subi R0,R0,#0
+	.text
+	.global subui
+subui:
+	subui R0,R0,#0
+	.text
+	.global and
+and:
+	and R0,R0,R0
+	.text
+	.global andi
+andi:
+	andi R0,R0,#0
+	.text
+	.global or
+or:
+	or R0,R0,R1
+	.text
+	.global ori
+ori:
+	ori R0,R0,#0
+	.text
+	.global xor
+xor:
+	xor R0,R0,R0
+	.text
+	.global xori
+xori:
+	xori R0,R0,#0
+	.text
+	.global nand
+nand:
+	nand R0,R0,R0
+	.text
+	.global nandi
+nandi:
+	nandi R0,R0,#0
+	.text
+	.global nor
+nor:
+	nor R0,R0,R0
+	.text
+	.global nori
+nori:
+	nori R0,R0,#0
+	.text
+	.global xnor
+xnor:
+	xnor R0,R0,R0
+	.text
+	.global xnori
+xnori:
+	xnori R0,R0,#0
+	.text
+	.global ldui
+ldui:
+	ldui R0,#0
+	.text
+	.global lsl
+lsl:
+	lsl R0,R0,R0
+	.text
+	.global lsli
+lsli:
+	lsli R0,R0,#0
+	.text
+	.global lsr
+lsr:
+	lsr R0,R0,R0
+	.text
+	.global lsri
+lsri:
+	lsri R0,R0,#0
+	.text
+	.global asr
+asr:
+	asr R0,R0,R0
+	.text
+	.global asri
+asri:
+	asri R0,R0,#0
+	.text
+	.global brlt
+brlt:
+	brlt R0,R0,0
+	.text
+	.global brle
+brle:
+	brle R0,R0,0
+	.text
+	.global breq
+breq:
+	breq R0,R0,0
+	.text
+	.global jmp
+jmp:
+	jmp 0
+	.text
+	.global jal
+jal:
+	jal R0,R0
+	.text
+	.global ei
+ei:
+	ei
+	.text
+	.global di
+di:
+	di
+	.text
+	.global reti
+reti:
+	reti R0
+	.text
+	.global ldw
+ldw:
+	ldw R0,R0,#0
+	.text
+	.global stw
+stw:
+	stw R0,R0,#0
+	.text
+	.global si
+si:
+	si R0
+	.global brne
+brne:
+	brne R0,R0,0
+	.global break
+break:
+	break
+	.text
+	.global nop
+nop:
+	nop
diff --git a/gas/testsuite/gas/ms1/badinsn.s b/gas/testsuite/gas/ms1/badinsn.s
new file mode 100644
index 0000000..7c817fe
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badinsn.s
@@ -0,0 +1,3 @@
+; Bogus instruction mnemonic should generate an error.
+
+addcrap R1,R2,R3
diff --git a/gas/testsuite/gas/ms1/badinsn1.s b/gas/testsuite/gas/ms1/badinsn1.s
new file mode 100644
index 0000000..32f487d
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badinsn1.s
@@ -0,0 +1,3 @@
+; Extra operand should generate and error message.
+
+add R1,R2,R3,R4
diff --git a/gas/testsuite/gas/ms1/badoffsethigh.s b/gas/testsuite/gas/ms1/badoffsethigh.s
new file mode 100644
index 0000000..eb293a7
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badoffsethigh.s
@@ -0,0 +1,4 @@
+; Offset greater than #32767 should cause an error since the offset is 
+; a signed quantity.
+
+brlt R1,R2,$32768
diff --git a/gas/testsuite/gas/ms1/badoffsetlow.s b/gas/testsuite/gas/ms1/badoffsetlow.s
new file mode 100644
index 0000000..1cbfb91
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badoffsetlow.s
@@ -0,0 +1,6 @@
+; Offset less than #-32786 should cause an error since the offset is
+; a signed quantity.  Also tests expression parsing.
+
+label1: add R1,R2,R3
+label2:	add R4,R5,R6
+	brlt R7,R8, ((label1-label2)-32765) ; evaluates to -32769
diff --git a/gas/testsuite/gas/ms1/badorder.s b/gas/testsuite/gas/ms1/badorder.s
new file mode 100644
index 0000000..901f31e
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badorder.s
@@ -0,0 +1,3 @@
+; Good operands in the wrong order should generate an error.
+
+addui R1, #32 R2
diff --git a/gas/testsuite/gas/ms1/badreg.s b/gas/testsuite/gas/ms1/badreg.s
new file mode 100644
index 0000000..4bec7f4
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badreg.s
@@ -0,0 +1,3 @@
+; Bad register name should generate an error.
+
+add R16,R10,R9
diff --git a/gas/testsuite/gas/ms1/badsignedimmhigh.s b/gas/testsuite/gas/ms1/badsignedimmhigh.s
new file mode 100644
index 0000000..802c34d
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badsignedimmhigh.s
@@ -0,0 +1,3 @@
+; Offset greater than #32767 should cause an error.
+
+addi R1,R2,#32768
diff --git a/gas/testsuite/gas/ms1/badsignedimmlow.s b/gas/testsuite/gas/ms1/badsignedimmlow.s
new file mode 100644
index 0000000..46a6298
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badsignedimmlow.s
@@ -0,0 +1,3 @@
+; Immediate lower than #-32769 should cause an error.
+
+addi R1,R2,#-32769
diff --git a/gas/testsuite/gas/ms1/badsyntax.s b/gas/testsuite/gas/ms1/badsyntax.s
new file mode 100644
index 0000000..9c8e501
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badsyntax.s
@@ -0,0 +1,3 @@
+; Good mnemonic with wrong operands should generate an error.
+
+add R1,R2,#0
diff --git a/gas/testsuite/gas/ms1/badsyntax1.s b/gas/testsuite/gas/ms1/badsyntax1.s
new file mode 100644
index 0000000..64fd6a5
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badsyntax1.s
@@ -0,0 +1,3 @@
+; Good mnemonic with too few operands should generate an error.
+
+add R1,R2
diff --git a/gas/testsuite/gas/ms1/badunsignedimmhigh.s b/gas/testsuite/gas/ms1/badunsignedimmhigh.s
new file mode 100644
index 0000000..1f0200f
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badunsignedimmhigh.s
@@ -0,0 +1,3 @@
+; Offset greater than #$FFFF should cause an error.
+
+andi R1,R2,#$10000
diff --git a/gas/testsuite/gas/ms1/badunsignedimmlow.s b/gas/testsuite/gas/ms1/badunsignedimmlow.s
new file mode 100644
index 0000000..8df8215
--- /dev/null
+++ b/gas/testsuite/gas/ms1/badunsignedimmlow.s
@@ -0,0 +1,3 @@
+; Offset less than #0 should cause an error.
+
+andi R1,R2,#-1
diff --git a/gas/testsuite/gas/ms1/errors.exp b/gas/testsuite/gas/ms1/errors.exp
new file mode 100644
index 0000000..90a8976
--- /dev/null
+++ b/gas/testsuite/gas/ms1/errors.exp
@@ -0,0 +1,79 @@
+# Test for error messages when a bad register name, an out of range operand, or 
+# invalid syntax is used.  Adapted from Ben Elliston's load-hazard testcase.
+
+# Run GAS and check that it emits the desired error for the test case.
+# Arguments:
+#   file -- name of the test case to assemble.
+#   testname -- a string describing the test.
+#   warnpattern -- a regular expression, suitable for use by the Tcl
+#     regexp command, to decide if the warning string was emitted by
+#     the assembler to stderr.
+
+proc mrisc1_error_test { file testname {warnpattern ""} } {
+    global comp_output
+
+    gas_run $file "" ">/dev/null"
+    verbose "output was $comp_output" 2
+
+    if {$warnpattern == ""} {
+	if {$comp_output == ""} { pass $testname } else { fail $testname }
+	return
+    }
+
+    if {[regexp "Error: $warnpattern" $comp_output]} {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+if [istarget mrisc1*-*-*] {
+    foreach file [glob -nocomplain -- $srcdir/$subdir/bad*.s] {
+	set file [file tail $file]
+	switch -- $file {
+	    "badreg.s" {
+		set warnpattern "unrecognized keyword/register name *"
+	    }
+	    "badorder.s" {
+		set warnpattern "unrecognized form of instruction*"
+	    }
+	    "badsyntax.s" {
+		set warnpattern "unrecognized keyword/register name *"
+	    }
+	    "badsyntax1.s" {
+		set warnpattern "unrecognized form of instruction*"
+	    }
+	    "badoffsethigh.s" {
+		set warnpattern "Operand out of range. Must be between -32768 and 32767.*"
+	    }
+	    "badoffsetlow.s" {
+		set warnpattern "Operand out of range. Must be between -32768 and 32767.*"
+	    }
+	    "badunsignedimmhigh.s" {
+		set warnpattern "operand out of range (65536 not between 0 and 65535)*"
+	    }
+	    "badunsignedimmlow.s" {
+		set warnpattern "operand out of range (65536 not between 0 and 65535)*"
+	    }
+	    "badsignedimmhigh.s" {
+		set warnpattern "operand out of range.*"
+	    }
+	    "badsignedimmlow.s" {
+		set warnpattern "operand out of range.*"
+	    }
+	    "badinsn.s" {
+		set warnpattern "unrecognized instruction *"
+	    }
+	    "badinsn1.s" {
+		set warnpattern "junk at end of line *"
+	    }
+            default {
+                error "no expected result specified for $file"
+                return
+
+	    }
+	}
+	mrisc1_error_test $file "assembler emits error for $file" $warnpattern
+    }
+
+}
diff --git a/gas/testsuite/gas/ms1/ldst.s b/gas/testsuite/gas/ms1/ldst.s
new file mode 100644
index 0000000..174bcc8
--- /dev/null
+++ b/gas/testsuite/gas/ms1/ldst.s
@@ -0,0 +1,28 @@
+; load/store tests
+
+	.data
+
+ldw_data:
+	.word 0xbabeface
+
+	.text
+
+ld_text:
+	ld	r4, r3
+	ld	r3, #8
+	ld	r5, #ld_text
+	ldh	r6, #ldh_text
+	ldh	r4, #4000
+	ldh	r5, #0x8000
+	ldh	r5, #-5
+	ldh	r5, #-0x8000
+	ldh	r0, #0xffff
+ldh_text:
+	ldw	r9, #30233000
+	ldw	r3, #ldw_data
+	ldb	r3, @[r9+r2]
+	ldb	@[r9+r3], r5	; store
+	ldb	r3, @[r8+6]
+	ldb	@[r8+7], r3	; store
+	ldw	r9, @[r14+23]
+	ldw	@[r14+10], r9	; store
diff --git a/gas/testsuite/gas/ms1/misc.d b/gas/testsuite/gas/ms1/misc.d
new file mode 100644
index 0000000..aec3424
--- /dev/null
+++ b/gas/testsuite/gas/ms1/misc.d
@@ -0,0 +1,21 @@
+#as:
+#objdump: -dr
+#name: misc
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	00 12 00 00 	add R0,R1,R2
+   4:	00 12 00 00 	add R0,R1,R2
+   8:	00 23 10 00 	add R1,R2,R3
+   c:	00 33 10 00 	add R1,R3,R3
+  10:	00 56 40 00 	add R4,R5,R6
+  14:	00 89 70 00 	add R7,R8,R9
+  18:	00 bc a0 00 	add R10,R11,R12
+  1c:	00 ef d0 00 	add R13,R14,R15
+  20:	03 dc 00 01 	addui R12,R13,#\$1
+  24:	03 fe 00 01 	addui R14,R15,#\$1
+  28:	03 10 00 00 	addui R0,R1,#\$0
+  2c:	03 10 ff ff 	addui R0,R1,#\$ffff
diff --git a/gas/testsuite/gas/ms1/misc.s b/gas/testsuite/gas/ms1/misc.s
new file mode 100644
index 0000000..3a7cd4e
--- /dev/null
+++ b/gas/testsuite/gas/ms1/misc.s
@@ -0,0 +1,21 @@
+; Check that register names, both upper and lower case work and that
+; the spacing between the operands doesn't matter.
+
+add R0,R1,R2
+add r0,r1,r2
+add R1,R2,r3
+add R1, R3, r3
+add R4,R5,R6
+add R7,R8,R9
+add R10,R11,R12
+add R13,R14,R15
+addui fp,sp,#1
+addui ra,ira,#1
+
+; Check that the range of legal operand values is accepted.
+
+addui R0,R1,#0
+addui R0,R1,#$FFFF
+
+
+
diff --git a/gas/testsuite/gas/ms1/ms1-16-003.d b/gas/testsuite/gas/ms1/ms1-16-003.d
new file mode 100644
index 0000000..0233d85
--- /dev/null
+++ b/gas/testsuite/gas/ms1/ms1-16-003.d
@@ -0,0 +1,33 @@
+#as: -march=ms1-16-003
+#objdump: -dr
+#name: ms1-16-003
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <iflush>:
+   0:	6a 00 00 00 	iflush
+00000004 <mul>:
+   4:	08 00 00 00 	mul R0,R0,R0
+00000008 <muli>:
+   8:	09 00 00 00 	muli R0,R0,#\$0
+0000000c <dbnz>:
+   c:	3d 00 00 00 	dbnz R0,\$0
+[ 	]*c: R_MS1_PC16	dbnz
+00000010 <fbcbincs>:
+  10:	f0 00 00 00 	fbcbincs #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000014 <mfbcbincs>:
+  14:	f4 00 00 00 	mfbcbincs R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000018 <fbcbincrs>:
+  18:	f8 00 00 00 	fbcbincrs R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+0000001c <mfbcbincrs>:
+  1c:	fc 00 00 00 	mfbcbincrs R0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000020 <wfbinc>:
+  20:	e0 00 00 00 	wfbinc #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000024 <mwfbinc>:
+  24:	e4 00 00 00 	mwfbinc R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+00000028 <wfbincr>:
+  28:	e8 00 00 00 	wfbincr R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+0000002c <mwfbincr>:
+  2c:	ec 00 00 00 	mwfbincr R0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
diff --git a/gas/testsuite/gas/ms1/ms1-16-003.s b/gas/testsuite/gas/ms1/ms1-16-003.s
new file mode 100644
index 0000000..ec1dd7b
--- /dev/null
+++ b/gas/testsuite/gas/ms1/ms1-16-003.s
@@ -0,0 +1,54 @@
+	.text
+	.global iflush
+iflush:
+	iflush
+
+	.global mul
+mul:
+	mul R0, R0, R0
+	
+	.global muli
+muli:
+	muli R0, R0, #0
+
+	.global dbnz
+dbnz:
+	dbnz	r0, dbnz
+
+	.global fbcbincs
+fbcbincs:
+	fbcbincs #0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mfbcbincs
+mfbcbincs:
+	mfbcbincs r0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	
+	.global fbcbincrs
+fbcbincrs:
+	fbcbincrs r0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mfbcbincrs
+mfbcbincrs:
+	mfbcbincrs r0, r0, #0, #0, #0, #0, #0, #0, #0
+	
+	
+	.global wfbinc
+wfbinc:
+# Documentation error.
+#	wfbinc #0, r0, #0, #0, #0, #0, #0, #0, #0, #0
+	wfbinc #0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mwfbinc
+mwfbinc:
+# Documentation error.
+#	mwfbinc r0, #0, #0, r0, #0, #0, #0, #0, #0
+	mwfbinc r0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global wfbincr
+wfbincr:
+	wfbincr r0, #0, #0, #0, #0, #0, #0, #0, #0, #0
+
+	.global mwfbincr
+mwfbincr:
+	mwfbincr r0, r0, #0, #0, #0, #0, #0, #0, #0
diff --git a/gas/testsuite/gas/ms1/ms1.exp b/gas/testsuite/gas/ms1/ms1.exp
new file mode 100644
index 0000000..49aea81
--- /dev/null
+++ b/gas/testsuite/gas/ms1/ms1.exp
@@ -0,0 +1,10 @@
+# MRISC1 assembler testsuite.
+
+if { [istarget mrisc1*-*-*] || [istarget ms1-*-*]} then {
+    #
+    run_dump_test "allinsn"
+    run_dump_test "misc"
+    run_dump_test "msys"
+    run_dump_test "ms1-16-003"
+    #
+}
diff --git a/gas/testsuite/gas/ms1/msys.d b/gas/testsuite/gas/ms1/msys.d
new file mode 100644
index 0000000..fb135dd
--- /dev/null
+++ b/gas/testsuite/gas/ms1/msys.d
@@ -0,0 +1,78 @@
+#as: -nosched
+#objdump: -dr
+#name: msys 
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <.text>:
+   0:	80 00 00 00 	ldctxt R0,R0,#\$0,#\$0,#\$0
+   4:	84 00 00 00 	ldfb R0,R0,#\$0
+   8:	88 00 00 00 	stfb R0,R0,#\$0
+   c:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  10:	90 00 00 00 	mfbcb R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0
+  14:	94 00 00 00 	fbcci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  18:	98 00 00 00 	fbrci R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  1c:	9c 00 00 00 	fbcri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  20:	a0 00 00 00 	fbrri R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  24:	a4 00 00 00 	mfbcci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  28:	a8 00 00 00 	mfbrci R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  2c:	ac 00 00 00 	mfbcri R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  30:	b0 00 00 00 	mfbrri R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0
+  34:	b4 00 00 00 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  38:	b8 00 00 00 	rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  3c:	bc 00 00 00 	mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  40:	c0 00 00 00 	cbcast #\$0,#\$0,#\$0
+  44:	c4 00 00 00 	dupcbcast #\$0,#\$0,#\$0,#\$0
+  48:	c8 00 00 00 	wfbi #\$0,#\$0,#\$0,#\$0,#\$0
+  4c:	cc 00 00 00 	wfb R0,R0,#\$0,#\$0,#\$0
+  50:	d0 00 00 00 	rcrisc R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  54:	d4 00 00 00 	fbcbinc R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  58:	d8 00 00 00 	rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  5c:	64 00 e0 00 	si R14
+  60:	b4 00 00 40 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0
+  64:	b4 00 00 00 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  68:	b4 00 00 40 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0
+  6c:	b4 00 00 00 	fbcbdr R0,#\$0,R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  70:	64 00 e0 00 	si R14
+  74:	b8 08 00 00 	rcfbcb #\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  78:	b8 00 00 00 	rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  7c:	b8 08 00 00 	rcfbcb #\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  80:	b8 00 00 00 	rcfbcb #\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  84:	64 00 e0 00 	si R14
+  88:	bc 20 00 00 	mrcfbcb R0,#\$0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  8c:	bc 10 00 00 	mrcfbcb R0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  90:	bc 00 00 00 	mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  94:	bc 20 00 00 	mrcfbcb R0,#\$0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  98:	bc 10 00 00 	mrcfbcb R0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  9c:	bc 00 00 00 	mrcfbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  a0:	64 00 e0 00 	si R14
+  a4:	d8 80 00 00 	rcxmode R0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0
+  a8:	d8 00 00 00 	rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  ac:	d8 80 00 00 	rcxmode R0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0
+  b0:	d8 00 00 00 	rcxmode R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  b4:	64 00 e0 00 	si R14
+  b8:	80 00 80 00 	ldctxt R0,R0,#\$1,#\$0,#\$0
+  bc:	80 00 00 00 	ldctxt R0,R0,#\$0,#\$0,#\$0
+  c0:	80 00 80 00 	ldctxt R0,R0,#\$1,#\$0,#\$0
+  c4:	80 00 00 00 	ldctxt R0,R0,#\$0,#\$0,#\$0
+  c8:	8c 00 08 00 	fbcb R0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0,#\$0
+  cc:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  d0:	c0 00 00 40 	cbcast #\$0,#\$1,#\$0
+  d4:	c0 00 00 00 	cbcast #\$0,#\$0,#\$0
+  d8:	64 00 e0 00 	si R14
+  dc:	8c 00 04 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0
+  e0:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  e4:	8c 00 04 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$1,#\$0,#\$0,#\$0
+  e8:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  ec:	64 00 e0 00 	si R14
+  f0:	8f 00 00 00 	fbcb R0,#\$3,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  f4:	8e 00 00 00 	fbcb R0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  f8:	8d 00 00 00 	fbcb R0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+  fc:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 100:	8f 00 00 00 	fbcb R0,#\$3,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 104:	8e 00 00 00 	fbcb R0,#\$2,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 108:	8d 00 00 00 	fbcb R0,#\$1,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 10c:	8c 00 00 00 	fbcb R0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0,#\$0
+ 110:	dc 00 00 00 	intlvr R0,#\$0,R0,#\$0,#\$0
diff --git a/gas/testsuite/gas/ms1/msys.s b/gas/testsuite/gas/ms1/msys.s
new file mode 100644
index 0000000..4ec028c
--- /dev/null
+++ b/gas/testsuite/gas/ms1/msys.s
@@ -0,0 +1,95 @@
+;; This file is a set of tests for the MorphoySys instructions.
+
+; Make sure that each mnemonic gives the proper opcode.  Use R0 and #0
+; for all operands so that everything but the opcode will be 0 in the
+; assembled instructions.
+
+	ldctxt R0,R0,#0,#0,#0
+	ldfb R0,R0,#0
+	stfb R0, R0, #0
+	fbcb R0,#0,#0,#0,#0,#0,#0,#0,#0
+	mfbcb R0,#0,R0,#0,#0,#0,#0,#0
+	fbcci R0,#0,#0,#0,#0,#0,#0,#0
+	fbrci R0,#0,#0,#0,#0,#0,#0,#0
+	fbcri R0,#0,#0,#0,#0,#0,#0,#0
+	fbrri R0,#0,#0,#0,#0,#0,#0,#0
+	mfbcci R0,#0,R0,#0,#0,#0,#0
+	mfbrci R0,#0,R0,#0,#0,#0,#0
+	mfbcri R0,#0,R0,#0,#0,#0,#0
+	mfbrri R0,#0,R0,#0,#0,#0,#0
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#0,#0
+	rcfbcb #0,#0,#0,#0,#0,#0,#0,#0,#0,#0
+	mrcfbcb R0,#0,#0,#0,#0,#0,#0,#0,#0
+	cbcast #0,#0,#0
+	dupcbcast #0,#0,#0,#0
+	wfbi #0,#0,#0,#0,#0
+	wfb R0,R0,#0,#0,#0
+	rcrisc R0,#0,R0,#0,#0,#0,#0,#0,#0
+	fbcbinc R0, #0, #0, #0, #0, #0, #0, #0
+	rcxmode R0, #0, #0, #0, #0, #0, #0, #0, #0
+
+; Check to make sure that the parse routines that allow predifined 
+; symbols (uppaer and lower case) to be used for some of the operands.
+
+; dup operand: dup, xx
+	si R14
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#dup,#0  ; dup = 1
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#xx,#0   ; xx = 0
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#DUP,#0 
+	fbcbdr R0,#0,R0,#0,#0,#0,#0,#0,#XX,#0   
+
+; ball operand: all, one
+	si R14
+	rcfbcb #0,#0,#all,#0,#0,#0,#0,#0,#0,#0  ; all = 1
+	rcfbcb #0,#0,#one,#0,#0,#0,#0,#0,#0,#0  ; one = 0
+	rcfbcb #0,#0,#ALL,#0,#0,#0,#0,#0,#0,#0  
+	rcfbcb #0,#0,#ONE,#0,#0,#0,#0,#0,#0,#0  
+
+; type operand: odd, even, oe 
+	si R14
+	mrcfbcb R0,#0,#oe,#0,#0,#0,#0,#0,#0     ; oe = 2
+	mrcfbcb R0,#0,#even,#0,#0,#0,#0,#0,#0   ; even = 1
+	mrcfbcb R0,#0,#odd,#0,#0,#0,#0,#0,#0    ; odd = 0
+	mrcfbcb R0,#0,#OE,#0,#0,#0,#0,#0,#0    
+	mrcfbcb R0,#0,#EVEN,#0,#0,#0,#0,#0,#0   
+	mrcfbcb R0,#0,#ODD,#0,#0,#0,#0,#0,#0    
+
+; xmode operand: pm, xm
+	si R14
+	rcxmode R0, #0, #0, #pm, #0, #0, #0, #0, #0  ; pm = 1
+	rcxmode R0, #0, #0, #xm, #0, #0, #0, #0, #0  ; xm = 0
+	rcxmode R0, #0, #0, #PM, #0, #0, #0, #0, #0  
+	rcxmode R0, #0, #0, #XM, #0, #0, #0, #0, #0 
+
+; rc, rc1, rc2 operands: r,c
+	si R14
+        ldctxt R0,R0,#r,#0,#0            ; rc operand.  r = 1 
+        ldctxt R0,R0,#c,#0,#0            ; rc operand.  c = 0 
+        ldctxt R0,R0,#R,#0,#0            
+        ldctxt R0,R0,#C,#0,#0           
+      
+	fbcb R0,#0,#0,#0,#r,#0,#0,#0,#0  ; rc1 operand.  r = 1
+	fbcb R0,#0,#0,#0,#c,#0,#0,#0,#0  ; rc1 operand.  c = 0
+
+	cbcast #0,#r,#0                  ; rc2 operand.  r = 1
+	cbcast #0,#c,#0                  ; rc2 opearnd.  c = 0
+
+; cbrb operand: cb, rb
+	si R14
+	fbcb R0,#0,#0,#0,#0,#rb,#0,#0,#0  ; rb = 1
+	fbcb R0,#0,#0,#0,#0,#cb,#0,#0,#0  ; cb = 0
+	fbcb R0,#0,#0,#0,#0,#RB,#0,#0,#0 
+	fbcb R0,#0,#0,#0,#0,#CB,#0,#0,#0  
+
+; rbbc operand: rt, br1, br2, cs
+	si R14
+	fbcb R0,#cs,#0,#0,#0,#0,#0,#0,#0   ; cs = 3
+	fbcb R0,#br2,#0,#0,#0,#0,#0,#0,#0  ; br2 = 2
+	fbcb R0,#br1,#0,#0,#0,#0,#0,#0,#0  ; br1 = 1
+	fbcb R0,#rt,#0,#0,#0,#cb,#0,#0,#0  ; rt = 0
+	fbcb R0,#CS,#0,#0,#0,#0,#0,#0,#0  
+	fbcb R0,#BR2,#0,#0,#0,#0,#0,#0,#0  
+	fbcb R0,#BR1,#0,#0,#0,#0,#0,#0,#0  
+	fbcb R0,#RT,#0,#0,#0,#cb,#0,#0,#0  
+
+	intlvr R0, #0, R0, #0, #0
diff --git a/gas/testsuite/gas/ms1/relocs.d b/gas/testsuite/gas/ms1/relocs.d
new file mode 100644
index 0000000..a9a66e9
--- /dev/null
+++ b/gas/testsuite/gas/ms1/relocs.d
@@ -0,0 +1,67 @@
+
+relocs.x:     file format elf32-mrisc1
+
+Contents of section .text:
+ 2000 00131000 37000004 12000000 3700fff8  ....7.......7...
+ 2010 03210000 03212215 03210001 03210000  .!...!"..!...!..
+ 2020 0321ffff 0321eeee 03210005 03210006  .!...!...!...!..
+ 2030 00675000                             .gP.            
+Contents of section .data:
+ 2134 0f000000 00000000 00000000 00000000  ................
+ 2144 00000000 00000000 00000000 00000000  ................
+ 2154 00000000 00000000 00000000 00000000  ................
+ 2164 00000000 00000000 00000000 00000000  ................
+ 2174 00000000 00000000 00000000 00000000  ................
+ 2184 00000000 00000000 00000000 00000000  ................
+ 2194 00000000 00000000 00000000 00000000  ................
+ 21a4 00000000 00000000 00000000 00000000  ................
+ 21b4 00000000 00000000 00000000 00000000  ................
+ 21c4 00000000 00000000 00000000 00000000  ................
+ 21d4 00000000 00000000 00000000 00000000  ................
+ 21e4 00000000 00000000 00000000 00000000  ................
+ 21f4 00000000 00000000 00000000 00000000  ................
+ 2204 00000000 00000000 00000000 00000000  ................
+ 2214 00020000 00000000 00000000 00000000  ................
+ 2224 00000000 00000000 00000000 00000000  ................
+ 2234 00000000 00000000 00000000 00000000  ................
+ 2244 00000000 00000000 00000000 00000000  ................
+ 2254 00000000 00000000 00000000 00000000  ................
+ 2264 00000000 00000000 00000000 00000000  ................
+ 2274 00000000 00000000 00000000 00000000  ................
+ 2284 00000000 00000000 00000000 00000000  ................
+ 2294 00000000 00000000 00000000 00000000  ................
+ 22a4 00000000 00000000 00000000 00000000  ................
+ 22b4 00000000 00000000 00000000 00000000  ................
+ 22c4 00000000 00000000 00000000 00000000  ................
+ 22d4 00000000 00000000 00000000 00000000  ................
+ 22e4 00000000 00000000 00000000 00000000  ................
+ 22f4 00000000 00000000 00000000 00000000  ................
+ 2304 00000000 00000000 00000000 00000000  ................
+ 2314 000003                               ...             
+Contents of section .sbss:
+Disassembly of section .text:
+
+00002000 <_start>:
+    2000:	00 13 10 00 	add R1,R1,R3
+
+00002004 <local>:
+    2004:	37 00 00 04 	jmp \$4
+
+00002008 <none>:
+    2008:	12 00 00 00 	or R0,R0,R0
+    200c:	37 00 ff f8 	jmp \$fffffff8
+    2010:	03 21 00 00 	addui R1,R2,#\$0
+    2014:	03 21 22 15 	addui R1,R2,#\$2215
+    2018:	03 21 00 01 	addui R1,R2,#\$1
+    201c:	03 21 00 00 	addui R1,R2,#\$0
+    2020:	03 21 ff ff 	addui R1,R2,#\$ffff
+    2024:	03 21 ee ee 	addui R1,R2,#\$eeee
+
+00002028 <dummy1>:
+    2028:	03 21 00 05 	addui R1,R2,#\$5
+
+0000202c <dummy2>:
+    202c:	03 21 00 06 	addui R1,R2,#\$6
+
+00002030 <i2>:
+    2030:	00 67 50 00 	add R5,R6,R7
diff --git a/gas/testsuite/gas/ms1/relocs.exp b/gas/testsuite/gas/ms1/relocs.exp
new file mode 100644
index 0000000..b02e208
--- /dev/null
+++ b/gas/testsuite/gas/ms1/relocs.exp
@@ -0,0 +1,35 @@
+# Relocation test.
+# This test is special because it exercises the linker's 
+
+proc ld_test { objects ldflags dest test } {
+    set ld_output [target_link $objects $dest $ldflags]
+    if [string match "" $ld_output] then { pass $test } else { fail $test }
+}
+
+
+proc objdump_test { exec flags dest test } {
+    set objcopy [find_binutils_prog objdump]
+    verbose -log "$objcopy $flags $exec > $dest"
+    catch "exec $objcopy $flags $exec > $dest" objdump_output
+    if [string match "" $objdump_output] then { pass $test } else { fail $test }
+}
+
+proc regexp_test { file1 file2 test } {
+    if [regexp_diff $file1 $file2] then { fail $test } else { pass $test }
+}
+
+
+global srcdir subdir
+if [istarget mrisc1*-*-* || istarget ms1-*] {
+    gas_test "relocs1.s" {-o relocs1.o} {} {assembling relocs1}
+
+    #    gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2}
+    #    ld_test {relocs1.o relocs2.o} {} {relocs.x} {linking relocs.x}
+    #    objdump_test {relocs.x} {-ds} {relocs.dump} {disassembling relocs.x}
+    #    regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly}
+
+    gas_test "relocs2.s" {-o relocs2.o} {} {assembling relocs2}
+    ld_test {relocs1.o relocs2.o} {} {relocs.x} {linking relocs.x}
+    objdump_test {relocs.x} {-ds} {relocs.dump} {disassembling relocs.x}
+    regexp_test {relocs.dump} "$srcdir/$subdir/relocs.d" {matching disassembly}
+}
diff --git a/gas/testsuite/gas/ms1/relocs1.s b/gas/testsuite/gas/ms1/relocs1.s
new file mode 100644
index 0000000..e874d50
--- /dev/null
+++ b/gas/testsuite/gas/ms1/relocs1.s
@@ -0,0 +1,31 @@
+;; This test is meant to exercise every unusual reloc supported
+;; by the mrisc port.  (Ok, so there's only one so far.  :P)
+
+	.text
+text:	
+	.global _start
+_start:	
+	add R1,R1,R3
+
+; Make sure local fixups work.
+local:
+        jmp (dummy2-dummy1)  
+
+; Test the PC16 reloc.
+none:
+	 or R0,R0,R0 ;nop to conform to scheduling restrictions
+	 jmp local                
+	                      
+; Test the %hi16 and %lo16 relocs
+addui R1,R2,#%hi16(d2)
+addui R1,R2,#%lo16(d2) 	
+addui R1,R2,#%hi16(65536)
+addui R1,R2,#%lo16(65536)
+addui R1,R2,#%hi16($FFFFEEEE)
+addui R1,R2,#%lo16($FFFFEEEE)
+
+dummy1: addui R1, R2, #5
+dummy2: addui R1, R2, #6
+
+	.data
+d1:	.byte $f
diff --git a/gas/testsuite/gas/ms1/relocs2.s b/gas/testsuite/gas/ms1/relocs2.s
new file mode 100644
index 0000000..7435406
--- /dev/null
+++ b/gas/testsuite/gas/ms1/relocs2.s
@@ -0,0 +1,22 @@
+	.text
+	;; Put code near the top of the address space
+text:
+	.global i2
+i2:	
+	
+	add R5, R6, R7
+
+	.data
+	;; Note that the .org that follows is more or less equivalent
+	;; to a .space, since the amount specified will be treated like
+	;; padding to be added between the .data section in relocs1.s
+	;; and this one.
+	;; Note also that the two test variables (d2 & d3) are intentionally
+	;; roughly $100 apart, so that the FR9 relocation processing in
+	;; bfd/elf32-ip2k.c (ip2k_final_link_relocate) is tested a little more.
+	.org $e0
+	.global d2
+d2:	.byte 2
+	.space $100
+	.global d3
+d3:	.byte 3