[ gas/ChangeLog ]

	* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
	ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
	(macro_build): Add case '2'.
	(macro): Expand M_BALIGN to nop, packrl.ph or balign.
	(validate_mips_insn): Add support for balign instruction.
	(mips_ip): Handle DSP R2 instructions. Support balign instruction.
	(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
	md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
	command line options.
	(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
	(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
	* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
	.set dspr2, .set nodspr2.

	[ gas/testsuite/ChangeLog ]
	* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
	DSP R2.
	* gas/mips/mips.exp: Run new test.

	[ include/opcode/Changelog ]
	* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
	(INSN_DSPR2): Add flag for DSP R2 instructions.
	(M_BALIGN): New macro.

	[ opcodes/ChangeLog ]
	* mips-dis.c (mips_arch_choices): Add DSP R2 support.
	(print_insn_args): Add support for balign instruction.
	* mips-opc.c (D33): New shortcut for DSP R2 instructions.
	(mips_builtin_opcodes): Add DSP R2 instructions.

	[ sim/mips/ChangeLog ]
	* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
	* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
	Add dsp2 to sim_igen_machine.
	* configure: Regenerate.
	* dsp.igen (do_ph_op): Add MUL support when op = 2.
	(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
	(mulq_rs.ph): Use do_ph_mulq.
	(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
	* mips.igen: Add dsp2 model and include dsp2.igen.
	(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
	for *mips32r2, *mips64r2, *dsp.
	(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
	for *mips32r2, *mips64r2, *dsp2.
	* dsp2.igen: New file for MIPS DSP REV 2 ASE.

	[ sim/testsuite/sim/mips/ChangeLog ]
	* basic.exp: Run the dsp2 test.
	* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
	* mips32-dsp2.s: New test.

8 files changed, 312 insertions, 19 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e692b9e..7c0799d 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,20 @@
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+            Chao-Ying Fu  <fu@mips.com>
+
+	* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
+	ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
+	(macro_build): Add case '2'.
+	(macro): Expand M_BALIGN to nop, packrl.ph or balign.
+	(validate_mips_insn): Add support for balign instruction.
+	(mips_ip): Handle DSP R2 instructions. Support balign instruction.
+	(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
+	md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
+	command line options.
+	(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
+	(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
+	* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
+	.set dspr2, .set nodspr2.
+
 2007-02-20  Nathan Sidwell  <nathan@codesourcery.com>
 
 	* config/tc-m68k.c (mcf5210a_ctrl, mcf52235_ctrl, mcf5225_ctrl): New.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 12fe476..056f7d2 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -193,6 +193,7 @@ struct mips_set_options
   int ase_mdmx;
   int ase_smartmips;
   int ase_dsp;
+  int ase_dspr2;
   int ase_mt;
   /* Whether we are assembling for the mips16 processor.  0 if we are
      not, 1 if we are, and -1 if the value has not been initialized.
@@ -244,7 +245,7 @@ static int file_mips_fp32 = -1;
 
 static struct mips_set_options mips_opts =
 {
-  ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
+  ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
 };
 
 /* These variables are filled in with the masks of registers used.
@@ -289,6 +290,13 @@ static int file_ase_dsp;
 
 #define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
 
+/* True if -mdspr2 was passed or implied by arguments passed on the
+   command line (e.g., by -march).  */
+static int file_ase_dspr2;
+
+#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2		\
+			        || mips_opts.isa == ISA_MIPS64R2)
+
 /* True if -mmt was passed or implied by arguments passed on the
    command line (e.g., by -march).  */
 static int file_ase_mt;
@@ -1052,6 +1060,7 @@ struct mips_cpu_info
 #define MIPS_CPU_ASE_MT		0x0008	/* CPU implements MT ASE */
 #define MIPS_CPU_ASE_MIPS3D	0x0010	/* CPU implements MIPS-3D ASE */
 #define MIPS_CPU_ASE_MDMX	0x0020	/* CPU implements MDMX ASE */
+#define MIPS_CPU_ASE_DSPR2	0x0040	/* CPU implements DSP R2 ASE */
 
 static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
 static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
@@ -3326,17 +3335,24 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
   assert (mo);
   assert (strcmp (name, mo->name) == 0);
 
-  /* Search until we get a match for NAME.  It is assumed here that
-     macros will never generate MDMX, MIPS-3D, DSP or MT instructions.  */
-  while (strcmp (fmt, mo->args) != 0
-	 || mo->pinfo == INSN_MACRO
-	 || !OPCODE_IS_MEMBER (mo,
+  while (1)
+    {
+      /* Search until we get a match for NAME.  It is assumed here that
+	 macros will never generate MDMX, MIPS-3D, or MT instructions.  */
+      if (strcmp (fmt, mo->args) == 0
+	  && mo->pinfo != INSN_MACRO
+	  && OPCODE_IS_MEMBER (mo,
 			       (mips_opts.isa
 				| (mips_opts.mips16 ? INSN_MIPS16 : 0)
+				| (mips_opts.ase_dsp ? INSN_DSP : 0)
+				| ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
+				   ? INSN_DSP64 : 0)
+				| (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
 				| (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
 			       mips_opts.arch)
-	 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
-    {
+	  && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
+	break;
+
       ++mo;
       assert (mo->name);
       assert (strcmp (name, mo->name) == 0);
@@ -3387,6 +3403,10 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
 	    }
 	  continue;
 
+	case '2':
+	  INSERT_OPERAND (BP, insn, va_arg (args, int));
+	  continue;
+
 	case 't':
 	case 'w':
 	case 'E':
@@ -4615,6 +4635,22 @@ macro (struct mips_cl_insn *ip)
       macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
       break;
 
+    case M_BALIGN:
+      switch (imm_expr.X_add_number)
+	{
+	case 0:
+	  macro_build (NULL, "nop", "");
+	  break;
+	case 2:
+	  macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
+	  break;
+	default:
+	  macro_build (NULL, "balign", "t,s,2", treg, sreg,
+		       (int)imm_expr.X_add_number);
+	  break;
+	}
+      break;
+
     case M_BEQ_I:
       s = "beq";
       goto beq_i;
@@ -8222,6 +8258,7 @@ validate_mips_insn (const struct mips_opcode *opc)
       case '%': USE_BITS (OP_MASK_VECALIGN,	OP_SH_VECALIGN); break;
       case '[': break;
       case ']': break;
+      case '2': USE_BITS (OP_MASK_BP,		OP_SH_BP);	break;
       case '3': USE_BITS (OP_MASK_SA3,  	OP_SH_SA3);	break;
       case '4': USE_BITS (OP_MASK_SA4,  	OP_SH_SA4);	break;
       case '5': USE_BITS (OP_MASK_IMM8, 	OP_SH_IMM8);	break;
@@ -8399,6 +8436,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 	      		     | (mips_opts.ase_dsp ? INSN_DSP : 0)
 	      		     | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
 				? INSN_DSP64 : 0)
+	      		     | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
 	      		     | (mips_opts.ase_mt ? INSN_MT : 0)
 			     | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
 			     | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
@@ -8454,6 +8492,20 @@ mips_ip (char *str, struct mips_cl_insn *ip)
 		return;
 	      break;
 
+	    case '2': /* dsp 2-bit unsigned immediate in bit 11 */
+	      my_getExpression (&imm_expr, s);
+	      check_absolute_expr (ip, &imm_expr);
+	      if ((unsigned long) imm_expr.X_add_number != 1
+		  && (unsigned long) imm_expr.X_add_number != 3)
+		{
+		  as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
+			  (unsigned long) imm_expr.X_add_number);
+		}
+	      INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
+	      imm_expr.X_op = O_absent;
+	      s = expr_end;
+	      continue;
+
 	    case '3': /* dsp 3-bit unsigned immediate in bit 21 */
 	      my_getExpression (&imm_expr, s);
 	      check_absolute_expr (ip, &imm_expr);
@@ -10826,9 +10878,13 @@ struct option md_longopts[] =
   {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
 #define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
   {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
+#define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
+  {"mdspr2", no_argument, NULL, OPTION_DSPR2},
+#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
+  {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
 
   /* Old-style architecture options.  Don't add more of these.  */
-#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 12)
+#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
 #define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
   {"m4650", no_argument, NULL, OPTION_M4650},
 #define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
@@ -11079,10 +11135,22 @@ md_parse_option (int c, char *arg)
 
     case OPTION_DSP:
       mips_opts.ase_dsp = 1;
+      mips_opts.ase_dspr2 = 0;
       break;
 
     case OPTION_NO_DSP:
       mips_opts.ase_dsp = 0;
+      mips_opts.ase_dspr2 = 0;
+      break;
+
+    case OPTION_DSPR2:
+      mips_opts.ase_dspr2 = 1;
+      mips_opts.ase_dsp = 1;
+      break;
+
+    case OPTION_NO_DSPR2:
+      mips_opts.ase_dspr2 = 0;
+      mips_opts.ase_dsp = 0;
       break;
 
     case OPTION_MT:
@@ -11497,10 +11565,19 @@ mips_after_parse_args (void)
       as_warn ("%s ISA does not support DSP ASE", 
 	       mips_cpu_info_from_isa (mips_opts.isa)->name);
 
+  if (mips_opts.ase_dspr2 == -1)
+    {
+      mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
+      mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
+    }
+  if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
+      as_warn ("%s ISA does not support DSP R2 ASE",
+	       mips_cpu_info_from_isa (mips_opts.isa)->name);
+
   if (mips_opts.ase_mt == -1)
     mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
   if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
-      as_warn ("%s ISA does not support MT ASE", 
+      as_warn ("%s ISA does not support MT ASE",
 	       mips_cpu_info_from_isa (mips_opts.isa)->name);
 
   file_mips_isa = mips_opts.isa;
@@ -11509,6 +11586,7 @@ mips_after_parse_args (void)
   file_ase_mdmx = mips_opts.ase_mdmx;
   file_ase_smartmips = mips_opts.ase_smartmips;
   file_ase_dsp = mips_opts.ase_dsp;
+  file_ase_dspr2 = mips_opts.ase_dspr2;
   file_ase_mt = mips_opts.ase_mt;
   mips_opts.gp32 = file_mips_gp32;
   mips_opts.fp32 = file_mips_fp32;
@@ -12399,9 +12477,26 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
 	as_warn ("%s ISA does not support DSP ASE", 
 		 mips_cpu_info_from_isa (mips_opts.isa)->name);
       mips_opts.ase_dsp = 1;
+      mips_opts.ase_dspr2 = 0;
     }
   else if (strcmp (name, "nodsp") == 0)
-    mips_opts.ase_dsp = 0;
+    {
+      mips_opts.ase_dsp = 0;
+      mips_opts.ase_dspr2 = 0;
+    }
+  else if (strcmp (name, "dspr2") == 0)
+    {
+      if (!ISA_SUPPORTS_DSPR2_ASE)
+	as_warn ("%s ISA does not support DSP R2 ASE",
+		 mips_cpu_info_from_isa (mips_opts.isa)->name);
+      mips_opts.ase_dspr2 = 1;
+      mips_opts.ase_dsp = 1;
+    }
+  else if (strcmp (name, "nodspr2") == 0)
+    {
+      mips_opts.ase_dspr2 = 0;
+      mips_opts.ase_dsp = 0;
+    }
   else if (strcmp (name, "mt") == 0)
     {
       if (!ISA_SUPPORTS_MT_ASE)
@@ -14085,6 +14180,7 @@ mips_elf_final_processing (void)
   /* Set MIPS ELF flags for ASEs.  */
   /* We may need to define a new flag for DSP ASE, and set this flag when
      file_ase_dsp is true.  */
+  /* Same for DSP R2.  */
   /* We may need to define a new flag for MT ASE, and set this flag when
      file_ase_mt is true.  */
   if (file_ase_mips16)
@@ -14825,6 +14921,9 @@ MIPS options:\n\
 -mdsp			generate DSP instructions\n\
 -mno-dsp		do not generate DSP instructions\n"));
   fprintf (stream, _("\
+-mdspr2			generate DSP R2 instructions\n\
+-mno-dspr2		do not generate DSP R2 instructions\n"));
+  fprintf (stream, _("\
 -mmt			generate MT instructions\n\
 -mno-mt			do not generate MT instructions\n"));
   fprintf (stream, _("\
diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index fed4213..c846805 100644
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -372,6 +372,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mips3d}] [@b{-no-mips3d}]
    [@b{-mdmx}] [@b{-no-mdmx}]
    [@b{-mdsp}] [@b{-mno-dsp}]
+   [@b{-mdspr2}] [@b{-mno-dspr2}]
    [@b{-mmt}] [@b{-mno-mt}]
    [@b{-mdebug}] [@b{-no-mdebug}]
    [@b{-mpdr}] [@b{-mno-pdr}]
@@ -1036,10 +1037,17 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 25071d9..b14b5fb 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -137,10 +137,17 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
@@ -520,13 +527,22 @@ from the MDMX Application Specific Extension from that point on
 in the assembly.  The @code{.set nomdmx} directive prevents MDMX
 instructions from being accepted.
 
-@cindex MIPS DSP instruction generation override
+@cindex MIPS DSP Release 1 instruction generation override
 @kindex @code{.set dsp}
 @kindex @code{.set nodsp}
 The directive @code{.set dsp} makes the assembler accept instructions
-from the DSP Application Specific Extension from that point on
-in the assembly.  The @code{.set nodsp} directive prevents DSP
-instructions from being accepted.
+from the DSP Release 1 Application Specific Extension from that point
+on in the assembly.  The @code{.set nodsp} directive prevents DSP
+Release 1 instructions from being accepted.
+
+@cindex MIPS DSP Release 2 instruction generation override
+@kindex @code{.set dspr2}
+@kindex @code{.set nodspr2}
+The directive @code{.set dspr2} makes the assembler accept instructions
+from the DSP Release 2 Application Specific Extension from that point
+on in the assembly.  This dirctive implies @code{.set dsp}.  The
+@code{.set nodspr2} directive prevents DSP Release 2 instructions from
+being accepted.
 
 @cindex MIPS MT instruction generation override
 @kindex @code{.set mt}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e69c151..f49f1f0 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2007-02-20  Thiemo Seufer  <ths@mips.com>
+            Chao-Ying Fu  <fu@mips.com>
+
+	* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
+	DSP R2.
+	* gas/mips/mips.exp: Run new test.
+
 2007-02-19  Andreas Krebbel  <krebbel1@de.ibm.com>
 
 	* gas/s390/esa-g5.d (cfxbr, cfebr, cfdbr): Exchanged floating
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 50c608a..ae0276d 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -772,6 +772,7 @@ if { [istarget mips*-*-vxworks*] } {
 
     run_dump_test_arches "smartmips"	[mips_arch_list_matching mips32 !gpr64]
     run_dump_test_arches "mips32-dsp"	[mips_arch_list_matching mips32r2]
+    run_dump_test_arches "mips32-dspr2"	[mips_arch_list_matching mips32r2]
     run_dump_test_arches "mips64-dsp"	[mips_arch_list_matching mips64r2]
     run_dump_test_arches "mips32-mt"	[mips_arch_list_matching mips32r2 !gpr64]
 
diff --git a/gas/testsuite/gas/mips/mips32-dspr2.d b/gas/testsuite/gas/mips/mips32-dspr2.d
new file mode 100644
index 0000000..90c20ef
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dspr2.d
@@ -0,0 +1,72 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev2 for MIPS32
+#as: -mdspr2 -32
+
+# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 7c010052 	absq_s\.qb	zero,at
+0+0004 <[^>]*> 7c430a10 	addu\.ph	at,v0,v1
+0+0008 <[^>]*> 7c641310 	addu_s\.ph	v0,v1,a0
+0+000c <[^>]*> 7c851818 	adduh\.qb	v1,a0,a1
+0+0010 <[^>]*> 7ca62098 	adduh_r\.qb	a0,a1,a2
+0+0014 <[^>]*> 7cc50031 	append	a1,a2,0x0
+0+0018 <[^>]*> 7cc5f831 	append	a1,a2,0x1f
+0+001c <[^>]*> 00000000 	nop
+0+0020 <[^>]*> 7ce60c31 	balign	a2,a3,0x1
+0+0024 <[^>]*> 7cc73391 	packrl.ph	a2,a2,a3
+0+0028 <[^>]*> 7ce61c31 	balign	a2,a3,0x3
+0+002c <[^>]*> 7ce83611 	cmpgdu\.eq\.qb	a2,a3,t0
+0+0030 <[^>]*> 7d093e51 	cmpgdu\.lt\.qb	a3,t0,t1
+0+0034 <[^>]*> 7d2a4691 	cmpgdu\.le\.qb	t0,t1,t2
+0+0038 <[^>]*> 7d2a0030 	dpa\.w\.ph	\$ac0,t1,t2
+0+003c <[^>]*> 7d4b0870 	dps\.w\.ph	\$ac1,t2,t3
+0+0040 <[^>]*> 716c1000 	madd	\$ac2,t3,t4
+0+0044 <[^>]*> 718d1801 	maddu	\$ac3,t4,t5
+0+0048 <[^>]*> 71ae0004 	msub	t5,t6
+0+004c <[^>]*> 71cf0805 	msubu	\$ac1,t6,t7
+0+0050 <[^>]*> 7e117b18 	mul\.ph	t7,s0,s1
+0+0054 <[^>]*> 7e328398 	mul_s\.ph	s0,s1,s2
+0+0058 <[^>]*> 7e538dd8 	mulq_rs\.w	s1,s2,s3
+0+005c <[^>]*> 7e749790 	mulq_s\.ph	s2,s3,s4
+0+0060 <[^>]*> 7e959d98 	mulq_s\.w	s3,s4,s5
+0+0064 <[^>]*> 7e9510b0 	mulsa\.w\.ph	\$ac2,s4,s5
+0+0068 <[^>]*> 02b61818 	mult	\$ac3,s5,s6
+0+006c <[^>]*> 02d70019 	multu	s6,s7
+0+0070 <[^>]*> 7f19bb51 	precr\.qb\.ph	s7,t8,t9
+0+0074 <[^>]*> 7f380791 	precr_sra\.ph\.w	t8,t9,0x0
+0+0078 <[^>]*> 7f38ff91 	precr_sra\.ph\.w	t8,t9,0x1f
+0+007c <[^>]*> 7f5907d1 	precr_sra_r\.ph\.w	t9,k0,0x0
+0+0080 <[^>]*> 7f59ffd1 	precr_sra_r\.ph\.w	t9,k0,0x1f
+0+0084 <[^>]*> 7f7a0071 	prepend	k0,k1,0x0
+0+0088 <[^>]*> 7f7af871 	prepend	k0,k1,0x1f
+0+008c <[^>]*> 7c1cd913 	shra\.qb	k1,gp,0x0
+0+0090 <[^>]*> 7cfcd913 	shra\.qb	k1,gp,0x7
+0+0094 <[^>]*> 7c1de153 	shra_r\.qb	gp,sp,0x0
+0+0098 <[^>]*> 7cfde153 	shra_r\.qb	gp,sp,0x7
+0+009c <[^>]*> 7ffee993 	shrav\.qb	sp,s8,ra
+0+00a0 <[^>]*> 7c1ff1d3 	shrav_r\.qb	s8,ra,zero
+0+00a4 <[^>]*> 7c00fe53 	shrl\.ph	ra,zero,0x0
+0+00a8 <[^>]*> 7de0fe53 	shrl\.ph	ra,zero,0xf
+0+00ac <[^>]*> 7c4106d3 	shrlv\.ph	zero,at,v0
+0+00b0 <[^>]*> 7c430a50 	subu\.ph	at,v0,v1
+0+00b4 <[^>]*> 7c641350 	subu_s\.ph	v0,v1,a0
+0+00b8 <[^>]*> 7c851858 	subuh\.qb	v1,a0,a1
+0+00bc <[^>]*> 7ca620d8 	subuh_r\.qb	a0,a1,a2
+0+00c0 <[^>]*> 7cc72a18 	addqh\.ph	a1,a2,a3
+0+00c4 <[^>]*> 7ce83298 	addqh_r\.ph	a2,a3,t0
+0+00c8 <[^>]*> 7d093c18 	addqh\.w	a3,t0,t1
+0+00cc <[^>]*> 7d2a4498 	addqh_r\.w	t0,t1,t2
+0+00d0 <[^>]*> 7d4b4a58 	subqh\.ph	t1,t2,t3
+0+00d4 <[^>]*> 7d6c52d8 	subqh_r\.ph	t2,t3,t4
+0+00d8 <[^>]*> 7d8d5c58 	subqh\.w	t3,t4,t5
+0+00dc <[^>]*> 7dae64d8 	subqh_r\.w	t4,t5,t6
+0+00e0 <[^>]*> 7dae0a30 	dpax\.w\.ph	\$ac1,t5,t6
+0+00e4 <[^>]*> 7dcf1270 	dpsx\.w\.ph	\$ac2,t6,t7
+0+00e8 <[^>]*> 7df01e30 	dpaqx_s\.w\.ph	\$ac3,t7,s0
+0+00ec <[^>]*> 7e1106b0 	dpaqx_sa\.w\.ph	\$ac0,s0,s1
+0+00f0 <[^>]*> 7e320e70 	dpsqx_s\.w\.ph	\$ac1,s1,s2
+0+00f4 <[^>]*> 7e5316f0 	dpsqx_sa\.w\.ph	\$ac2,s2,s3
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/mips32-dspr2.s b/gas/testsuite/gas/mips/mips32-dspr2.s
new file mode 100644
index 0000000..e22d798
--- /dev/null
+++ b/gas/testsuite/gas/mips/mips32-dspr2.s
@@ -0,0 +1,73 @@
+# source file to test assembly of MIPS DSP ASE Rev2 for MIPS32 instructions
+
+	.set noreorder
+	.set noat
+
+	.text
+text_label:
+
+	absq_s.qb	$0,$1
+	addu.ph		$1,$2,$3
+	addu_s.ph	$2,$3,$4
+	adduh.qb	$3,$4,$5
+	adduh_r.qb	$4,$5,$6
+	append		$5,$6,0
+	append		$5,$6,31
+	balign		$6,$7,0
+	balign		$6,$7,1
+	balign		$6,$7,2
+	balign		$6,$7,3
+	cmpgdu.eq.qb	$6,$7,$8
+	cmpgdu.lt.qb	$7,$8,$9
+	cmpgdu.le.qb	$8,$9,$10
+	dpa.w.ph	$ac0,$9,$10
+	dps.w.ph	$ac1,$10,$11
+	madd		$ac2,$11,$12
+	maddu		$ac3,$12,$13
+	msub		$ac0,$13,$14
+	msubu		$ac1,$14,$15
+	mul.ph		$15,$16,$17
+	mul_s.ph	$16,$17,$18
+	mulq_rs.w	$17,$18,$19
+	mulq_s.ph	$18,$19,$20
+	mulq_s.w	$19,$20,$21
+	mulsa.w.ph	$ac2,$20,$21
+	mult		$ac3,$21,$22
+	multu		$ac0,$22,$23
+	precr.qb.ph	$23,$24,$25
+	precr_sra.ph.w	$24,$25,0
+	precr_sra.ph.w	$24,$25,31
+	precr_sra_r.ph.w	$25,$26,0
+	precr_sra_r.ph.w	$25,$26,31
+	prepend		$26,$27,0
+	prepend		$26,$27,31
+	shra.qb		$27,$28,0
+	shra.qb		$27,$28,7
+	shra_r.qb	$28,$29,0
+	shra_r.qb	$28,$29,7
+	shrav.qb	$29,$30,$31
+	shrav_r.qb	$30,$31,$0
+	shrl.ph		$31,$0,0
+	shrl.ph		$31,$0,15
+	shrlv.ph	$0,$1,$2
+	subu.ph		$1,$2,$3
+	subu_s.ph	$2,$3,$4
+	subuh.qb	$3,$4,$5
+	subuh_r.qb	$4,$5,$6
+	addqh.ph        $5,$6,$7
+	addqh_r.ph      $6,$7,$8
+	addqh.w         $7,$8,$9
+	addqh_r.w       $8,$9,$10
+	subqh.ph        $9,$10,$11
+	subqh_r.ph      $10,$11,$12
+	subqh.w         $11,$12,$13
+	subqh_r.w       $12,$13,$14
+	dpax.w.ph       $ac1,$13,$14
+	dpsx.w.ph       $ac2,$14,$15
+	dpaqx_s.w.ph    $ac3,$15,$16
+	dpaqx_sa.w.ph   $ac0,$16,$17
+	dpsqx_s.w.ph    $ac1,$17,$18
+	dpsqx_sa.w.ph   $ac2,$18,$19
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space	8