aarch64: Add support for FEAT_SME2p1 instructions.

Hi,

This patch add support for FEAT_SME2p1 and "movaz" instructions
along with the optional flag +sme2p1.

Following "movaz" instructions are add:
Move and zero two ZA tile slices to vector registers.
Move and zero four ZA tile slices to vector registers.

Regression testing for aarch64-none-elf target and found no regressions.

Ok for binutils-master?

Regards,
Srinath.

5 files changed, 104 insertions, 0 deletions

diff --git a/gas/NEWS b/gas/NEWS
index 43662fa..542ded4 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -3,6 +3,9 @@
   hand-written asm using the new command line option --scfi=experimental on
   x86-64.  Only System V AMD64 ABI is supported.
 
+* Add support for the AArch64 Scalable Matrix Extension version 2.1 (SME2.1)
+  instructions.
+
 * Add support for 'armv8.9-a' and 'armv9.4-a' for -march in Arm GAS.
 
 * Initial support for Intel APX: 32 GPRs, NDD, PUSH2/POP2 and PUSHP/POPP.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index bc40d12..34159c2 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4492,6 +4492,7 @@ parse_sme_immediate (char **str, int64_t *imm)
 
    [<Wv>, <imm>]
    [<Wv>, #<imm>]
+   [<Ws>, <offsf>:<offsl>]
 
    Return true on success, populating OPND with the parsed index.  */
 
@@ -4592,6 +4593,7 @@ parse_sme_za_index (char **str, struct aarch64_indexed_za *opnd)
    <Pm>.<T>[<Wv>< #<imm>]
    ZA[<Wv>, #<imm>]
    <ZAn><HV>.<T>[<Wv>, #<imm>]
+   <ZAn><HV>.<T>[<Ws>, <offsf>:<offsl>]
 
    FLAGS is as for parse_typed_reg.  */
 
@@ -7865,6 +7867,21 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	  info->qualifier = qualifier;
 	  break;
 
+	case AARCH64_OPND_SME_ZA_array_vrsb_1:
+	case AARCH64_OPND_SME_ZA_array_vrsh_1:
+	case AARCH64_OPND_SME_ZA_array_vrss_1:
+	case AARCH64_OPND_SME_ZA_array_vrsd_1:
+	case AARCH64_OPND_SME_ZA_array_vrsb_2:
+	case AARCH64_OPND_SME_ZA_array_vrsh_2:
+	case AARCH64_OPND_SME_ZA_array_vrss_2:
+	case AARCH64_OPND_SME_ZA_array_vrsd_2:
+	  if (!parse_dual_indexed_reg (&str, REG_TYPE_ZATHV,
+				       &info->indexed_za, &qualifier, 0))
+	    goto failure;
+	  info->qualifier = qualifier;
+	  break;
+
+
 	case AARCH64_OPND_SME_VLxN_10:
 	case AARCH64_OPND_SME_VLxN_13:
 	  po_strict_enum_or_fail (aarch64_sme_vlxn_array);
@@ -10336,6 +10353,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"d128",		AARCH64_FEATURE (D128),
 			AARCH64_FEATURE (LSE128)},
   {"b16b16",		AARCH64_FEATURE (B16B16), AARCH64_FEATURE (SVE2)},
+  {"sme2p1",		AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index ccf18ee..1f3a4fb 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -276,6 +276,8 @@ automatically cause those extensions to be disabled.
  @tab Enable TRCIT instruction.
 @item @code{d128} @tab Armv9.4-A @tab No
  @tab Enable the 128-bit Page Descriptor Extension.  This implies @code{lse128}.
+@item @code{sme2p1} @tab N/A @tab No
+ @tab Enable the SME2.1 Extension.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.d b/gas/testsuite/gas/aarch64/sme2p1-1.d
new file mode 100644
index 0000000..a6e7b76
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-1.d
@@ -0,0 +1,42 @@
+#name: Test of SME2.1 movaz instructions.
+#as: -march=armv9.4-a+sme2p1
+#objdump: -dr
+
+[^:]+:     file format .*
+
+
+[^:]+:
+
+[^:]+:
+.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
+.*:	c046c260 	movaz	{z0.h-z1.h}, za0v.h \[w14, 6:7\]
+.*:	c086c220 	movaz	{z0.s-z1.s}, za0v.s \[w14, 2:3\]
+.*:	c0c6c200 	movaz	{z0.d-z1.d}, za0v.d \[w14, 0:1\]
+.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
+.*:	c0462260 	movaz	{z0.h-z1.h}, za0h.h \[w13, 6:7\]
+.*:	c0864220 	movaz	{z0.s-z1.s}, za0h.s \[w14, 2:3\]
+.*:	c0c66200 	movaz	{z0.d-z1.d}, za0h.d \[w15, 0:1\]
+.*:	c006c260 	movaz	{z0.b-z1.b}, za0v.b \[w14, 6:7\]
+.*:	c046c2e0 	movaz	{z0.h-z1.h}, za1v.h \[w14, 6:7\]
+.*:	c086c2a0 	movaz	{z0.s-z1.s}, za2v.s \[w14, 2:3\]
+.*:	c0c6c260 	movaz	{z0.d-z1.d}, za3v.d \[w14, 0:1\]
+.*:	c00602e0 	movaz	{z0.b-z1.b}, za0h.b \[w12, 14:15\]
+.*:	c04622e0 	movaz	{z0.h-z1.h}, za1h.h \[w13, 6:7\]
+.*:	c08642a0 	movaz	{z0.s-z1.s}, za2h.s \[w14, 2:3\]
+.*:	c0c66260 	movaz	{z0.d-z1.d}, za3h.d \[w15, 0:1\]
+.*:	c006c660 	movaz	{z0.b-z3.b}, za0v.b \[w14, 12:15\]
+.*:	c046c620 	movaz	{z0.h-z3.h}, za0v.h \[w14, 4:7\]
+.*:	c086c600 	movaz	{z0.s-z3.s}, za0v.s \[w14, 0:3\]
+.*:	c0c6c600 	movaz	{z0.d-z3.d}, za0v.d \[w14, 0:3\]
+.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
+.*:	c0462620 	movaz	{z0.h-z3.h}, za0h.h \[w13, 4:7\]
+.*:	c0864600 	movaz	{z0.s-z3.s}, za0h.s \[w14, 0:3\]
+.*:	c0c66600 	movaz	{z0.d-z3.d}, za0h.d \[w15, 0:3\]
+.*:	c006c640 	movaz	{z0.b-z3.b}, za0v.b \[w14, 8:11\]
+.*:	c046c660 	movaz	{z0.h-z3.h}, za1v.h \[w14, 4:7\]
+.*:	c086c640 	movaz	{z0.s-z3.s}, za2v.s \[w14, 0:3\]
+.*:	c0c6c660 	movaz	{z0.d-z3.d}, za3v.d \[w14, 0:3\]
+.*:	c0060660 	movaz	{z0.b-z3.b}, za0h.b \[w12, 12:15\]
+.*:	c0462660 	movaz	{z0.h-z3.h}, za1h.h \[w13, 4:7\]
+.*:	c0864640 	movaz	{z0.s-z3.s}, za2h.s \[w14, 0:3\]
+.*:	c0c66660 	movaz	{z0.d-z3.d}, za3h.d \[w15, 0:3\]
diff --git a/gas/testsuite/gas/aarch64/sme2p1-1.s b/gas/testsuite/gas/aarch64/sme2p1-1.s
new file mode 100644
index 0000000..77481d4
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p1-1.s
@@ -0,0 +1,39 @@
+	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
+	movaz {z0.h - z1.h}, ZA0V.H [w14, 6:7]
+	movaz {z0.s - z1.s}, ZA0V.S [w14, 2:3]
+	movaz {z0.d - z1.d}, ZA0V.D [w14, 0:1]
+
+	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
+	movaz {z0.h - z1.h}, ZA0H.H [w13, 6:7]
+	movaz {z0.s - z1.s}, ZA0H.S [w14, 2:3]
+	movaz {z0.d - z1.d}, ZA0H.D [w15, 0:1]
+
+	movaz {z0.b - z1.b}, ZA0V.B [w14, 6:7]
+	movaz {z0.h - z1.h}, ZA1V.H [w14, 6:7]
+	movaz {z0.s - z1.s}, ZA2V.S [w14, 2:3]
+	movaz {z0.d - z1.d}, ZA3V.D [w14, 0:1]
+
+	movaz {z0.b - z1.b}, ZA0H.B [w12, 14:15]
+	movaz {z0.h - z1.h}, ZA1H.H [w13, 6:7]
+	movaz {z0.s - z1.s}, ZA2H.S [w14, 2:3]
+	movaz {z0.d - z1.d}, ZA3H.D [w15, 0:1]
+
+	movaz {z0.b - z3.b}, ZA0V.B [w14, 12:15]
+	movaz {z0.h - z3.h}, ZA0V.H [w14, 4:7]
+	movaz {z0.s - z3.s}, ZA0V.S [w14, 0:3]
+	movaz {z0.d - z3.d}, ZA0V.D [w14, 0:3]
+
+	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
+	movaz {z0.h - z3.h}, ZA0H.H [w13, 4:7]
+	movaz {z0.s - z3.s}, ZA0H.S [w14, 0:3]
+	movaz {z0.d - z3.d}, ZA0H.D [w15, 0:3]
+
+	movaz {z0.b - z3.b}, ZA0V.B [w14, 8:11]
+	movaz {z0.h - z3.h}, ZA1V.H [w14, 4:7]
+	movaz {z0.s - z3.s}, ZA2V.S [w14, 0:3]
+	movaz {z0.d - z3.d}, ZA3V.D [w14, 0:3]
+
+	movaz {z0.b - z3.b}, ZA0H.B [w12, 12:15]
+	movaz {z0.h - z3.h}, ZA1H.H [w13, 4:7]
+	movaz {z0.s - z3.s}, ZA2H.S [w14, 0:3]
+	movaz {z0.d - z3.d}, ZA3H.D [w15, 0:3]