aarch64: Add FEAT_SPECRES2 support

This patch add supports for FEAT_SPECRES2 "Enhanced speculation
restriction instructions" adding the "cosp" instruction.

This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+.  It is
enabled by the +predres2 march flag.

6 files changed, 25 insertions, 0 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 8654049..6672470 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10259,6 +10259,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sha2",		AARCH64_FEATURE (SHA2), AARCH64_FEATURE (FP)},
   {"sb",		AARCH64_FEATURE (SB), AARCH64_NO_FEATURES},
   {"predres",		AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES},
+  {"predres2",		AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)},
   {"aes",		AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)},
   {"sm4",		AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)},
   {"sha3",		AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 2bfb98a..d1209d1 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -270,6 +270,8 @@ automatically cause those extensions to be disabled.
  @tab Enable the 128-bit Atomic Instructions extension.  This implies @code{lse}.
 @item @code{rasv2} @tab N/A @tab Armv9.4-A or later
  @tab Enable the Reliability, Availability and Serviceability extension v2.
+@item @code{predres2} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
+ @tab Enable Prediction instructions.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.d b/gas/testsuite/gas/aarch64/illegal-predres2-1.d
new file mode 100644
index 0000000..f858afd
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.d
@@ -0,0 +1,3 @@
+#as: -march=armv8-a
+#source: predres2.s
+#error_output: illegal-predres2-1.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/illegal-predres2-1.l b/gas/testsuite/gas/aarch64/illegal-predres2-1.l
new file mode 100644
index 0000000..15f5680
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/illegal-predres2-1.l
@@ -0,0 +1,5 @@
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cosp rctx,x1'
+[^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx'
+[^:]*:[0-9]+: Error: selected processor does not support `cfp rctx,x1'
diff --git a/gas/testsuite/gas/aarch64/predres2.d b/gas/testsuite/gas/aarch64/predres2.d
new file mode 100644
index 0000000..cc5ea08
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres2.d
@@ -0,0 +1,10 @@
+#as: -march=armv8-a+predres2
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d50b73c1 	cosp	rctx, x1
+.*:	d50b7381 	cfp	rctx, x1
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/predres2.s b/gas/testsuite/gas/aarch64/predres2.s
new file mode 100644
index 0000000..3f6f88c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/predres2.s
@@ -0,0 +1,4 @@
+/* File to test the +predres2 option.  */
+func:
+	cosp rctx, x1
+	cfp rctx, x1