2008-02-20 Paul Brook <paul@codesourcery.com>

	ld/
	* emultempl/armelf.em (OPTION_FIX_V4BX_INTERWORKING): Define.
	(PARSE_AND_LIST_LONGOPTS): Add fix-v4bx-interworking.
	(PARSE_AND_LIST_OPTIONS): Ditto.
	(PARSE_AND_LIST_ARGS_CASES): Handle OPTION_FIX_V4BX_INTERWORKING.
	* emulparams/armelf.sh (OTHER_TEXT_SECTIONS): Add .v4_bx.
	* emulparams/armelf_linux.sh (OTHER_TEXT_SECTIONS): Ditto.
	* emulparams/armnto.sh (OTHER_TEXT_SECTIONS): Ditto.
	* ld.texinfo: Document --fix-v4bx-interworking.

	ld/testsuite/
	* ld-arm/armv4-bx.d: New test.
	* ld-arm/armv4-bx.s: New test.
	* ld-arm/arm.ld: Add .v4bx.
	* ld-arm/arm-elf.exp: Add armv4-bx.

	gas/testsuite/
	* gas/arm/thumb.d: Exclude EABI targets.
	* gas/arm/arch4t.d: Exclude EABI targts.
	* gas/arm/v4bx.d: New test.
	* gas/arm/v4bx.s: New test.
	* gas/arm/thumb-eabi.d: New test.
	* gas/arm/arch4t-eabi.d: New test.

	gas/
	* config/tc-arm.c (fix_v4bx): New variable.
	(do_bx): Generate V4BX relocations.
	(md_assemble): Allow bx on v4 codes when fix_v4bx.
	(md_apply_fix): Handle BFD_RELOC_ARM_V4BX.
	(tc_gen_reloc): Ditto.
	(OPTION_FIX_V4BX): Define.
	(md_longopts): Add fix-v4bx.
	(md_parse_option): Handle OPTION_FIX_V4BX.
	(md_show_usage): Document --fix-v4bx.
	* doc/c-arm.texi: Document --fix-v4bx.

	bfd/
	* reloc.c: Add BFD_RELOC_ARM_V4BX.
	* elf32-arm.c (elf32_arm_reloc_map): Add BFD_RELOC_ARM_V4BX.
	(ARM_BX_GLUE_SECTION_NAME, ARM_BX_GLUE_SECTION_NAME): Define.
	(elf32_arm_link_hash_table): Add bx_glue_size and bx_glue_offset.
	Update comment for fix_v4bx.
	(elf32_arm_link_hash_table_create): Zero bx_glue_size and
	bx_glue_offset.
	(ARM_BX_VENEER_SIZE, armbx1_tst_insn, armbx2_moveq_insn,
	armbx3_bx_insn): New.
	(bfd_elf32_arm_allocate_interworking_sections): Allocate BX veneer
	section.
	(bfd_elf32_arm_add_glue_sections_to_bfd): Ditto.
	(bfd_elf32_arm_process_before_allocation): Record BX veneers.
	(record_arm_bx_glue, elf32_arm_bx_glue): New functions.
	(elf32_arm_final_link_relocate): Handle BX veneers.
	(elf32_arm_output_arch_local_syms): Output mapping symbol for .v4_bx.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.

8 files changed, 266 insertions, 5 deletions

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 412db5f..4d8eb42 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -143,6 +143,7 @@ static int atpcs	     = FALSE;
 static int support_interwork = FALSE;
 static int uses_apcs_float   = FALSE;
 static int pic_code	     = FALSE;
+static int fix_v4bx	     = FALSE;
 
 /* Variables that we set while parsing command-line options.  Once all
    options have been read we re-process these values to set the real
@@ -6760,10 +6761,23 @@ do_blx (void)
 static void
 do_bx (void)
 {
+  bfd_boolean want_reloc;
+
   if (inst.operands[0].reg == REG_PC)
     as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
 
   inst.instruction |= inst.operands[0].reg;
+  /* Output R_ARM_V4BX relocations if is an EABI object that looks like
+     it is for ARMv4t or earlier.  */
+  want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
+  if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
+      want_reloc = TRUE;
+
+  if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
+    want_reloc = FALSE;
+
+  if (want_reloc)
+    inst.reloc.type = BFD_RELOC_ARM_V4BX;
 }
 
 
@@ -14272,9 +14286,15 @@ md_assemble (char *str)
     }
   else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
     {
+      bfd_boolean is_bx;
+
+      /* bx is allowed on v5 cores, and sometimes on v4 cores.  */
+      is_bx = (opcode->aencode == do_bx);
+
       /* Check that this instruction is supported for this CPU.  */
-      if (!opcode->avariant ||
-	  !ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant))
+      if (!(is_bx && fix_v4bx)
+	  && !(opcode->avariant &&
+	       ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
 	{
 	  as_bad (_("selected processor does not support `%s'"), str);
 	  return;
@@ -14296,8 +14316,7 @@ md_assemble (char *str)
 	opcode->aencode ();
       /* Arm mode bx is marked as both v4T and v5 because it's still required
          on a hypothetical non-thumb v5 core.  */
-      if (ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v4t)
-	  || ARM_CPU_HAS_FEATURE (*opcode->avariant, arm_ext_v5))
+      if (is_bx)
 	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
       else
 	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
@@ -18969,6 +18988,11 @@ md_apply_fix (fixS *	fixP,
         }
       break;
 
+    case BFD_RELOC_ARM_V4BX:
+      /* This will need to go in the object file.  */
+      fixP->fx_done = 0;
+      break;
+
     case BFD_RELOC_UNUSED:
     default:
       as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -19119,6 +19143,7 @@ tc_gen_reloc (asection *section, fixS *fixp)
     case BFD_RELOC_ARM_LDC_SB_G0:
     case BFD_RELOC_ARM_LDC_SB_G1:
     case BFD_RELOC_ARM_LDC_SB_G2:
+    case BFD_RELOC_ARM_V4BX:
       code = fixp->fx_r_type;
       break;
 
@@ -19806,6 +19831,7 @@ const char * md_shortopts = "m:k";
 #define OPTION_EL (OPTION_MD_BASE + 1)
 #endif
 #endif
+#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
 
 struct option md_longopts[] =
 {
@@ -19815,6 +19841,7 @@ struct option md_longopts[] =
 #ifdef OPTION_EL
   {"EL", no_argument, NULL, OPTION_EL},
 #endif
+  {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
   {NULL, no_argument, NULL, 0}
 };
 
@@ -20430,6 +20457,10 @@ md_parse_option (int c, char * arg)
       break;
 #endif
 
+    case OPTION_FIX_V4BX:
+      fix_v4bx = TRUE;
+      break;
+
     case 'a':
       /* Listing option.  Just ignore these, we don't support additional
 	 ones.	*/
@@ -20527,6 +20558,9 @@ md_show_usage (FILE * fp)
   fprintf (fp, _("\
   -EL                     assemble code for a little-endian cpu\n"));
 #endif
+
+  fprintf (fp, _("\
+  --fix-v4bx              Allow BX in ARMv4 code\n"));
 }
 
 
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi
index 404c8ef..ef5dcc0 100644
--- a/gas/doc/c-arm.texi
+++ b/gas/doc/c-arm.texi
@@ -276,6 +276,11 @@ be marked as being encoded for a little-endian processor.
 This option specifies that the output of the assembler should be marked
 as position-independent code (PIC).
 
+@cindex @code{--fix-v4bx} command line option, ARM
+@item --fix-v4bx
+Allow @code{BX} instructions in ARMv4 code.  This is intended for use with
+the linker option of the same name.
+
 @end table
 
 
diff --git a/gas/testsuite/gas/arm/arch4t-eabi.d b/gas/testsuite/gas/arm/arch4t-eabi.d
new file mode 100644
index 0000000..dfab64d
--- /dev/null
+++ b/gas/testsuite/gas/arm/arch4t-eabi.d
@@ -0,0 +1,40 @@
+# name: ARM architecture 4t instructions (EABI)
+# as: -march=armv4t
+# objdump: -dr --prefix-addresses --show-raw-insn
+# source: arch4t.s
+# target: *-*-*eabi *-*-symbianelf
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e12fff10 ?	bx	r0
+.*: R_ARM_V4BX.*
+0+04 <[^>]+> 012fff11 ?	bxeq	r1
+.*: R_ARM_V4BX.*
+0+08 <[^>]+> e15f30b8 ?	ldrh	r3, \[pc, #-8\]	; 0+08 <[^>]+>
+0+0c <[^>]+> e1d540f0 ?	ldrsh	r4, \[r5\]
+0+10 <[^>]+> e19140d3 ?	ldrsb	r4, \[r1, r3\]
+0+14 <[^>]+> e1b410f4 ?	ldrsh	r1, \[r4, r4\]!
+0+18 <[^>]+> 011510d3 ?	ldrsbeq	r1, \[r5, -r3\]
+0+1c <[^>]+> 109620b7 ?	ldrhne	r2, \[r6\], r7
+0+20 <[^>]+> 309720f8 ?	ldrshcc	r2, \[r7\], r8
+0+24 <[^>]+> e1d32fdf ?	ldrsb	r2, \[r3, #255\]
+0+28 <[^>]+> e1541ffa ?	ldrsh	r1, \[r4, #-250\]
+0+2c <[^>]+> e1d51fd0 ?	ldrsb	r1, \[r5, #240\]
+0+30 <[^>]+> e1cf23b0 ?	strh	r2, \[pc, #48\]	; 0+68 <[^>]+>
+0+34 <[^>]+> 11c330b0 ?	strhne	r3, \[r3\]
+0+38 <[^>]+> e328f002 ?	msr	CPSR_f, #2	; 0x2
+0+3c <[^>]+> e121f003 ?	msr	CPSR_c, r3
+0+40 <[^>]+> e122f004 ?	msr	CPSR_x, r4
+0+44 <[^>]+> e124f005 ?	msr	CPSR_s, r5
+0+48 <[^>]+> e128f006 ?	msr	CPSR_f, r6
+0+4c <[^>]+> e129f007 ?	msr	CPSR_fc, r7
+0+50 <[^>]+> e368f004 ?	msr	SPSR_f, #4	; 0x4
+0+54 <[^>]+> e161f008 ?	msr	SPSR_c, r8
+0+58 <[^>]+> e162f009 ?	msr	SPSR_x, r9
+0+5c <[^>]+> e164f00a ?	msr	SPSR_s, sl
+0+60 <[^>]+> e168f00b ?	msr	SPSR_f, fp
+0+64 <[^>]+> e169f00c ?	msr	SPSR_fc, ip
+0+68 <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+0+6c <[^>]+> e1a00000 ?	nop			\(mov r0,r0\)
+
diff --git a/gas/testsuite/gas/arm/arch4t.d b/gas/testsuite/gas/arm/arch4t.d
index f7e343f..4ec95f4 100644
--- a/gas/testsuite/gas/arm/arch4t.d
+++ b/gas/testsuite/gas/arm/arch4t.d
@@ -1,6 +1,8 @@
 # name: ARM architecture 4t instructions
 # as: -march=armv4t
 # objdump: -dr --prefix-addresses --show-raw-insn
+# EABI targets have their own variant.
+# not-target: *-*-*eabi *-*-symbianelf
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/thumb-eabi.d b/gas/testsuite/gas/arm/thumb-eabi.d
new file mode 100644
index 0000000..3c7b4ae
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb-eabi.d
@@ -0,0 +1,165 @@
+# name: Thumb instructions (EABI)
+# as: -mcpu=arm7t
+# objdump: -dr --prefix-addresses --show-raw-insn
+# source: thumb.s
+# target: *-*-*eabi *-*-symbianelf
+
+.*: +file format .*arm.*
+
+Disassembly of section \.text:
+0+000 <[^>]+> 00ca      	lsls	r2, r1, #3
+0+002 <[^>]+> 0fe3      	lsrs	r3, r4, #31
+0+004 <[^>]+> 1147      	asrs	r7, r0, #5
+0+006 <[^>]+> 0011      	lsls	r1, r2, #0
+0+008 <[^>]+> 0023      	lsls	r3, r4, #0
+0+00a <[^>]+> 002c      	lsls	r4, r5, #0
+0+00c <[^>]+> 083e      	lsrs	r6, r7, #32
+0+00e <[^>]+> 1008      	asrs	r0, r1, #32
+0+010 <[^>]+> 18d1      	adds	r1, r2, r3
+0+012 <[^>]+> 1ca2      	adds	r2, r4, #2
+0+014 <[^>]+> 1beb      	subs	r3, r5, r7
+0+016 <[^>]+> 1fe2      	subs	r2, r4, #7
+0+018 <[^>]+> 24ff      	movs	r4, #255
+0+01a <[^>]+> 2bfa      	cmp	r3, #250
+0+01c <[^>]+> 367b      	adds	r6, #123
+0+01e <[^>]+> 3d80      	subs	r5, #128
+0+020 <[^>]+> 402b      	ands	r3, r5
+0+022 <[^>]+> 4074      	eors	r4, r6
+0+024 <[^>]+> 4081      	lsls	r1, r0
+0+026 <[^>]+> 40da      	lsrs	r2, r3
+0+028 <[^>]+> 4134      	asrs	r4, r6
+0+02a <[^>]+> 417d      	adcs	r5, r7
+0+02c <[^>]+> 41a0      	sbcs	r0, r4
+0+02e <[^>]+> 41e1      	rors	r1, r4
+0+030 <[^>]+> 422a      	tst	r2, r5
+0+032 <[^>]+> 4249      	negs	r1, r1
+0+034 <[^>]+> 429a      	cmp	r2, r3
+0+036 <[^>]+> 42e1      	cmn	r1, r4
+0+038 <[^>]+> 4318      	orrs	r0, r3
+0+03a <[^>]+> 436c      	muls	r4, r5
+0+03c <[^>]+> 43bd      	bics	r5, r7
+0+03e <[^>]+> 43ed      	mvns	r5, r5
+0+040 <[^>]+> 4469      	add	r1, sp
+0+042 <[^>]+> 4494      	add	ip, r2
+0+044 <[^>]+> 44c9      	add	r9, r9
+0+046 <[^>]+> 4571      	cmp	r1, lr
+0+048 <[^>]+> 4580      	cmp	r8, r0
+0+04a <[^>]+> 45f4      	cmp	ip, lr
+0+04c <[^>]+> 4648      	mov	r0, r9
+0+04e <[^>]+> 46a1      	mov	r9, r4
+0+050 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+052 <[^>]+> 4738      	bx	r7
+0+054 <[^>]+> 4740      	bx	r8
+0+056 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+058 <[^>]+> 4778      	bx	pc
+0+05a <[^>]+> 4b20      	ldr	r3, \[pc, #128\]	\(0+0dc <[^>]+>\)
+0+05c <[^>]+> 4c02      	ldr	r4, \[pc, #8\]	\(0+068 <[^>]+>\)
+0+05e <[^>]+> 5088      	str	r0, \[r1, r2\]
+0+060 <[^>]+> 5511      	strb	r1, \[r2, r4\]
+0+062 <[^>]+> 59f5      	ldr	r5, \[r6, r7\]
+0+064 <[^>]+> 5d62      	ldrb	r2, \[r4, r5\]
+0+066 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+068 <[^>]+> 52d1      	strh	r1, \[r2, r3\]
+0+06a <[^>]+> 5a23      	ldrh	r3, \[r4, r0\]
+0+06c <[^>]+> 57f1      	ldrsb	r1, \[r6, r7\]
+0+06e <[^>]+> 5f42      	ldrsh	r2, \[r0, r5\]
+0+070 <[^>]+> 67db      	str	r3, \[r3, #124\]
+0+072 <[^>]+> 6fe1      	ldr	r1, \[r4, #124\]
+0+074 <[^>]+> 682d      	ldr	r5, \[r5, #0\]
+0+076 <[^>]+> 77e9      	strb	r1, \[r5, #31\]
+0+078 <[^>]+> 7161      	strb	r1, \[r4, #5\]
+0+07a <[^>]+> 7032      	strb	r2, \[r6, #0\]
+0+07c <[^>]+> 87ec      	strh	r4, \[r5, #62\]
+0+07e <[^>]+> 8885      	ldrh	r5, \[r0, #4\]
+0+080 <[^>]+> 8813      	ldrh	r3, \[r2, #0\]
+0+082 <[^>]+> 93ff      	str	r3, \[sp, #1020\]
+0+084 <[^>]+> 990b      	ldr	r1, \[sp, #44\]
+0+086 <[^>]+> 9a00      	ldr	r2, \[sp, #0\]
+0+088 <[^>]+> a7ff      	add	r7, pc, #1020	\(adr r7, 0+488 <[^>]+>\)
+0+08a <[^>]+> ac80      	add	r4, sp, #512
+0+08c <[^>]+> b043      	add	sp, #268
+0+08e <[^>]+> b09a      	sub	sp, #104
+0+090 <[^>]+> b0c3      	sub	sp, #268
+0+092 <[^>]+> b01b      	add	sp, #108
+0+094 <[^>]+> b417      	push	{r0, r1, r2, r4}
+0+096 <[^>]+> b5f9      	push	{r0, r3, r4, r5, r6, r7, lr}
+0+098 <[^>]+> bc98      	pop	{r3, r4, r7}
+0+09a <[^>]+> bdff      	pop	{r0, r1, r2, r3, r4, r5, r6, r7, pc}
+0+09c <[^>]+> c3f3      	stmia	r3!, {r0, r1, r4, r5, r6, r7}
+0+09e <[^>]+> c8fe      	ldmia	r0!, {r1, r2, r3, r4, r5, r6, r7}
+0+0a0 <[^>]+> d0e2      	beq.n	0+068 <[^>]+>
+0+0a2 <[^>]+> d1e1      	bne.n	0+068 <[^>]+>
+0+0a4 <[^>]+> d2e0      	bcs.n	0+068 <[^>]+>
+0+0a6 <[^>]+> d3df      	bcc.n	0+068 <[^>]+>
+0+0a8 <[^>]+> d4de      	bmi.n	0+068 <[^>]+>
+0+0aa <[^>]+> d5dd      	bpl.n	0+068 <[^>]+>
+0+0ac <[^>]+> d6dc      	bvs.n	0+068 <[^>]+>
+0+0ae <[^>]+> d7db      	bvc.n	0+068 <[^>]+>
+0+0b0 <[^>]+> d8da      	bhi.n	0+068 <[^>]+>
+0+0b2 <[^>]+> d9d9      	bls.n	0+068 <[^>]+>
+0+0b4 <[^>]+> dad8      	bge.n	0+068 <[^>]+>
+0+0b6 <[^>]+> dcd7      	bgt.n	0+068 <[^>]+>
+0+0b8 <[^>]+> dbd6      	blt.n	0+068 <[^>]+>
+0+0ba <[^>]+> dcd5      	bgt.n	0+068 <[^>]+>
+0+0bc <[^>]+> ddd4      	ble.n	0+068 <[^>]+>
+0+0be <[^>]+> d8d3      	bhi.n	0+068 <[^>]+>
+0+0c0 <[^>]+> d3d2      	bcc.n	0+068 <[^>]+>
+0+0c2 <[^>]+> d3d1      	bcc.n	0+068 <[^>]+>
+0+0c4 <[^>]+> e7d0      	b.n	0+068 <[^>]+>
+0+0c6 <[^>]+> 00ac      	lsls	r4, r5, #2
+0+0c8 <[^>]+> 1c9a      	adds	r2, r3, #2
+0+0ca <[^>]+> b07f      	add	sp, #508
+0+0cc <[^>]+> b0ff      	sub	sp, #508
+0+0ce <[^>]+> a8ff      	add	r0, sp, #1020
+0+0d0 <[^>]+> a0ff      	add	r0, pc, #1020	\(adr r0, 0+4d0 <[^>]+>\)
+0+0d2 <[^>]+> b01a      	add	sp, #104
+0+0d4 <[^>]+> b09a      	sub	sp, #104
+0+0d6 <[^>]+> a81a      	add	r0, sp, #104
+0+0d8 <[^>]+> a01a      	add	r0, pc, #104	\(adr r0, 0+144 <[^>]+>\)
+0+0da <[^>]+> 3168      	adds	r1, #104
+0+0dc <[^>]+> 2668      	movs	r6, #104
+0+0de <[^>]+> 2f68      	cmp	r7, #104
+0+0e0 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+0e2 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+0e4 <[^>]+> eafffffe 	b	0+0e4 <[^>]+>
+0+0e8 <[^>]+> ea000011 	b	0+134 <[^>]+>
+0+0ec <[^>]+> ebfffffc 	bl	0+0e4 <[^>]+>
+0+0f0 <[^>]+> eb00000f 	bl	0+134 <[^>]+>
+0+0f4 <[^>]+> e12fff10 	bx	r0
+.*: R_ARM_V4BX.*
+0+0f8 <[^>]+> ef123456 	(swi|svc)	0x00123456
+0+0fc <[^>]+> a004      	add	r0, pc, #16	\(adr r0, 0+110 <[^>]+>\)
+0+0fe <[^>]+> e77f      	b.n	0+000 <[^>]+>
+0+100 <[^>]+> e018      	b.n	0+134 <[^>]+>
+0+102 <[^>]+> f7ff ff7d 	bl	0+000 <[^>]+>
+0+106 <[^>]+> f000 f815 	bl	0+134 <[^>]+>
+0+10a <[^>]+> 4700      	bx	r0
+0+10c <[^>]+> dfff      	(swi|svc)	255
+0+10e <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+110 <[^>]+> d010      	beq.n	0+134 <[^>]+>
+0+112 <[^>]+> d10f      	bne.n	0+134 <[^>]+>
+0+114 <[^>]+> d20e      	bcs.n	0+134 <[^>]+>
+0+116 <[^>]+> d30d      	bcc.n	0+134 <[^>]+>
+0+118 <[^>]+> d40c      	bmi.n	0+134 <[^>]+>
+0+11a <[^>]+> d50b      	bpl.n	0+134 <[^>]+>
+0+11c <[^>]+> d60a      	bvs.n	0+134 <[^>]+>
+0+11e <[^>]+> d709      	bvc.n	0+134 <[^>]+>
+0+120 <[^>]+> d808      	bhi.n	0+134 <[^>]+>
+0+122 <[^>]+> d907      	bls.n	0+134 <[^>]+>
+0+124 <[^>]+> da06      	bge.n	0+134 <[^>]+>
+0+126 <[^>]+> dc05      	bgt.n	0+134 <[^>]+>
+0+128 <[^>]+> db04      	blt.n	0+134 <[^>]+>
+0+12a <[^>]+> dc03      	bgt.n	0+134 <[^>]+>
+0+12c <[^>]+> dd02      	ble.n	0+134 <[^>]+>
+0+12e <[^>]+> d801      	bhi.n	0+134 <[^>]+>
+0+130 <[^>]+> d300      	bcc.n	0+134 <[^>]+>
+0+132 <[^>]+> d3ff      	bcc.n	0+134 <[^>]+>
+0+134 <[^>]+> f000 fc00 	bl	0+938 <[^>]+>
+	\.\.\.
+0+938 <[^>]+> f7ff fbfc 	bl	0+134 <[^>]+>
+0+93c <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+944 <[^>]+>\)
+0+93e <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+944 <[^>]+>\)
+0+940 <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+948 <[^>]+>\)
+0+942 <[^>]+> 4801      	ldr	r0, \[pc, #4\]	\(0+948 <[^>]+>\)
+0+944 <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0+946 <[^>]+> 46c0      	nop			\(mov r8, r8\)
diff --git a/gas/testsuite/gas/arm/thumb.d b/gas/testsuite/gas/arm/thumb.d
index 7f9b253..1d3ac9f 100644
--- a/gas/testsuite/gas/arm/thumb.d
+++ b/gas/testsuite/gas/arm/thumb.d
@@ -2,7 +2,8 @@
 # as: -mcpu=arm7t
 # objdump: -dr --prefix-addresses --show-raw-insn
 # The arm-aout and arm-pe ports do not support Thumb branch relocations.
-# not-target: *-*-*aout* *-*-pe
+# EABI targets have their own variant.
+# not-target: *-*-*aout* *-*-pe *-*-*eabi *-*-symbianelf
 
 .*: +file format .*arm.*
 
diff --git a/gas/testsuite/gas/arm/v4bx.d b/gas/testsuite/gas/arm/v4bx.d
new file mode 100644
index 0000000..d37c25b
--- /dev/null
+++ b/gas/testsuite/gas/arm/v4bx.d
@@ -0,0 +1,10 @@
+# objdump: -dr --prefix-addresses --show-raw-insn
+# as: -meabi=4 --fix-v4bx
+# This test is only valid on ELF based ports.
+#not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix*
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+00 <[^>]+> e12fff1e 	bx	lr
+			0: R_ARM_V4BX	\*ABS\*
diff --git a/gas/testsuite/gas/arm/v4bx.s b/gas/testsuite/gas/arm/v4bx.s
new file mode 100644
index 0000000..fecedcc
--- /dev/null
+++ b/gas/testsuite/gas/arm/v4bx.s
@@ -0,0 +1,4 @@
+	.arch armv4
+	.text
+foo:	
+	bx	lr