diff options
| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-11-13 16:59:20 +0100 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2022-11-17 16:43:49 +0800 |
| commit | 4a3bc79bf4c0e89c876c930a1e95a02213277460 (patch) | |
| tree | 4a82c5fbaf454ec2fcf147c1134d67b2f38d5879 /gas | |
| parent | 7a4ce4a1bcff9710b7dede9797e6d5eb2364c06e (diff) | |
| download | gdb-4a3bc79bf4c0e89c876c930a1e95a02213277460.zip gdb-4a3bc79bf4c0e89c876c930a1e95a02213277460.tar.gz gdb-4a3bc79bf4c0e89c876c930a1e95a02213277460.tar.bz2 | |
RISC-V: Add T-Head Fmv vendor extension
This patch adds the XTheadFmv extension, which allows to access the
upper 32 bits of a double-precision floating-point register in RV32.
The XTheadFmv extension is documented in the RISC-V toolchain
contentions:
https://github.com/riscv-non-isa/riscv-toolchain-conventions
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/NEWS | 6 | ||||
| -rw-r--r-- | gas/doc/c-riscv.texi | 5 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-fmv.d | 11 | ||||
| -rw-r--r-- | gas/testsuite/gas/riscv/x-thead-fmv.s | 3 |
4 files changed, 22 insertions, 3 deletions
@@ -26,9 +26,9 @@ for --enable-compressed-debug-sections. * Add support for various T-Head extensions (XTheadBa, XTheadBb, XTheadBs, - XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadMemIdx, XTheadMemPair, - XTheadMac, and XTheadSync) from version 2.0 of the T-Head ISA manual, which - are implemented in the Allwinner D1. + XTheadCmo, XTheadCondMov, XTheadFMemIdx, XTheadFmv, XTheadMemIdx, + XTheadMemPair, XTheadMac, and XTheadSync) from version 2.0 of the T-Head + ISA manual, which are implemented in the Allwinner D1. * Add support for the RISC-V Zawrs extension, version 1.0-rc4. diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi index cc63760..f2a69d8 100644 --- a/gas/doc/c-riscv.texi +++ b/gas/doc/c-riscv.texi @@ -734,6 +734,11 @@ The XTheadFMemIdx extension provides floating-point memory operations. It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf}. +@item XTheadFmv +The XTheadFmv extension provides access to the upper 32 bits of a doulbe-precision floating point register. + +It is documented in @url{https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.1.0/xthead-2022-11-07-2.1.0.pdf}. + @item XTheadMac The XTheadMac extension provides multiply-accumulate instructions. diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.d b/gas/testsuite/gas/riscv/x-thead-fmv.d new file mode 100644 index 0000000..f2bbe01 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmv.d @@ -0,0 +1,11 @@ +#as: -march=rv32i_xtheadfmv +#source: x-thead-fmv.s +#objdump: -dr + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 <target>: +[ ]+[0-9a-f]+:[ ]+6005950b[ ]+th.fmv.hw.x[ ]+a0,fa1 +[ ]+[0-9a-f]+:[ ]+5005158b[ ]+th.fmv.x.hw[ ]+a1,fa0 diff --git a/gas/testsuite/gas/riscv/x-thead-fmv.s b/gas/testsuite/gas/riscv/x-thead-fmv.s new file mode 100644 index 0000000..250ba83 --- /dev/null +++ b/gas/testsuite/gas/riscv/x-thead-fmv.s @@ -0,0 +1,3 @@ +target: + th.fmv.hw.x a0, fa1 + th.fmv.x.hw a1, fa0 |