[MIPS] Rename COPROC related macros

gas/

	* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
	and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.

include/opcode/

	* mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
	(INSN_LOAD_COPROC): New define.
	(INSN_COPROC_MOVE_DELAY): Rename to...
	(INSN_COPROC_MOVE): New define.

opcodes/

	* micromips-opc.c (COD): Rename throughout to...
	(CM): New define, update to use INSN_COPROC_MOVE.
	(LCD): Rename throughout to...
	(LC): New define, update to use INSN_LOAD_COPROC.
	* mips-opc.c: Likewise.

2 files changed, 13 insertions, 8 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 487b0c7..72d54db 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
 2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
 
+	* config/tc-mips.c: Rename INSN_LOAD_COPROC_DELAY to INSN_LOAD_COPROC
+	and INSN_COPROC_MOVE_DELAY to INSN_COPROC_MOVE throughout.
+
+2014-07-29  Matthew Fortune  <matthew.fortune@imgtec.com>
+
 	* config/tc-mips.c (mips_flags_frag): New static global.
 	(struct mips_set_options): Add oddspreg field.
 	(file_mips_opts, mips_opts): Initialize oddspreg.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 2340afc..03f2b13 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -533,8 +533,8 @@ static int mips_32bitmode = 0;
 /* Whether the processor uses hardware interlocks to avoid delays
    required by coprocessor instructions, and thus does not require
    nops to be inserted.  This applies to instructions marked
-   INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
-   between instructions marked INSN_WRITE_COND_CODE and ones marked
+   INSN_LOAD_COPROC, INSN_COPROC_MOVE, and to delays between
+   instructions marked INSN_WRITE_COND_CODE and ones marked
    INSN_READ_COND_CODE.  These nops are only required at MIPS ISA
    levels I, II, and III and microMIPS mode instructions are always
    interlocked.  */
@@ -4509,7 +4509,7 @@ mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum)
      otherwise it depends on oddspreg.  */
   if ((insn->pinfo & FP_S)
       && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY
-			 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
+			 | INSN_LOAD_COPROC | INSN_COPROC_MOVE)))
     return FPR_SIZE == 32 || oddspreg;
 
   /* Allow odd registers for single-precision ops and double-precision if the
@@ -4688,9 +4688,9 @@ convert_reg_type (const struct mips_opcode *opcode,
 	 FPR load, store or move (including moves to and from GPRs).  */
       if ((mips_opts.ase & ASE_MDMX)
 	  && (opcode->pinfo & FP_D)
-	  && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
+	  && (opcode->pinfo & (INSN_COPROC_MOVE
 			       | INSN_COPROC_MEMORY_DELAY
-			       | INSN_LOAD_COPROC_DELAY
+			       | INSN_LOAD_COPROC
 			       | INSN_LOAD_MEMORY
 			       | INSN_STORE_MEMORY)))
 	return RTYPE_FPU | RTYPE_VEC;
@@ -5842,7 +5842,7 @@ reg_needs_delay (unsigned int reg)
   prev_pinfo = history[0].insn_mo->pinfo;
   if (!mips_opts.noreorder
       && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
-	  || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
+	  || ((prev_pinfo & INSN_LOAD_COPROC) && !cop_interlocks))
       && (gpr_write_mask (&history[0]) & (1 << reg)))
     return TRUE;
 
@@ -5960,7 +5960,7 @@ insns_between (const struct mips_cl_insn *insn1,
 	 are on the RT register.  */
       /* Itbl support may require additional care here.  */
       if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
-	  || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
+	  || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC)))
 	{
 	  if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))
 	    return 1;
@@ -5974,7 +5974,7 @@ insns_between (const struct mips_cl_insn *insn1,
       /* Itbl support may require additional care here. FIXME!
 	 Need to modify this to include knowledge about
 	 user specified delays!  */
-      else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
+      else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE))
 	       || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
 	{
 	  /* Handle cases where INSN1 writes to a known general coprocessor