Add support to the ARC disassembler for selecting instruction classes.

gas	* testsuite/gas/arc/dsp.d: New file.
	* testsuite/gas/arc/dsp.s: Likewise.
	* testsuite/gas/arc/fpu.d: Likewise.
	* testsuite/gas/arc/fpu.s: Likewise.
	* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
	* testsuite/gas/arc/ext3op.d: Likewise.
	* testsuite/gas/arc/tdpfp.d: Likewise.
	* testsuite/gas/arc/tfpuda.d: Likewise.

opcodes	* arc-dis.c (skipclass): New structure.
	(decodelist): New variable.
	(is_compatible_p): New function.
	(new_element): Likewise.
	(skip_class_p): Likewise.
	(find_format_from_table): Use skip_class_p function.
	(find_format): Decode first the extension instructions.
	(print_insn_arc): Select either ARCEM or ARCHS based on elf
	e_flags.
	(parse_option): New function.
	(parse_disassembler_options): Likewise.
	(print_arc_disassembler_options): Likewise.
	(print_insn_arc): Use parse_disassembler_options function.  Proper
	select ARCv2 cpu variant.
	* disassemble.c (disassembler_usage): Add ARC disassembler
	options.

binutils* doc/binutils.texi (objdump): Add ARC disassembler options.
	* testsuite/binutils-all/arc/dsp.s: New file.
	* testsuite/binutils-all/arc/objdump.exp: Likewise.

include	* dis-asm.h: Declare print_arc_disassembler_options.

9 files changed, 254 insertions, 4 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index b3872ce..f0e5784 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,14 @@
+2016-07-20  Claudiu Zissulescu  <claziss@synopsys.com>
+
+	* testsuite/gas/arc/dsp.d: New file.
+	* testsuite/gas/arc/dsp.s: Likewise.
+	* testsuite/gas/arc/fpu.d: Likewise.
+	* testsuite/gas/arc/fpu.s: Likewise.
+	* testsuite/gas/arc/ext2op.d: Add specific disassembler option.
+	* testsuite/gas/arc/ext3op.d: Likewise.
+	* testsuite/gas/arc/tdpfp.d: Likewise.
+	* testsuite/gas/arc/tfpuda.d: Likewise.
+
 2016-07-20  Maciej W. Rozycki  <macro@imgtec.com>
 
 	* config/tc-mips.c (mips_force_relocation): Remove
diff --git a/gas/testsuite/gas/arc/dsp.d b/gas/testsuite/gas/arc/dsp.d
new file mode 100644
index 0000000..22961ae
--- /dev/null
+++ b/gas/testsuite/gas/arc/dsp.d
@@ -0,0 +1,96 @@
+#as: -mcpu=arcem
+#objdump: -dr --prefix-addresses --show-raw-insn -M dsp
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+0x[0-9a-f]+ 3211 0100           	vmac2hnfr	r0,r2,r4
+0x[0-9a-f]+ 282f 0084           	abssh	r0,r2
+0x[0-9a-f]+ 282f 003f           	aslacc	r0
+0x[0-9a-f]+ 292f 003f           	aslsacc	r0
+0x[0-9a-f]+ 2a0c 0100           	asrsr	r0,r2,r4
+0x[0-9a-f]+ 321b 8100           	cbflyhf0r	r0,r2,r4
+0x[0-9a-f]+ 302f 00b9           	cbflyhf1r	r0,r2
+0x[0-9a-f]+ 3209 8100           	cmacchfr	r0,r2,r4
+0x[0-9a-f]+ 3208 8100           	cmacchnfr	r0,r2,r4
+0x[0-9a-f]+ 3207 8100           	cmachfr	r0,r2,r4
+0x[0-9a-f]+ 3206 8100           	cmachnfr	r0,r2,r4
+0x[0-9a-f]+ 3205 8100           	cmpychfr	r0,r2,r4
+0x[0-9a-f]+ 3202 8100           	cmpychnfr	r0,r2,r4
+0x[0-9a-f]+ 321b 0100           	cmpyhfmr	r0,r2,r4
+0x[0-9a-f]+ 3201 8100           	cmpyhfr	r0,r2,r4
+0x[0-9a-f]+ 3200 8100           	cmpyhnfr	r0,r2,r4
+0x[0-9a-f]+ 2b2f 003f           	divacc	r0
+0x[0-9a-f]+ 3218 0100           	dmachbl	r0,r2,r4
+0x[0-9a-f]+ 3219 0100           	dmachbm	r0,r2,r4
+0x[0-9a-f]+ 2a2c 0100           	dmachf	r0,r2,r4
+0x[0-9a-f]+ 2a2d 0100           	dmachfr	r0,r2,r4
+0x[0-9a-f]+ 3216 0100           	dmpyhbl	r0,r2,r4
+0x[0-9a-f]+ 3217 0100           	dmpyhbm	r0,r2,r4
+0x[0-9a-f]+ 2a2a 0100           	dmpyhf	r0,r2,r4
+0x[0-9a-f]+ 2a2b 0100           	dmpyhfr	r0,r2,r4
+0x[0-9a-f]+ 2a28 0100           	dmpyhwf	r0,r2,r4
+0x[0-9a-f]+ 2c2f 803f           	flagacc	r0
+0x[0-9a-f]+ 282f 0098           	getacc	r0,r2
+0x[0-9a-f]+ 320c 0100           	macf	r0,r2,r4
+0x[0-9a-f]+ 320d 0100           	macfr	r0,r2,r4
+0x[0-9a-f]+ 3222 0100           	macwhfm	r0,r2,r4
+0x[0-9a-f]+ 3223 0100           	macwhfmr	r0,r2,r4
+0x[0-9a-f]+ 321d 0100           	macwhl	r0,r2,r4
+0x[0-9a-f]+ 321f 0100           	macwhul	r0,r2,r4
+0x[0-9a-f]+ 320a 0100           	mpyf	r0,r2,r4
+0x[0-9a-f]+ 320b 0100           	mpyfr	r0,r2,r4
+0x[0-9a-f]+ 3224 0100           	mpywhfl	r0,r2,r4
+0x[0-9a-f]+ 3225 0100           	mpywhflr	r0,r2,r4
+0x[0-9a-f]+ 3220 0100           	mpywhfm	r0,r2,r4
+0x[0-9a-f]+ 3221 0100           	mpywhfmr	r0,r2,r4
+0x[0-9a-f]+ 321c 0100           	mpywhl	r0,r2,r4
+0x[0-9a-f]+ 321e 0100           	mpywhul	r0,r2,r4
+0x[0-9a-f]+ 3215 0100           	msubdf	r0,r2,r4
+0x[0-9a-f]+ 320e 0100           	msubf	r0,r2,r4
+0x[0-9a-f]+ 320f 0100           	msubfr	r0,r2,r4
+0x[0-9a-f]+ 282f 0086           	negsh	r0,r2
+0x[0-9a-f]+ 282f 0099           	normacc	r0,r2
+0x[0-9a-f]+ 282f 0083           	rndh	r0,r2
+0x[0-9a-f]+ 282f 0082           	sath	r0,r2
+0x[0-9a-f]+ 2a0d 8100           	setacc	r0,r2,r4
+0x[0-9a-f]+ 2a2f 003f           	sqrtacc	r0
+0x[0-9a-f]+ 282f 00a8           	vabs2h	r0,r2
+0x[0-9a-f]+ 282f 00a9           	vabss2h	r0,r2
+0x[0-9a-f]+ 2a24 0100           	vadd4b	r0,r2,r4
+0x[0-9a-f]+ 2a14 8100           	vadds2h	r0,r2,r4
+0x[0-9a-f]+ 2a16 8100           	vaddsubs2h	r0,r2,r4
+0x[0-9a-f]+ 2a0d 0100           	valgn2h	r0,r2,r4
+0x[0-9a-f]+ 2a21 0100           	vasl2h	r0,r2,r4
+0x[0-9a-f]+ 2a21 8100           	vasls2h	r0,r2,r4
+0x[0-9a-f]+ 2a22 0100           	vasr2h	r0,r2,r4
+0x[0-9a-f]+ 2a22 8100           	vasrs2h	r0,r2,r4
+0x[0-9a-f]+ 2a23 8100           	vasrsr2h	r0,r2,r4
+0x[0-9a-f]+ 282f 00a4           	vext2bhl	r0,r2
+0x[0-9a-f]+ 282f 00a5           	vext2bhm	r0,r2
+0x[0-9a-f]+ 2a23 0100           	vlsr2h	r0,r2,r4
+0x[0-9a-f]+ 2a1e 0100           	vmac2h	r0,r2,r4
+0x[0-9a-f]+ 2a1e 8100           	vmac2hf	r0,r2,r4
+0x[0-9a-f]+ 2a1f 8100           	vmac2hfr	r0,r2,r4
+0x[0-9a-f]+ 2a1f 0100           	vmac2hu	r0,r2,r4
+0x[0-9a-f]+ 2a24 8100           	vmax2h	r0,r2,r4
+0x[0-9a-f]+ 2a25 8100           	vmin2h	r0,r2,r4
+0x[0-9a-f]+ 2a1c 0100           	vmpy2h	r0,r2,r4
+0x[0-9a-f]+ 2a1c 8100           	vmpy2hf	r0,r2,r4
+0x[0-9a-f]+ 2a1d 8100           	vmpy2hfr	r0,r2,r4
+0x[0-9a-f]+ 2a1d 0100           	vmpy2hu	r0,r2,r4
+0x[0-9a-f]+ 2a20 0100           	vmpy2hwf	r0,r2,r4
+0x[0-9a-f]+ 3204 0100           	vmsub2hf	r0,r2,r4
+0x[0-9a-f]+ 3203 0100           	vmsub2hfr	r0,r2,r4
+0x[0-9a-f]+ 3211 8100           	vmsub2hnfr	r0,r2,r4
+0x[0-9a-f]+ 282f 00aa           	vneg2h	r0,r2
+0x[0-9a-f]+ 282f 00ab           	vnegs2h	r0,r2
+0x[0-9a-f]+ 282f 00ac           	vnorm2h	r0,r2
+0x[0-9a-f]+ 282f 00a2           	vrep2hl	r0,r2
+0x[0-9a-f]+ 282f 00a3           	vrep2hm	r0,r2
+0x[0-9a-f]+ 282f 00a6           	vsext2bhl	r0,r2
+0x[0-9a-f]+ 282f 00a7           	vsext2bhm	r0,r2
+0x[0-9a-f]+ 2a25 0100           	vsub4b	r0,r2,r4
+0x[0-9a-f]+ 2a17 8100           	vsubadds2h	r0,r2,r4
+0x[0-9a-f]+ 2a15 8100           	vsubs2h	r0,r2,r4
diff --git a/gas/testsuite/gas/arc/dsp.s b/gas/testsuite/gas/arc/dsp.s
new file mode 100644
index 0000000..2847af6
--- /dev/null
+++ b/gas/testsuite/gas/arc/dsp.s
@@ -0,0 +1,90 @@
+#Test if disassembler correctly prints DSP instructions.
+	vmac2hnfr	r0,r2,r4
+	abssh		r0,r2
+	aslacc		r0
+	aslsacc		r0
+	asrsr		r0,r2,r4
+	cbflyhf0r	r0,r2,r4
+	cbflyhf1r	r0,r2
+	cmacchfr	r0,r2,r4
+	cmacchnfr	r0,r2,r4
+	cmachfr		r0,r2,r4
+	cmachnfr	r0,r2,r4
+	cmpychfr	r0,r2,r4
+	cmpychnfr	r0,r2,r4
+	cmpyhfmr	r0,r2,r4
+	cmpyhfr		r0,r2,r4
+	cmpyhnfr	r0,r2,r4
+	divacc		r0
+	dmachbl		r0,r2,r4
+	dmachbm		r0,r2,r4
+	dmachf		r0,r2,r4
+	dmachfr		r0,r2,r4
+	dmpyhbl		r0,r2,r4
+	dmpyhbm		r0,r2,r4
+	dmpyhf		r0,r2,r4
+	dmpyhfr		r0,r2,r4
+	dmpyhwf		r0,r2,r4
+	flagacc		r0
+	getacc		r0,r2
+	macf		r0,r2,r4
+	macfr		r0,r2,r4
+	macwhfm		r0,r2,r4
+	macwhfmr	r0,r2,r4
+	macwhl		r0,r2,r4
+	macwhul		r0,r2,r4
+	mpyf		r0,r2,r4
+	mpyfr		r0,r2,r4
+	mpywhfl		r0,r2,r4
+	mpywhflr	r0,r2,r4
+	mpywhfm		r0,r2,r4
+	mpywhfmr	r0,r2,r4
+	mpywhl		r0,r2,r4
+	mpywhul		r0,r2,r4
+	msubdf		r0,r2,r4
+	msubf		r0,r2,r4
+	msubfr		r0,r2,r4
+	negsh		r0,r2
+	normacc		r0,r2
+	rndh		r0,r2
+	sath		r0,r2
+	setacc		r0,r2,r4
+	sqrtacc		r0
+	vabs2h		r0,r2
+	vabss2h		r0,r2
+	vadd4b		r0,r2,r4
+	vadds2h		r0,r2,r4
+	vaddsubs2h	r0,r2,r4
+	valgn2h		r0,r2,r4
+	vasl2h		r0,r2,r4
+	vasls2h		r0,r2,r4
+	vasr2h		r0,r2,r4
+	vasrs2h		r0,r2,r4
+	vasrsr2h	r0,r2,r4
+	vext2bhl	r0,r2
+	vext2bhm	r0,r2
+	vlsr2h		r0,r2,r4
+	vmac2h		r0,r2,r4
+	vmac2hf		r0,r2,r4
+	vmac2hfr	r0,r2,r4
+	vmac2hu		r0,r2,r4
+	vmax2h		r0,r2,r4
+	vmin2h		r0,r2,r4
+	vmpy2h		r0,r2,r4
+	vmpy2hf		r0,r2,r4
+	vmpy2hfr	r0,r2,r4
+	vmpy2hu		r0,r2,r4
+	vmpy2hwf	r0,r2,r4
+	vmsub2hf	r0,r2,r4
+	vmsub2hfr	r0,r2,r4
+	vmsub2hnfr	r0,r2,r4
+	vneg2h		r0,r2
+	vnegs2h		r0,r2
+	vnorm2h		r0,r2
+	vrep2hl		r0,r2
+	vrep2hm		r0,r2
+	vsext2bhl	r0,r2
+	vsext2bhm	r0,r2
+	vsub4b		r0,r2,r4
+	vsubadds2h	r0,r2,r4
+	vsubs2h		r0,r2,r4
diff --git a/gas/testsuite/gas/arc/ext2op.d b/gas/testsuite/gas/arc/ext2op.d
index 144989e..00ef6ac 100644
--- a/gas/testsuite/gas/arc/ext2op.d
+++ b/gas/testsuite/gas/arc/ext2op.d
@@ -1,5 +1,5 @@
 #as: -mcpu=arcem
-#objdump: -dr
+#objdump: -dr -M quarkse_em
 
 .*: +file format .*arc.*
 
diff --git a/gas/testsuite/gas/arc/ext3op.d b/gas/testsuite/gas/arc/ext3op.d
index 926a13c..7a63f14 100644
--- a/gas/testsuite/gas/arc/ext3op.d
+++ b/gas/testsuite/gas/arc/ext3op.d
@@ -1,5 +1,5 @@
 #as: -mcpu=arcem
-#objdump: -dr
+#objdump: -dr -M quarkse_em
 
 .*: +file format .*arc.*
 
diff --git a/gas/testsuite/gas/arc/fpu.d b/gas/testsuite/gas/arc/fpu.d
new file mode 100644
index 0000000..ab805da
--- /dev/null
+++ b/gas/testsuite/gas/arc/fpu.d
@@ -0,0 +1,29 @@
+#as: -mcpu=archs
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arc.*
+
+
+Disassembly of section .text:
+0x[0-9a-f]+ 3208 0100           	fcvt32	r0,r2,r4
+0x[0-9a-f]+ 3209 0100           	fcvt32_64	r0,r2,r4
+0x[0-9a-f]+ 3238 0100           	fcvt64	r0,r2,r4
+0x[0-9a-f]+ 3239 0100           	fcvt64_32	r0,r2,r4
+0x[0-9a-f]+ 3231 0100           	fdadd	r0,r2,r4
+0x[0-9a-f]+ 3033 8080           	fdcmp	r0,r2
+0x[0-9a-f]+ 3034 8080           	fdcmpf	r0,r2
+0x[0-9a-f]+ 3237 0100           	fddiv	r0,r2,r4
+0x[0-9a-f]+ 3235 0100           	fdmadd	r0,r2,r4
+0x[0-9a-f]+ 3236 0100           	fdmsub	r0,r2,r4
+0x[0-9a-f]+ 3230 0100           	fdmul	r0,r2,r4
+0x[0-9a-f]+ 302f 0081           	fdsqrt	r0,r2
+0x[0-9a-f]+ 3232 0100           	fdsub	r0,r2,r4
+0x[0-9a-f]+ 3201 0100           	fsadd	r0,r2,r4
+0x[0-9a-f]+ 3003 8080           	fscmp	r0,r2
+0x[0-9a-f]+ 3004 8080           	fscmpf	r0,r2
+0x[0-9a-f]+ 3207 0100           	fsdiv	r0,r2,r4
+0x[0-9a-f]+ 3205 0100           	fsmadd	r0,r2,r4
+0x[0-9a-f]+ 3206 0100           	fsmsub	r0,r2,r4
+0x[0-9a-f]+ 3200 0100           	fsmul	r0,r2,r4
+0x[0-9a-f]+ 302f 0080           	fssqrt	r0,r2
+0x[0-9a-f]+ 3202 0100           	fssub	r0,r2,r4
diff --git a/gas/testsuite/gas/arc/fpu.s b/gas/testsuite/gas/arc/fpu.s
new file mode 100644
index 0000000..78c18bf
--- /dev/null
+++ b/gas/testsuite/gas/arc/fpu.s
@@ -0,0 +1,24 @@
+# Test if all fpu ops are correctly disassembled as they share the
+# same opcode space with FPX instructions.
+	fcvt32		r0,r2,r4
+	fcvt32_64	r0,r2,r4
+	fcvt64		r0,r2,r4
+	fcvt64_32	r0,r2,r4
+	fdadd		r0,r2,r4
+	fdcmp		r0,r2
+	fdcmpf		r0,r2
+	fddiv		r0,r2,r4
+	fdmadd		r0,r2,r4
+	fdmsub		r0,r2,r4
+	fdmul		r0,r2,r4
+	fdsqrt		r0,r2
+	fdsub		r0,r2,r4
+	fsadd		r0,r2,r4
+	fscmp		r0,r2
+	fscmpf		r0,r2
+	fsdiv		r0,r2,r4
+	fsmadd		r0,r2,r4
+	fsmsub		r0,r2,r4
+	fsmul		r0,r2,r4
+	fssqrt		r0,r2
+	fssub		r0,r2,r4
diff --git a/gas/testsuite/gas/arc/tdpfp.d b/gas/testsuite/gas/arc/tdpfp.d
index 6475ebc..a2edb0e 100644
--- a/gas/testsuite/gas/arc/tdpfp.d
+++ b/gas/testsuite/gas/arc/tdpfp.d
@@ -1,5 +1,5 @@
 #as:-mcpu=arcem -mdpfp
-#objdump: -dr
+#objdump: -dr -M dpfp
 #source: tfpx.s
 
 .*: +file format .*arc.*
diff --git a/gas/testsuite/gas/arc/tfpuda.d b/gas/testsuite/gas/arc/tfpuda.d
index a6645a5..640500e 100644
--- a/gas/testsuite/gas/arc/tfpuda.d
+++ b/gas/testsuite/gas/arc/tfpuda.d
@@ -1,5 +1,5 @@
 #as:-mcpu=arcem -mfpuda
-#objdump: -dr
+#objdump: -dr -M fpuda
 #source: tfpx.s
 
 .*: +file format .*arc.*