[AArch64] Support for ARMv8.1a Limited Ordering Regions extension

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
include/
  * aarch64.h (AARCH64_FEATURE_LOR): New.

opcodes/
  * aarch64-tbl.h (aarch64_feature_lor): New.
  (LOR): New.
  (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
  "stllrb", "stllrh".
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.

gas/
  * config/tc-aarch64.c (aarch64_features): Add "lor".
  * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
  architecture extensions.

gas/testsuite/
  * lor-directive.d: New.
  * lor.d: New.
  * lor.s: New.

7 files changed, 106 insertions, 0 deletions

diff --git a/gas/ChangeLog b/gas/ChangeLog
index dd2f446..2401a44 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+	* config/tc-aarch64.c (aarch64_features): Add "lor".
+	* doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
+	architecture extensions.
+
 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 
 	* config/tc-aarch64.c (parse_sys_reg): New parameter.  Check target
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 707936d..28fb41c 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -7400,6 +7400,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"lse",		AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0)},
   {"simd",		AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
   {"pan",		AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
+  {"lor",		AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
   {NULL,		AARCH64_ARCH_NONE}
 };
 
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index f790c7a..2b5689c 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -135,6 +135,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Advanced SIMD extensions.  This implies @code{fp}.
 @item @code{pan} @tab ARMv8-A @tab ARMv8-A or later
  @tab Enable Privileged Access Never support.
+@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
+ @tab Enable Limited Ordering Regions extensions.
 @end multitable
 
 @node AArch64 Syntax
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 233e138..6e2ea2d 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>
+
+	* lor-directive.d: New.
+	* lor.d: New.
+	* lor.s: New
+
 2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>
 
 	* pan-directive.d: New.
diff --git a/gas/testsuite/gas/aarch64/lor-directive.d b/gas/testsuite/gas/aarch64/lor-directive.d
new file mode 100644
index 0000000..3238bb9
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lor-directive.d
@@ -0,0 +1,25 @@
+#objdump: -dr
+#as: --defsym DIRECTIVE=1
+#source: lor.s
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.text>:
+   0:	889f7c00 	stllr	w0, \[x0\]
+   4:	c89f7c00 	stllr	x0, \[x0\]
+   8:	889f7c01 	stllr	w1, \[x0\]
+   c:	c89f7c22 	stllr	x2, \[x1\]
+  10:	489f7c43 	stllrh	w3, \[x2\]
+  14:	089f7c64 	stllrb	w4, \[x3\]
+  18:	089f7fe5 	stllrb	w5, \[sp\]
+  1c:	88df7c00 	ldlar	w0, \[x0\]
+  20:	c8df7c00 	ldlar	x0, \[x0\]
+  24:	88df7c01 	ldlar	w1, \[x0\]
+  28:	c8df7c22 	ldlar	x2, \[x1\]
+  2c:	08df7c43 	ldlarb	w3, \[x2\]
+  30:	48df7c64 	ldlarh	w4, \[x3\]
+  34:	88df7fe5 	ldlar	w5, \[sp\]
+
diff --git a/gas/testsuite/gas/aarch64/lor.d b/gas/testsuite/gas/aarch64/lor.d
new file mode 100644
index 0000000..006983b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lor.d
@@ -0,0 +1,23 @@
+#objdump: -dr
+#as: -march=armv8-a+lor
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+0000000000000000 <.text>:
+   0:	889f7c00 	stllr	w0, \[x0\]
+   4:	c89f7c00 	stllr	x0, \[x0\]
+   8:	889f7c01 	stllr	w1, \[x0\]
+   c:	c89f7c22 	stllr	x2, \[x1\]
+  10:	489f7c43 	stllrh	w3, \[x2\]
+  14:	089f7c64 	stllrb	w4, \[x3\]
+  18:	089f7fe5 	stllrb	w5, \[sp\]
+  1c:	88df7c00 	ldlar	w0, \[x0\]
+  20:	c8df7c00 	ldlar	x0, \[x0\]
+  24:	88df7c01 	ldlar	w1, \[x0\]
+  28:	c8df7c22 	ldlar	x2, \[x1\]
+  2c:	08df7c43 	ldlarb	w3, \[x2\]
+  30:	48df7c64 	ldlarh	w4, \[x3\]
+  34:	88df7fe5 	ldlar	w5, \[sp\]
diff --git a/gas/testsuite/gas/aarch64/lor.s b/gas/testsuite/gas/aarch64/lor.s
new file mode 100644
index 0000000..3d296ab
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lor.s
@@ -0,0 +1,43 @@
+/* lor.s Test file for AArch64 LOR extension instructions.
+
+   Copyright (C) 2015 Free Software Foundation, Inc.  Contributed by ARM Ltd.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the license, or
+   (at your option) any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; see the file COPYING3. If not,
+   see <http://www.gnu.org/licenses/>.  */
+
+	.text
+	.ifdef DIRECTIVE
+	.arch_extension lor
+	.endif
+
+        stllr w0, [x0]
+	stllr x0, [x0]
+	
+	stllr w1, [x0]
+	stllr x2, [x1]
+        stllrh w3, [x2]
+        stllrb w4, [x3]
+	stllrb w5, [sp]
+        
+        ldlar w0, [x0]
+	ldlar x0, [x0]
+
+        ldlar w1, [x0]
+	ldlar x2, [x1]
+        ldlarb w3, [x2]
+        ldlarh w4, [x3]
+        ldlar w5, [sp]  
+