x86/APX: extend SSE2AVX coverage

Legacy encoded SIMD insns are converted to AVX ones in that mode. When
eGPR-s are in use, i.e. with APX, convert to AVX10 insns (where
available; there are quite a few which can't be converted).

Note that LDDQU is represented as VMOVDQU32 (and the prior use of the
sse3 template there needs dropping, to get the order right).

Note further that in a few cases, due to the use of templates, AVX512VL
is used when AVX512F would suffice. Since AVX10 is the main reference,
this shouldn't be too much of a problem.

7 files changed, 613 insertions, 3 deletions

diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index b037468..13da7a6 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -4133,7 +4133,7 @@ build_evex_prefix (void)
   /* Check the REX.W bit and VEXW.  */
   if (i.tm.opcode_modifier.vexw == VEXWIG)
     w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
-  else if (i.tm.opcode_modifier.vexw)
+  else if (i.tm.opcode_modifier.vexw && !(i.rex & REX_W))
     w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
   else
     w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0;
@@ -8281,7 +8281,12 @@ check_VecOperands (const insn_template *t)
   if ((is_cpu (t, CpuXOP) && t->operands == 5)
       || (t->opcode_space == SPACE_0F3A
 	  && (t->base_opcode | 3) == 0x0b
-	  && is_cpu (t, CpuAPX_F)))
+	  && (is_cpu (t, CpuAPX_F)
+	   || (t->opcode_modifier.sse2avx && t->opcode_modifier.evex
+	       && (!t->opcode_modifier.vex
+		   || (i.encoding != encoding_default
+		       && i.encoding != encoding_vex
+		       && i.encoding != encoding_vex3))))))
     {
       if (i.op[0].imms->X_op != O_constant
 	  || !fits_in_imm4 (i.op[0].imms->X_add_number))
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 7254d56..36ba825 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -312,7 +312,9 @@ when respective checks fail.
 @cindex @samp{-msse2avx} option, x86-64
 @item -msse2avx
 This option specifies that the assembler should encode SSE instructions
-with VEX prefix.
+with VEX prefix, requiring AVX to be available.  SSE instructions using
+extended GPRs will be encoded with EVEX prefix, requiring AVX512 or AVX10 to
+be available.
 
 @cindex @samp{-muse-unaligned-vector-move} option, i386
 @cindex @samp{-muse-unaligned-vector-move} option, x86-64
diff --git a/gas/testsuite/gas/i386/sse2avx-apx.d b/gas/testsuite/gas/i386/sse2avx-apx.d
new file mode 100644
index 0000000..edc3117
--- /dev/null
+++ b/gas/testsuite/gas/i386/sse2avx-apx.d
@@ -0,0 +1,261 @@
+#as: -msse2avx
+#objdump: -dw
+#name: x86-64 SSE+ with APX encoding
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <sse2avx>:
+[ 	]*[a-f0-9]+:	62 f9 7c 08 5b 60 01 	vcvtdq2ps 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 ff 08 e6 60 01 	vcvtpd2dqx 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 5a 60 01 	vcvtpd2psx 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7d 08 5b 60 01 	vcvtps2dq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 e6 60 01 	vcvttpd2dqx 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 5b 60 01 	vcvttps2dq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 6f 60 01 	vmovdqu32 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 28 60 01 	vmovapd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7c 08 28 60 01 	vmovaps 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7d 08 6f 60 01 	vmovdqa32 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 6f 60 01 	vmovdqu32 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 2a 60 01 	vmovntdqa 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 16 60 01 	vmovshdup 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 12 60 01 	vmovsldup 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 10 60 01 	vmovupd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7c 08 10 60 01 	vmovups 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 1c 60 01 	vpabsb 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 1d 60 01 	vpabsw 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 1e 60 01 	vpabsd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 4c 60 01 	vrcp14ps 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 4e 60 01 	vrsqrt14ps 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 51 60 01 	vsqrtpd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7c 08 51 60 01 	vsqrtps 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 29 60 01 	vmovapd %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7c 08 29 60 01 	vmovaps %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7f 60 01 	vmovdqa32 %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7e 08 7f 60 01 	vmovdqu32 %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7d 08 e7 60 01 	vmovntdq %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 fd 08 2b 60 01 	vmovntpd %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7c 08 2b 60 01 	vmovntps %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 fd 08 11 60 01 	vmovupd %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7c 08 11 60 01 	vmovups %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 cd 08 58 70 01 	vaddpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 58 70 01 	vaddps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 dc 70 01 	vaesenc 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 dd 70 01 	vaesenclast 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 de 70 01 	vaesdec 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 df 70 01 	vaesdeclast 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 55 70 01 	vandnpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 55 70 01 	vandnps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 54 70 01 	vandpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 54 70 01 	vandps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 5e 70 01 	vdivpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 5e 70 01 	vdivps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 cf 70 01 	vgf2p8mulb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 5f 70 01 	vmaxpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 5f 70 01 	vmaxps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 5d 70 01 	vminpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 5d 70 01 	vminps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 59 70 01 	vmulpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 59 70 01 	vmulps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 56 70 01 	vorpd  0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 56 70 01 	vorps  0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 63 70 01 	vpacksswb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 6b 70 01 	vpackssdw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 67 70 01 	vpackuswb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 2b 70 01 	vpackusdw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 fc 70 01 	vpaddb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 fd 70 01 	vpaddw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 fe 70 01 	vpaddd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 d4 70 01 	vpaddq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 ec 70 01 	vpaddsb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 ed 70 01 	vpaddsw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 dc 70 01 	vpaddusb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 dd 70 01 	vpaddusw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 db 70 01 	vpandd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 df 70 01 	vpandnd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e0 70 01 	vpavgb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e3 70 01 	vpavgw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 44 70 01 00 	vpclmullqlqdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 44 70 01 01 	vpclmulhqlqdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 44 70 01 10 	vpclmullqhqdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 44 70 01 11 	vpclmulhqhqdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 f5 70 01 	vpmaddwd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 04 70 01 	vpmaddubsw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 3c 70 01 	vpmaxsb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 ee 70 01 	vpmaxsw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 3d 70 01 	vpmaxsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 de 70 01 	vpmaxub 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 3e 70 01 	vpmaxuw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 3f 70 01 	vpmaxud 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 38 70 01 	vpminsb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 ea 70 01 	vpminsw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 39 70 01 	vpminsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 da 70 01 	vpminub 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 3a 70 01 	vpminuw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 3b 70 01 	vpminud 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa cd 08 28 70 01 	vpmuldq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e4 70 01 	vpmulhuw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 0b 70 01 	vpmulhrsw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e5 70 01 	vpmulhw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 d5 70 01 	vpmullw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 40 70 01 	vpmulld 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 f4 70 01 	vpmuludq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 eb 70 01 	vpord  0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 f6 70 01 	vpsadbw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 00 70 01 	vpshufb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 f1 70 01 	vpsllw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 f2 70 01 	vpslld 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 f3 70 01 	vpsllq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e1 70 01 	vpsraw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e2 70 01 	vpsrad 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 d1 70 01 	vpsrlw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 d2 70 01 	vpsrld 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 d3 70 01 	vpsrlq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 f8 70 01 	vpsubb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 f9 70 01 	vpsubw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 fa 70 01 	vpsubd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 fb 70 01 	vpsubq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e8 70 01 	vpsubsb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 e9 70 01 	vpsubsw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 d8 70 01 	vpsubusb 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 d9 70 01 	vpsubusw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 68 70 01 	vpunpckhbw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 69 70 01 	vpunpckhwd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 6a 70 01 	vpunpckhdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 6d 70 01 	vpunpckhqdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 60 70 01 	vpunpcklbw 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 61 70 01 	vpunpcklwd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 62 70 01 	vpunpckldq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 6c 70 01 	vpunpcklqdq 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4d 08 ef 70 01 	vpxord 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 5c 70 01 	vsubpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 5c 70 01 	vsubps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 15 70 01 	vunpckhpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 15 70 01 	vunpckhps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 14 70 01 	vunpcklpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 14 70 01 	vunpcklps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 57 70 01 	vxorpd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 57 70 01 	vxorps 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 7d 08 70 70 01 64 	vpshufd \$0x64,0x10\(%r16\),%xmm6
+[ 	]*[a-f0-9]+:	62 f9 7e 08 70 70 01 64 	vpshufhw \$0x64,0x10\(%r16\),%xmm6
+[ 	]*[a-f0-9]+:	62 f9 7f 08 70 70 01 64 	vpshuflw \$0x64,0x10\(%r16\),%xmm6
+[ 	]*[a-f0-9]+:	62 fb fd 08 09 70 01 04 	vrndscalepd \$(0x)?4,0x10\(%r16\),%xmm6
+[ 	]*[a-f0-9]+:	62 fb 7d 08 08 70 01 04 	vrndscaleps \$(0x)?4,0x10\(%r16\),%xmm6
+[ 	]*[a-f0-9]+:	62 fb cd 08 ce 70 01 64 	vgf2p8affineqb \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb cd 08 cf 70 01 64 	vgf2p8affineinvqb \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 0f 70 01 64 	vpalignr \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 44 70 01 64 	vpclmulqdq \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cd 08 c6 70 01 64 	vshufpd \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4c 08 c6 70 01 64 	vshufps \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 fd 08 2f 60 02 	vcomisd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 e6 60 02 	vcvtdq2pd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 e6 60 02 	vcvtdq2pd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7c 08 5a 60 02 	vcvtps2pd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 ff 08 12 60 02 	vmovddup 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 ff 08 10 60 02 	vmovsd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 20 60 02 	vpmovsxbw 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 23 60 02 	vpmovsxwd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 25 60 02 	vpmovsxdq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 30 60 02 	vpmovzxbw 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 33 60 02 	vpmovzxwd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 35 60 02 	vpmovzxdq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 2e 60 02 	vucomisd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 13 60 02 	vmovlpd %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7c 08 13 60 02 	vmovlps %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 fd 08 17 60 02 	vmovhpd %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7c 08 17 60 02 	vmovhps %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 ff 08 11 60 02 	vmovsd %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 dd 08 12 60 02 	vmovlpd 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5c 08 12 60 02 	vmovlps 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 dd 08 16 60 02 	vmovhpd 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5c 08 16 60 02 	vmovhps 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 7e e0    	vmovq  %xmm4,%r16
+[ 	]*[a-f0-9]+:	62 f9 fd 08 6e e0    	vmovq  %r16,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 7e e0    	vmovq  %xmm4,%r16
+[ 	]*[a-f0-9]+:	62 f9 fd 08 6e e0    	vmovq  %r16,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 fd 08 d6 60 02 	vmovq  %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 fe 08 7e 60 02 	vmovq  0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 e1 7f 08 2d c4    	vcvtsd2si %xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7f 08 2d 48 02 	vcvtsd2si 0x10\(%r16\),%ecx
+[ 	]*[a-f0-9]+:	62 e1 7f 08 2c c4    	vcvttsd2si %xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7f 08 2c 48 02 	vcvttsd2si 0x10\(%r16\),%ecx
+[ 	]*[a-f0-9]+:	62 e1 ff 08 2d c4    	vcvtsd2si %xmm4,%r16
+[ 	]*[a-f0-9]+:	62 f9 ff 08 2d 48 02 	vcvtsd2si 0x10\(%r16\),%rcx
+[ 	]*[a-f0-9]+:	62 e1 ff 08 2c c4    	vcvttsd2si %xmm4,%r16
+[ 	]*[a-f0-9]+:	62 f9 ff 08 2c 48 02 	vcvttsd2si 0x10\(%r16\),%rcx
+[ 	]*[a-f0-9]+:	62 f9 df 08 2a e0    	vcvtsi2sd %r16,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 df 08 2a 60 02 	vcvtsi2sdq 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 de 08 2a e0    	vcvtsi2ss %r16,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 de 08 2a 60 02 	vcvtsi2ssq 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb dd 08 22 e0 64 	vpinsrq \$0x64,%r16,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb dd 08 22 60 02 64 	vpinsrq \$0x64,0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb fd 08 16 e0 64 	vpextrq \$0x64,%xmm4,%r16
+[ 	]*[a-f0-9]+:	62 fb fd 08 16 60 02 64 	vpextrq \$0x64,%xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 fb cd 08 0b 70 02 04 	vrndscalesd \$(0x)?4,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 58 70 02 	vaddsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 5a 70 02 	vcvtsd2ss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 5e 70 02 	vdivsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 5f 70 02 	vmaxsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 5d 70 02 	vminsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 59 70 02 	vmulsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 51 70 02 	vsqrtsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 cf 08 5c 70 02 	vsubsd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 58 70 04 	vaddss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 5a 70 04 	vcvtss2sd 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 5e 70 04 	vdivss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 5f 70 04 	vmaxss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 5d 70 04 	vminss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 59 70 04 	vmulss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 4d 70 04 	vrcp14ss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 4d 08 4f 70 04 	vrsqrt14ss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 51 70 04 	vsqrtss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 4e 08 5c 70 04 	vsubss 0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 f9 7c 08 2f 60 04 	vcomiss 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 10 60 04 	vmovss 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 21 60 04 	vpmovsxbd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 24 60 04 	vpmovsxwq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 31 60 04 	vpmovzxbd 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 34 60 04 	vpmovzxwq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7c 08 2e 60 04 	vucomiss 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7e 08 11 60 04 	vmovss %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e e0    	vmovd  %xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e 60 04 	vmovd  %xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 7d 08 6e e0    	vmovd  %r16d,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 7d 08 6e 60 04 	vmovd  0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 e1 7e 08 2d c4    	vcvtss2si %xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7e 08 2d 48 04 	vcvtss2si 0x10\(%r16\),%ecx
+[ 	]*[a-f0-9]+:	62 e1 7e 08 2c c4    	vcvttss2si %xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7e 08 2c 48 04 	vcvttss2si 0x10\(%r16\),%ecx
+[ 	]*[a-f0-9]+:	62 e1 fe 08 2d c4    	vcvtss2si %xmm4,%r16
+[ 	]*[a-f0-9]+:	62 f9 fe 08 2d 48 04 	vcvtss2si 0x10\(%r16\),%rcx
+[ 	]*[a-f0-9]+:	62 e1 fe 08 2c c4    	vcvttss2si %xmm4,%r16
+[ 	]*[a-f0-9]+:	62 f9 fe 08 2c 48 04 	vcvttss2si 0x10\(%r16\),%rcx
+[ 	]*[a-f0-9]+:	62 fb fd 08 17 e0 64 	vextractps \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 fb 7d 08 16 e0 64 	vpextrd \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 fb 7d 08 16 60 04 64 	vpextrd \$0x64,%xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 fb 7d 08 17 e0 64 	vextractps \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 fb 7d 08 17 60 04 64 	vextractps \$0x64,%xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 fb 5d 08 22 e0 64 	vpinsrd \$0x64,%r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb 5d 08 22 60 04 64 	vpinsrd \$0x64,0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5f 08 2a e0    	vcvtsi2sd %r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5f 08 2a 60 04 	vcvtsi2sdl 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5e 08 2a e0    	vcvtsi2ss %r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5e 08 2a 60 04 	vcvtsi2ssl 0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb 4d 08 21 70 04 64 	vinsertps \$0x64,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fb 4d 08 0a 70 04 04 	vrndscaless \$(0x)?4,0x10\(%r16\),%xmm6,%xmm6
+[ 	]*[a-f0-9]+:	62 fa 7d 08 22 60 08 	vpmovsxbq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 fa 7d 08 32 60 08 	vpmovzxbq 0x10\(%r16\),%xmm4
+[ 	]*[a-f0-9]+:	62 e1 7d 08 c5 c4 64 	vpextrw \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 e1 7d 08 c5 c4 64 	vpextrw \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 fb 7d 08 15 60 08 64 	vpextrw \$0x64,%xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 f9 5d 08 c4 e0 64 	vpinsrw \$0x64,%r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5d 08 c4 e0 64 	vpinsrw \$0x64,%r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 f9 5d 08 c4 60 08 64 	vpinsrw \$0x64,0x10\(%r16\),%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb 7d 08 14 e0 64 	vpextrb \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 fb 7d 08 14 e0 64 	vpextrb \$0x64,%xmm4,%r16d
+[ 	]*[a-f0-9]+:	62 fb 7d 08 14 60 10 64 	vpextrb \$0x64,%xmm4,0x10\(%r16\)
+[ 	]*[a-f0-9]+:	62 fb 5d 08 20 e0 64 	vpinsrb \$0x64,%r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb 5d 08 20 e0 64 	vpinsrb \$0x64,%r16d,%xmm4,%xmm4
+[ 	]*[a-f0-9]+:	62 fb 5d 08 20 60 10 64 	vpinsrb \$0x64,0x10\(%r16\),%xmm4,%xmm4
+#pass
diff --git a/gas/testsuite/gas/i386/sse2avx-apx.s b/gas/testsuite/gas/i386/sse2avx-apx.s
new file mode 100644
index 0000000..f248ae9
--- /dev/null
+++ b/gas/testsuite/gas/i386/sse2avx-apx.s
@@ -0,0 +1,320 @@
+	.text
+	.sse_check warning
+sse2avx:
+
+# Tests for op mem128, xmm
+	cvtdq2ps 16(%r16),%xmm4
+	cvtpd2dq 16(%r16),%xmm4
+	cvtpd2ps 16(%r16),%xmm4
+	cvtps2dq 16(%r16),%xmm4
+	cvttpd2dq 16(%r16),%xmm4
+	cvttps2dq 16(%r16),%xmm4
+	lddqu 16(%r16),%xmm4
+	movapd 16(%r16),%xmm4
+	movaps 16(%r16),%xmm4
+	movdqa 16(%r16),%xmm4
+	movdqu 16(%r16),%xmm4
+	movntdqa 16(%r16),%xmm4
+	movshdup 16(%r16),%xmm4
+	movsldup 16(%r16),%xmm4
+	movupd 16(%r16),%xmm4
+	movups 16(%r16),%xmm4
+	pabsb 16(%r16),%xmm4
+	pabsw 16(%r16),%xmm4
+	pabsd 16(%r16),%xmm4
+	rcpps 16(%r16),%xmm4
+	rsqrtps 16(%r16),%xmm4
+	sqrtpd 16(%r16),%xmm4
+	sqrtps 16(%r16),%xmm4
+
+# Tests for op xmm, mem128
+	movapd %xmm4,16(%r16)
+	movaps %xmm4,16(%r16)
+	movdqa %xmm4,16(%r16)
+	movdqu %xmm4,16(%r16)
+	movntdq %xmm4,16(%r16)
+	movntpd %xmm4,16(%r16)
+	movntps %xmm4,16(%r16)
+	movupd %xmm4,16(%r16)
+	movups %xmm4,16(%r16)
+
+# Tests for op mem128, xmm[, xmm]
+	addpd 16(%r16),%xmm6
+	addps 16(%r16),%xmm6
+	aesenc 16(%r16),%xmm6
+	aesenclast 16(%r16),%xmm6
+	aesdec 16(%r16),%xmm6
+	aesdeclast 16(%r16),%xmm6
+	andnpd 16(%r16),%xmm6
+	andnps 16(%r16),%xmm6
+	andpd 16(%r16),%xmm6
+	andps 16(%r16),%xmm6
+	divpd 16(%r16),%xmm6
+	divps 16(%r16),%xmm6
+	gf2p8mulb 16(%r16),%xmm6
+	maxpd 16(%r16),%xmm6
+	maxps 16(%r16),%xmm6
+	minpd 16(%r16),%xmm6
+	minps 16(%r16),%xmm6
+	mulpd 16(%r16),%xmm6
+	mulps 16(%r16),%xmm6
+	orpd 16(%r16),%xmm6
+	orps 16(%r16),%xmm6
+	packsswb 16(%r16),%xmm6
+	packssdw 16(%r16),%xmm6
+	packuswb 16(%r16),%xmm6
+	packusdw 16(%r16),%xmm6
+	paddb 16(%r16),%xmm6
+	paddw 16(%r16),%xmm6
+	paddd 16(%r16),%xmm6
+	paddq 16(%r16),%xmm6
+	paddsb 16(%r16),%xmm6
+	paddsw 16(%r16),%xmm6
+	paddusb 16(%r16),%xmm6
+	paddusw 16(%r16),%xmm6
+	pand 16(%r16),%xmm6
+	pandn 16(%r16),%xmm6
+	pavgb 16(%r16),%xmm6
+	pavgw 16(%r16),%xmm6
+	pclmullqlqdq 16(%r16),%xmm6
+	pclmulhqlqdq 16(%r16),%xmm6
+	pclmullqhqdq 16(%r16),%xmm6
+	pclmulhqhqdq 16(%r16),%xmm6
+	pmaddwd 16(%r16),%xmm6
+	pmaddubsw 16(%r16),%xmm6
+	pmaxsb 16(%r16),%xmm6
+	pmaxsw 16(%r16),%xmm6
+	pmaxsd 16(%r16),%xmm6
+	pmaxub 16(%r16),%xmm6
+	pmaxuw 16(%r16),%xmm6
+	pmaxud 16(%r16),%xmm6
+	pminsb 16(%r16),%xmm6
+	pminsw 16(%r16),%xmm6
+	pminsd 16(%r16),%xmm6
+	pminub 16(%r16),%xmm6
+	pminuw 16(%r16),%xmm6
+	pminud 16(%r16),%xmm6
+	pmuldq 16(%r16),%xmm6
+	pmulhuw 16(%r16),%xmm6
+	pmulhrsw 16(%r16),%xmm6
+	pmulhw 16(%r16),%xmm6
+	pmullw 16(%r16),%xmm6
+	pmulld 16(%r16),%xmm6
+	pmuludq 16(%r16),%xmm6
+	por 16(%r16),%xmm6
+	psadbw 16(%r16),%xmm6
+	pshufb 16(%r16),%xmm6
+	psllw 16(%r16),%xmm6
+	pslld 16(%r16),%xmm6
+	psllq 16(%r16),%xmm6
+	psraw 16(%r16),%xmm6
+	psrad 16(%r16),%xmm6
+	psrlw 16(%r16),%xmm6
+	psrld 16(%r16),%xmm6
+	psrlq 16(%r16),%xmm6
+	psubb 16(%r16),%xmm6
+	psubw 16(%r16),%xmm6
+	psubd 16(%r16),%xmm6
+	psubq 16(%r16),%xmm6
+	psubsb 16(%r16),%xmm6
+	psubsw 16(%r16),%xmm6
+	psubusb 16(%r16),%xmm6
+	psubusw 16(%r16),%xmm6
+	punpckhbw 16(%r16),%xmm6
+	punpckhwd 16(%r16),%xmm6
+	punpckhdq 16(%r16),%xmm6
+	punpckhqdq 16(%r16),%xmm6
+	punpcklbw 16(%r16),%xmm6
+	punpcklwd 16(%r16),%xmm6
+	punpckldq 16(%r16),%xmm6
+	punpcklqdq 16(%r16),%xmm6
+	pxor 16(%r16),%xmm6
+	subpd 16(%r16),%xmm6
+	subps 16(%r16),%xmm6
+	unpckhpd 16(%r16),%xmm6
+	unpckhps 16(%r16),%xmm6
+	unpcklpd 16(%r16),%xmm6
+	unpcklps 16(%r16),%xmm6
+	xorpd 16(%r16),%xmm6
+	xorps 16(%r16),%xmm6
+
+# Tests for op imm8, mem128, xmm
+	pshufd $100,16(%r16),%xmm6
+	pshufhw $100,16(%r16),%xmm6
+	pshuflw $100,16(%r16),%xmm6
+	roundpd $4,16(%r16),%xmm6
+	roundps $4,16(%r16),%xmm6
+
+# Tests for op imm8, mem128, xmm[, xmm]
+	gf2p8affineqb $100,16(%r16),%xmm6
+	gf2p8affineinvqb $100,16(%r16),%xmm6
+	palignr $100,16(%r16),%xmm6
+	pclmulqdq $100,16(%r16),%xmm6
+	shufpd $100,16(%r16),%xmm6
+	shufps $100,16(%r16),%xmm6
+
+# Tests for op mem64, xmm
+	comisd 16(%r16),%xmm4
+	cvtdq2pd 16(%r16),%xmm4
+	cvtpi2pd 16(%r16),%xmm4
+	cvtps2pd 16(%r16),%xmm4
+	movddup 16(%r16),%xmm4
+	movsd 16(%r16),%xmm4
+	pmovsxbw 16(%r16),%xmm4
+	pmovsxwd 16(%r16),%xmm4
+	pmovsxdq 16(%r16),%xmm4
+	pmovzxbw 16(%r16),%xmm4
+	pmovzxwd 16(%r16),%xmm4
+	pmovzxdq 16(%r16),%xmm4
+	ucomisd 16(%r16),%xmm4
+
+# Tests for op xmm, mem64
+	movlpd %xmm4,16(%r16)
+	movlps %xmm4,16(%r16)
+	movhpd %xmm4,16(%r16)
+	movhps %xmm4,16(%r16)
+	movsd %xmm4,16(%r16)
+
+# Tests for op mem64, xmm[, xmm]
+	movlpd 16(%r16),%xmm4
+	movlps 16(%r16),%xmm4
+	movhpd 16(%r16),%xmm4
+	movhps 16(%r16),%xmm4
+
+# Tests for op xmm, regq/mem64
+# Tests for op regq/mem64, xmm
+	movd %xmm4,%r16
+	movd %r16,%xmm4
+	movq %xmm4,%r16
+	movq %r16,%xmm4
+	movq %xmm4,16(%r16)
+	movq 16(%r16),%xmm4
+
+# Tests for op xmm/mem64, regl
+	cvtsd2si %xmm4,%r16d
+	cvtsd2si 16(%r16),%ecx
+	cvttsd2si %xmm4,%r16d
+	cvttsd2si 16(%r16),%ecx
+
+# Tests for op xmm/mem64, regq
+	cvtsd2si %xmm4,%r16
+	cvtsd2si 16(%r16),%rcx
+	cvttsd2si %xmm4,%r16
+	cvttsd2si 16(%r16),%rcx
+
+# Tests for op regq/mem64, xmm[, xmm]
+	cvtsi2sdq %r16,%xmm4
+	cvtsi2sdq 16(%r16),%xmm4
+	cvtsi2ssq %r16,%xmm4
+	cvtsi2ssq 16(%r16),%xmm4
+
+# Tests for op imm8, regq/mem64, xmm[, xmm]
+	pinsrq $100,%r16,%xmm4
+	pinsrq $100,16(%r16),%xmm4
+
+# Tests for op imm8, xmm, regq/mem64
+	pextrq $100,%xmm4,%r16
+	pextrq $100,%xmm4,16(%r16)
+
+# Tests for op imm8, mem64, xmm[, xmm]
+	roundsd $4,16(%r16),%xmm6
+
+# Tests for op mem64, xmm[, xmm]
+	addsd 16(%r16),%xmm6
+	cvtsd2ss 16(%r16),%xmm6
+	divsd 16(%r16),%xmm6
+	maxsd 16(%r16),%xmm6
+	minsd 16(%r16),%xmm6
+	mulsd 16(%r16),%xmm6
+	sqrtsd 16(%r16),%xmm6
+	subsd 16(%r16),%xmm6
+
+# Tests for op mem32, xmm[, xmm]
+	addss 16(%r16),%xmm6
+	cvtss2sd 16(%r16),%xmm6
+	divss 16(%r16),%xmm6
+	maxss 16(%r16),%xmm6
+	minss 16(%r16),%xmm6
+	mulss 16(%r16),%xmm6
+	rcpss 16(%r16),%xmm6
+	rsqrtss 16(%r16),%xmm6
+	sqrtss 16(%r16),%xmm6
+	subss 16(%r16),%xmm6
+
+# Tests for op mem32, xmm
+	comiss 16(%r16),%xmm4
+	movss 16(%r16),%xmm4
+	pmovsxbd 16(%r16),%xmm4
+	pmovsxwq 16(%r16),%xmm4
+	pmovzxbd 16(%r16),%xmm4
+	pmovzxwq 16(%r16),%xmm4
+	ucomiss 16(%r16),%xmm4
+
+# Tests for op xmm, mem32
+	movss %xmm4,16(%r16)
+
+# Tests for op xmm, regl/mem32
+# Tests for op regl/mem32, xmm
+	movd %xmm4,%r16d
+	movd %xmm4,16(%r16)
+	movd %r16d,%xmm4
+	movd 16(%r16),%xmm4
+
+# Tests for op xmm/mem32, regl
+	cvtss2si %xmm4,%r16d
+	cvtss2si 16(%r16),%ecx
+	cvttss2si %xmm4,%r16d
+	cvttss2si 16(%r16),%ecx
+
+# Tests for op xmm/mem32, regq
+	cvtss2si %xmm4,%r16
+	cvtss2si 16(%r16),%rcx
+	cvttss2si %xmm4,%r16
+	cvttss2si 16(%r16),%rcx
+
+# Tests for op imm8, xmm, regq/mem32
+	extractps $100,%xmm4,%r16
+
+# Tests for op imm8, xmm, regl/mem32
+	pextrd $100,%xmm4,%r16d
+	pextrd $100,%xmm4,16(%r16)
+	extractps $100,%xmm4,%r16d
+	extractps $100,%xmm4,16(%r16)
+
+# Tests for op imm8, regl/mem32, xmm[, xmm]
+	pinsrd $100,%r16d,%xmm4
+	pinsrd $100,16(%r16),%xmm4
+
+# Tests for op regl/mem32, xmm[, xmm]
+	cvtsi2sd %r16d,%xmm4
+	cvtsi2sd 16(%r16),%xmm4
+	cvtsi2ss %r16d,%xmm4
+	cvtsi2ss 16(%r16),%xmm4
+
+# Tests for op imm8, mem32, xmm[, xmm]
+	insertps $100,16(%r16),%xmm6
+	roundss $4,16(%r16),%xmm6
+
+# Tests for op mem16, xmm
+	pmovsxbq 16(%r16),%xmm4
+	pmovzxbq 16(%r16),%xmm4
+
+# Tests for op imm8, xmm, regl/mem16
+	pextrw $100,%xmm4,%r16d
+	pextrw $100,%xmm4,%r16
+	pextrw $100,%xmm4,16(%r16)
+
+# Tests for op imm8, regl/mem16, xmm[, xmm]
+	pinsrw $100,%r16d,%xmm4
+	pinsrw $100,%r16,%xmm4
+	pinsrw $100,16(%r16),%xmm4
+
+# Tests for op imm8, xmm, regl/mem8
+	pextrb $100,%xmm4,%r16d
+	pextrb $100,%xmm4,%r16
+	pextrb $100,%xmm4,16(%r16)
+
+# Tests for op imm8, regl/mem8, xmm[, xmm]
+	pinsrb $100,%r16d,%xmm4
+	pinsrb $100,%r16,%xmm4
+	pinsrb $100,16(%r16),%xmm4
diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.d b/gas/testsuite/gas/i386/x86-64-sse2avx.d
index dbbba4f..a652ef6 100644
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.d
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.d
@@ -746,9 +746,19 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	c5 79 7e c8          	vmovd  %xmm9,%eax
 [ 	]*[a-f0-9]+:	c4 a1 79 7e c8       	vmovd  %xmm1,%eax
 [ 	]*[a-f0-9]+:	c4 e1 f9 7e c8       	vmovq  %xmm1,%rax
+[ 	]*[a-f0-9]+:	62 f1 7d 08 7e c8    	\{evex\} vmovd %xmm1,%eax
 [ 	]*[a-f0-9]+:	c5 f9 7e c8          	vmovd  %xmm1,%eax
 [ 	]*[a-f0-9]+:	c5 f9 7e c8          	vmovd  %xmm1,%eax
 [ 	]*[a-f0-9]+:	c4 e1 79 7e c8       	vmovd  %xmm1,%eax
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e c8    	vmovd  %xmm1,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e c8    	vmovd  %xmm1,%r16d
+[ 	]*[a-f0-9]+:	62 d9 7d 08 7e c8    	vmovd  %xmm1,%r24d
+[ 	]*[a-f0-9]+:	62 79 7d 08 7e c8    	vmovd  %xmm9,%r16d
+[ 	]*[a-f0-9]+:	62 b9 7d 08 7e c8    	vmovd  %xmm1,%r16d
+[ 	]*[a-f0-9]+:	62 f9 fd 08 7e c8    	vmovq  %xmm1,%r16
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e c8    	vmovd  %xmm1,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e c8    	vmovd  %xmm1,%r16d
+[ 	]*[a-f0-9]+:	62 f9 7d 08 7e c8    	vmovd  %xmm1,%r16d
 [ 	]*[a-f0-9]+:	c5 f8 ae 11          	vldmxcsr \(%rcx\)
 [ 	]*[a-f0-9]+:	c5 f8 ae 19          	vstmxcsr \(%rcx\)
 [ 	]*[a-f0-9]+:	c5 f8 5b f4          	vcvtdq2ps %xmm4,%xmm6
diff --git a/gas/testsuite/gas/i386/x86-64-sse2avx.s b/gas/testsuite/gas/i386/x86-64-sse2avx.s
index 8b37a60..4de8118 100644
--- a/gas/testsuite/gas/i386/x86-64-sse2avx.s
+++ b/gas/testsuite/gas/i386/x86-64-sse2avx.s
@@ -847,10 +847,21 @@ _start:
 	rex.r	movd	%xmm1, %eax
 	rex.x	movd	%xmm1, %eax
 	rex.w	movd	%xmm1, %eax
+	{evex}	movd	%xmm1, %eax
 	{rex}	movd	%xmm1, %eax
 	{rex2}	movd	%xmm1, %eax
 	{vex3}	movd	%xmm1, %eax
 
+		movd	%xmm1, %r16d
+	rex	movd	%xmm1, %r16d
+	rex.b	movd	%xmm1, %r16d
+	rex.r	movd	%xmm1, %r16d
+	rex.x	movd	%xmm1, %r16d
+	rex.w	movd	%xmm1, %r16d
+	{evex}	movd	%xmm1, %r16d
+	{rex}	movd	%xmm1, %r16d
+	{rex2}	movd	%xmm1, %r16d
+
 	.intel_syntax noprefix
 # Tests for op mem64
 	ldmxcsr DWORD PTR [rcx]
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index e5e469c..627626a 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -390,6 +390,7 @@ run_dump_test "x86-64-apx-jmpabs-inval"
 run_dump_test "x86-64-apx-nf"
 run_dump_test "x86-64-apx-nf-intel"
 run_dump_test "x86-64-apx_f-evex"
+run_dump_test "sse2avx-apx"
 run_dump_test "x86-64-avx512f-rcigrz-intel"
 run_dump_test "x86-64-avx512f-rcigrz"
 run_dump_test "x86-64-clwb"