2005-09-06 Paul Brook <paul@codesourcery.com>

gas/ * config/tc-arm.c (arm_it): Add relax field. (T16_32_TAB): Add addi, addis, add_pc, add_sp, dec_sp, inc_sp, b, bcond, ldr_pc, ldr_pc2, ldr_sp, str_sp, subi, subis. (do_t_add_sub, do_t_addr, do_t_branch, do_t_ldst, do_t_mov_cmp): Allow relaxation. (output_relax_insn): New function. (put_thumb32_insn): New function. (output_inst): Use new functions. (md_assemble): Don't throw error on relaxable instructions. (insns): Change "b" entry from TCE(...) to tCE(...). (md_estimate_size_before_relax): Return 2. (md_convert_frag, relax_immediate, relax_adr, relax_addsub, relax_branch, arm_relax_frag): New functions. (arm_force_relocation): Return 0 for Thumb-2 immediate operand relocations. * config/tc-arm.h (md_convert_frag): Remove definition. (md_relax_frag): Define. (arm_relax_frag): Add prototype. gas/testsuite/ * gas/arm/thumb2_relax.d: New test. * gas/arm/thumb2_relax.s: New test. * gas/arm/thumb32.d: Adjust expected results to include relaxation. * gas/arm/thumb32.s: Tweak for better coverage of relaxable instructions. Remove load/store tests.
author: Paul Brook <paul@codesourcery.com> 2005-09-06 16:59:24 +0000
committer: Paul Brook <paul@codesourcery.com> 2005-09-06 16:59:24 +0000
commit: 0110f2b896d40a2ab1d19b85f7990d1c1a45792a (patch)
tree: 0b9fef94c8cfa8d6ff26146fd8578e43db60f1b6 /gas
parent: 9a64e435419869030e27d54f0433810b8b56d1ac (diff)
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8 files changed, 1783 insertions, 1120 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 3745af3..7e37abc 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,24 @@
+2005-09-06  Paul Brook  <paul@codesourcery.com>
+
+	* config/tc-arm.c (arm_it): Add relax field.
+	(T16_32_TAB): Add addi, addis, add_pc, add_sp, dec_sp, inc_sp,
+	b, bcond, ldr_pc, ldr_pc2, ldr_sp, str_sp, subi, subis.
+	(do_t_add_sub, do_t_addr, do_t_branch, do_t_ldst,
+	do_t_mov_cmp): Allow relaxation.
+	(output_relax_insn): New function.
+	(put_thumb32_insn): New function.
+	(output_inst): Use new functions.
+	(md_assemble): Don't throw error on relaxable instructions.
+	(insns): Change "b" entry from TCE(...) to tCE(...).
+	(md_estimate_size_before_relax): Return 2.
+	(md_convert_frag, relax_immediate, relax_adr, relax_addsub,
+	relax_branch, arm_relax_frag): New functions.
+	(arm_force_relocation): Return 0 for Thumb-2 immediate operand
+	relocations.
+	* config/tc-arm.h (md_convert_frag): Remove definition.
+	(md_relax_frag): Define.
+	(arm_relax_frag): Add prototype.
+
 2005-09-02  Paul Brook  <paul@codesourcery.com>
 
 	* config/tc-arm.c (do_rn_rd): Enforce SWP operand constraints.
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 23d5bc7..30fd223 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -213,6 +213,9 @@ struct arm_it
   int		size;
   int		size_req;
   int		cond;
+  /* Set to the opcode if the instruction needs relaxation.
+     Zero if the instruction is not relaxed.  */
+  unsigned long	relax;
   struct
   {
     bfd_reloc_code_real_type type;
@@ -5759,17 +5762,24 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
    encodings (the latter only in post-V6T2 cores).  The index is the
    value used in the insns table below.  When there is more than one
    possible 16-bit encoding for the instruction, this table always
-   holds variant (1).  */
+   holds variant (1).
+   Also contains several pseudo-instructions used during relaxation.  */
 #define T16_32_TAB				\
   X(adc,   4140, eb400000),			\
   X(adcs,  4140, eb500000),			\
   X(add,   1c00, eb000000),			\
   X(adds,  1c00, eb100000),			\
+  X(addi,  0000, f1000000),			\
+  X(addis, 0000, f1100000),			\
+  X(add_pc,000f, f20f0000),			\
+  X(add_sp,000d, f10d0000),			\
   X(adr,   000f, f20f0000),			\
   X(and,   4000, ea000000),			\
   X(ands,  4000, ea100000),			\
   X(asr,   1000, fa40f000),			\
   X(asrs,  1000, fa50f000),			\
+  X(b,     e000, f000b000),			\
+  X(bcond, d000, f0008000),			\
   X(bic,   4380, ea200000),			\
   X(bics,  4380, ea300000),			\
   X(cmn,   42c0, eb100f00),			\
@@ -5777,14 +5787,19 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(cpsie, b660, f3af8400),			\
   X(cpsid, b670, f3af8600),			\
   X(cpy,   4600, ea4f0000),			\
+  X(dec_sp,80dd, f1bd0d00),			\
   X(eor,   4040, ea800000),			\
   X(eors,  4040, ea900000),			\
+  X(inc_sp,00dd, f10d0d00),			\
   X(ldmia, c800, e8900000),			\
   X(ldr,   6800, f8500000),			\
   X(ldrb,  7800, f8100000),			\
   X(ldrh,  8800, f8300000),			\
   X(ldrsb, 5600, f9100000),			\
   X(ldrsh, 5e00, f9300000),			\
+  X(ldr_pc,4800, f85f0000),			\
+  X(ldr_pc2,4800, f85f0000),			\
+  X(ldr_sp,9800, f85d0000),			\
   X(lsl,   0000, fa00f000),			\
   X(lsls,  0000, fa10f000),			\
   X(lsr,   0800, fa20f000),			\
@@ -5812,8 +5827,11 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
   X(str,   6000, f8400000),			\
   X(strb,  7000, f8000000),			\
   X(strh,  8000, f8200000),			\
+  X(str_sp,9000, f84d0000),			\
   X(sub,   1e00, eba00000),			\
   X(subs,  1e00, ebb00000),			\
+  X(subi,  8000, f1a00000),			\
+  X(subis, 8000, f1b00000),			\
   X(sxtb,  b240, fa4ff080),			\
   X(sxth,  b200, fa0ff080),			\
   X(tst,   4200, ea100f00),			\
@@ -5875,17 +5893,61 @@ do_t_add_sub (void)
 
   if (unified_syntax)
     {
+      bfd_boolean flags;
+      bfd_boolean narrow;
+      int opcode;
+
+      flags = (inst.instruction == T_MNEM_adds
+	       || inst.instruction == T_MNEM_subs);
+      if (flags)
+	narrow = (current_it_mask == 0);
+      else
+	narrow = (current_it_mask != 0);
       if (!inst.operands[2].isreg)
 	{
-	  /* ??? Convert large immediates to addw/subw.  */
-	  /* ??? 16-bit adds with small immediates.  */
-	  /* For an immediate, we always generate a 32-bit opcode;
-	     section relaxation will shrink it later if possible.  */
-	  inst.instruction = THUMB_OP32 (inst.instruction);
-	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-	  inst.instruction |= inst.operands[0].reg << 8;
-	  inst.instruction |= inst.operands[1].reg << 16;
-	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	  opcode = 0;
+	  if (inst.size_req != 4)
+	    {
+	      int add;
+
+	      add = (inst.instruction == T_MNEM_add
+		     || inst.instruction == T_MNEM_adds);
+	      /* Attempt to use a narrow opcode, with relaxation if
+	         appropriate.  */
+	      if (Rd == REG_SP && Rs == REG_SP && !flags)
+		opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
+	      else if (Rd <= 7 && Rs == REG_SP && add && !flags)
+		opcode = T_MNEM_add_sp;
+	      else if (Rd <= 7 && Rs == REG_PC && add && !flags)
+		opcode = T_MNEM_add_pc;
+	      else if (Rd <= 7 && Rs <= 7 && narrow)
+		{
+		  if (flags)
+		    opcode = add ? T_MNEM_addis : T_MNEM_subis;
+		  else
+		    opcode = add ? T_MNEM_addi : T_MNEM_subi;
+		}
+	      if (opcode)
+		{
+		  inst.instruction = THUMB_OP16(opcode);
+		  inst.instruction |= (Rd << 4) | Rs;
+		  inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+		  if (inst.size_req != 2)
+		    inst.relax = opcode;
+		}
+	      else
+		constraint (inst.size_req == 2, BAD_HIREG);
+	    }
+	  if (inst.size_req == 4
+	      || (inst.size_req != 2 && !opcode))
+	    {
+	      /* ??? Convert large immediates to addw/subw.  */
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      inst.instruction |= inst.operands[1].reg << 16;
+	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	    }
 	}
       else
 	{
@@ -5893,13 +5955,6 @@ do_t_add_sub (void)
 	  /* See if we can do this with a 16-bit instruction.  */
 	  if (!inst.operands[2].shifted && inst.size_req != 4)
 	    {
-	      bfd_boolean narrow;
-
-	      if (inst.instruction == T_MNEM_adds
-		  || inst.instruction == T_MNEM_subs)
-		narrow = (current_it_mask == 0);
-	      else
-		narrow = (current_it_mask != 0);
 	      if (Rd > 7 || Rs > 7 || Rn > 7)
 		narrow = FALSE;
 
@@ -5992,10 +6047,16 @@ do_t_add_sub (void)
 static void
 do_t_adr (void)
 {
-  if (unified_syntax && inst.size_req != 2)
+  if (unified_syntax && inst.size_req == 0 && inst.operands[0].reg <= 7)
+    {
+      /* Defer to section relaxation.  */
+      inst.relax = inst.instruction;
+      inst.instruction = THUMB_OP16 (inst.instruction);
+      inst.instruction |= inst.operands[0].reg << 4;
+    }
+  else if (unified_syntax && inst.size_req != 2)
     {
-      /* Always generate a 32-bit opcode;
-	 section relaxation will shrink it later if possible.  */
+      /* Generate a 32-bit opcode.  */
       inst.instruction = THUMB_OP32 (inst.instruction);
       inst.instruction |= inst.operands[0].reg << 8;
       inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
@@ -6003,6 +6064,7 @@ do_t_adr (void)
     }
   else
     {
+      /* Generate a 16-bit opcode.  */
       inst.instruction = THUMB_OP16 (inst.instruction);
       inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
       inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */
@@ -6266,29 +6328,37 @@ do_t_blx (void)
 static void
 do_t_branch (void)
 {
-  if (unified_syntax && inst.size_req != 2)
+  int opcode;
+  if (inst.cond != COND_ALWAYS)
+    opcode = T_MNEM_bcond;
+  else
+    opcode = inst.instruction;
+
+  if (unified_syntax && inst.size_req == 4)
     {
+      inst.instruction = THUMB_OP32(opcode);
       if (inst.cond == COND_ALWAYS)
-	{
-	  inst.instruction = 0xf000b000;
-	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
-	}
+	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH25;
       else
 	{
 	  assert (inst.cond != 0xF);
-	  inst.instruction = (inst.cond << 22) | 0xf0008000;
+	  inst.instruction |= inst.cond << 22;
 	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH20;
 	}
     }
   else
     {
+      inst.instruction = THUMB_OP16(opcode);
       if (inst.cond == COND_ALWAYS)
 	inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH12;
       else
 	{
-	  inst.instruction = 0xd000 | (inst.cond << 8);
+	  inst.instruction |= inst.cond << 8;
 	  inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH9;
 	}
+      /* Allow section relaxation.  */
+      if (unified_syntax && inst.size_req != 2)
+	inst.relax = opcode;
     }
 
   inst.reloc.pc_rel = 1;
@@ -6562,21 +6632,67 @@ do_t_ldrexd (void)
 static void
 do_t_ldst (void)
 {
+  unsigned long opcode;
+  int Rn;
+
+  opcode = inst.instruction;
   if (unified_syntax)
     {
-      /* Generation of 16-bit instructions for anything other than
-	 Rd, [Rn, Ri] is deferred to section relaxation time.  */
-      if (inst.operands[1].isreg && inst.operands[1].immisreg
+      if (inst.operands[1].isreg
+	  && !inst.operands[1].writeback
 	  && !inst.operands[1].shifted && !inst.operands[1].postind
 	  && !inst.operands[1].negative && inst.operands[0].reg <= 7
-	  && inst.operands[1].reg <= 7 && inst.operands[1].imm <= 7
-	  && inst.instruction <= 0xffff)
+	  && opcode <= 0xffff
+	  && inst.size_req != 4)
 	{
-	  inst.instruction = THUMB_OP16 (inst.instruction);
-	  goto op16;
+	  /* Insn may have a 16-bit form.  */
+	  Rn = inst.operands[1].reg;
+	  if (inst.operands[1].immisreg)
+	    {
+	      inst.instruction = THUMB_OP16 (opcode);
+	      /* [Rn, Ri] */
+	      if (Rn <= 7 && inst.operands[1].imm <= 7)
+		goto op16;
+	    }
+	  else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
+		    && opcode != T_MNEM_ldrsb)
+		   || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
+		   || (Rn == REG_SP && opcode == T_MNEM_str))
+	    {
+	      /* [Rn, #const] */
+	      if (Rn > 7)
+		{
+		  if (Rn == REG_PC)
+		    {
+		      if (inst.reloc.pc_rel)
+			opcode = T_MNEM_ldr_pc2;
+		      else
+			opcode = T_MNEM_ldr_pc;
+		    }
+		  else
+		    {
+		      if (opcode == T_MNEM_ldr)
+			opcode = T_MNEM_ldr_sp;
+		      else
+			opcode = T_MNEM_str_sp;
+		    }
+		  inst.instruction = inst.operands[0].reg << 8;
+		}
+	      else
+		{
+		  inst.instruction = inst.operands[0].reg;
+		  inst.instruction |= inst.operands[1].reg << 3;
+		}
+	      inst.instruction |= THUMB_OP16 (opcode);
+	      if (inst.size_req == 2)
+		inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
+	      else
+		inst.relax = opcode;
+	      return;
+	    }
 	}
-
-      inst.instruction = THUMB_OP32 (inst.instruction);
+      /* Definitely a 32-bit variant.  */
+      inst.instruction = THUMB_OP32 (opcode);
       inst.instruction |= inst.operands[0].reg << 12;
       encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
       return;
@@ -6708,26 +6824,41 @@ do_t_mov_cmp (void)
     {
       int r0off = (inst.instruction == T_MNEM_mov
 		   || inst.instruction == T_MNEM_movs) ? 8 : 16;
+      unsigned long opcode;
       bfd_boolean narrow;
       bfd_boolean low_regs;
 
       low_regs = (inst.operands[0].reg <= 7 && inst.operands[1].reg <= 7);
+      opcode = inst.instruction;
       if (current_it_mask)
-	narrow = inst.instruction != T_MNEM_movs;
+	narrow = opcode != T_MNEM_movs;
       else
-	narrow = inst.instruction != T_MNEM_movs || low_regs;
+	narrow = opcode != T_MNEM_movs || low_regs;
       if (inst.size_req == 4
 	  || inst.operands[1].shifted)
 	narrow = FALSE;
 
       if (!inst.operands[1].isreg)
 	{
-	  /* For an immediate, we always generate a 32-bit opcode;
-	     section relaxation will shrink it later if possible.  */
-	  inst.instruction = THUMB_OP32 (inst.instruction);
-	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
-	  inst.instruction |= inst.operands[0].reg << r0off;
-	  inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	  /* Immediate operand.  */
+	  if (current_it_mask == 0 && opcode == T_MNEM_mov)
+	    narrow = 0;
+	  if (low_regs && narrow)
+	    {
+	      inst.instruction = THUMB_OP16 (opcode);
+	      inst.instruction |= inst.operands[0].reg << 8;
+	      if (inst.size_req == 2)
+		inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
+	      else
+		inst.relax = opcode;
+	    }
+	  else
+	    {
+	      inst.instruction = THUMB_OP32 (inst.instruction);
+	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
+	      inst.instruction |= inst.operands[0].reg << r0off;
+	      inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	    }
 	}
       else if (!narrow)
 	{
@@ -7501,6 +7632,46 @@ fix_new_arm (fragS *	   frag,
   new_fix->tc_fix_data = thumb_mode;
 }
 
+/* Create a frg for an instruction requiring relaxation.  */
+static void
+output_relax_insn (void)
+{
+  char * to;
+  symbolS *sym;
+  int offset;
+
+  switch (inst.reloc.exp.X_op)
+    {
+    case O_symbol:
+      sym = inst.reloc.exp.X_add_symbol;
+      offset = inst.reloc.exp.X_add_number;
+      break;
+    case O_constant:
+      sym = NULL;
+      offset = inst.reloc.exp.X_add_number;
+      break;
+    default:
+      sym = make_expr_symbol (&inst.reloc.exp);
+      offset = 0;
+      break;
+  }
+  to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
+		 inst.relax, sym, offset, NULL/*offset, opcode*/);
+  md_number_to_chars (to, inst.instruction, THUMB_SIZE);
+
+#ifdef OBJ_ELF
+  dwarf2_emit_insn (INSN_SIZE);
+#endif
+}
+
+/* Write a 32-bit thumb instruction to buf.  */
+static void
+put_thumb32_insn (char * buf, unsigned long insn)
+{
+  md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
+  md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
+}
+
 static void
 output_inst (const char * str)
 {
@@ -7511,6 +7682,10 @@ output_inst (const char * str)
       as_bad ("%s -- `%s'", inst.error, str);
       return;
     }
+  if (inst.relax) {
+      output_relax_insn();
+      return;
+  }
   if (inst.size == 0)
     return;
 
@@ -7519,8 +7694,7 @@ output_inst (const char * str)
   if (thumb_mode && (inst.size > THUMB_SIZE))
     {
       assert (inst.size == (2 * THUMB_SIZE));
-      md_number_to_chars (to, inst.instruction >> 16, THUMB_SIZE);
-      md_number_to_chars (to + THUMB_SIZE, inst.instruction, THUMB_SIZE);
+      put_thumb32_insn (to, inst.instruction);
     }
   else if (inst.size > INSN_SIZE)
     {
@@ -7819,7 +7993,7 @@ md_assemble (char *str)
       if (current_it_mask == 0x10)
 	current_it_mask = 0;
 
-      if (!inst.error)
+      if (!(inst.error || inst.relax))
 	{
 	  assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
 	  inst.size = (inst.instruction > 0xffff ? 4 : 2);
@@ -8364,7 +8538,7 @@ static const struct asm_opcode insns[] =
  tC3(ldmfd,	8900000, ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
 
  TCE(swi,	f000000, df00,     1, (EXPi),        swi, t_swi),
- TCE(b,		a000000, e000,	   1, (EXPr),	     branch, t_branch),
+ tCE(b,		a000000, b,	   1, (EXPr),	     branch, t_branch),
  TCE(bl,	b000000, f000f800, 1, (EXPr),	     branch, t_branch23),
 
   /* Pseudo ops.  */
@@ -9600,12 +9774,344 @@ md_chars_to_number (char * buf, int n)
 
 /* MD interface: Sections.  */
 
+/* Estimate the size of a frag before relaxing.  Assume everything fits in
+   2 bytes.  */
+
 int
-md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED,
+md_estimate_size_before_relax (fragS * fragp,
 			       segT    segtype ATTRIBUTE_UNUSED)
 {
-  as_fatal (_("md_estimate_size_before_relax\n"));
-  return 1;
+  fragp->fr_var = 2;
+  return 2;
+}
+
+/* Convert a machine dependent frag.  */
+
+void
+md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
+{
+  unsigned long insn;
+  unsigned long old_op;
+  char *buf;
+  expressionS exp;
+  fixS *fixp;
+  int reloc_type;
+  int pc_rel;
+  int opcode;
+
+  buf = fragp->fr_literal + fragp->fr_fix;
+
+  old_op = bfd_get_16(abfd, buf);
+  if (fragp->fr_symbol) {
+      exp.X_op = O_symbol;
+      exp.X_add_symbol = fragp->fr_symbol;
+  } else {
+      exp.X_op = O_constant;
+  }
+  exp.X_add_number = fragp->fr_offset;
+  opcode = fragp->fr_subtype;
+  switch (opcode)
+    {
+    case T_MNEM_ldr_pc:
+    case T_MNEM_ldr_pc2:
+    case T_MNEM_ldr_sp:
+    case T_MNEM_str_sp:
+    case T_MNEM_ldr:
+    case T_MNEM_ldrb:
+    case T_MNEM_ldrh:
+    case T_MNEM_str:
+    case T_MNEM_strb:
+    case T_MNEM_strh:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32(opcode);
+	  if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
+	    {
+	      insn |= (old_op & 0x700) << 4;
+	    }
+	  else
+	    {
+	      insn |= (old_op & 7) << 12;
+	      insn |= (old_op & 0x38) << 13;
+	    }
+	  insn |= 0x00000c00;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
+	}
+      else
+	{
+	  reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
+	}
+      pc_rel = (opcode == T_MNEM_ldr_pc2);
+      break;
+    case T_MNEM_adr:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32 (opcode);
+	  insn |= (old_op & 0xf0) << 4;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
+	}
+      else
+	{
+	  reloc_type = BFD_RELOC_ARM_THUMB_ADD;
+	  exp.X_add_number -= 4;
+	}
+      pc_rel = 1;
+      break;
+    case T_MNEM_mov:
+    case T_MNEM_movs:
+    case T_MNEM_cmp:
+    case T_MNEM_cmn:
+      if (fragp->fr_var == 4)
+	{
+	  int r0off = (opcode == T_MNEM_mov
+		       || opcode == T_MNEM_movs) ? 0 : 8;
+	  insn = THUMB_OP32 (opcode);
+	  insn = (insn & 0xe1ffffff) | 0x10000000;
+	  insn |= (old_op & 0x700) << r0off;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	{
+	  reloc_type = BFD_RELOC_ARM_THUMB_IMM;
+	}
+      pc_rel = 0;
+      break;
+    case T_MNEM_b:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32(opcode);
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
+	}
+      else
+	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
+      pc_rel = 1;
+      break;
+    case T_MNEM_bcond:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32(opcode);
+	  insn |= (old_op & 0xf00) << 14;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
+	}
+      else
+	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
+      pc_rel = 1;
+      break;
+    case T_MNEM_add_sp:
+    case T_MNEM_add_pc:
+    case T_MNEM_inc_sp:
+    case T_MNEM_dec_sp:
+      if (fragp->fr_var == 4)
+	{
+	  /* ??? Choose between add and addw.  */
+	  insn = THUMB_OP32 (opcode);
+	  insn |= (old_op & 0xf0) << 4;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
+      pc_rel = 0;
+      break;
+
+    case T_MNEM_addi:
+    case T_MNEM_addis:
+    case T_MNEM_subi:
+    case T_MNEM_subis:
+      if (fragp->fr_var == 4)
+	{
+	  insn = THUMB_OP32 (opcode);
+	  insn |= (old_op & 0xf0) << 4;
+	  insn |= (old_op & 0xf) << 16;
+	  put_thumb32_insn (buf, insn);
+	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
+	}
+      else
+	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
+      pc_rel = 0;
+      break;
+    default:
+      abort();
+    }
+  fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
+		      reloc_type);
+  fixp->fx_file = fragp->fr_file;
+  fixp->fx_line = fragp->fr_line;
+  fragp->fr_fix += fragp->fr_var;
+}
+
+/* Return the size of a relaxable immediate operand instruction.
+   SHIFT and SIZE specify the form of the allowable immediate.  */
+static int
+relax_immediate (fragS *fragp, int size, int shift)
+{
+  offsetT offset;
+  offsetT mask;
+  offsetT low;
+
+  /* ??? Should be able to do better than this.  */
+  if (fragp->fr_symbol)
+    return 4;
+
+  low = (1 << shift) - 1;
+  mask = (1 << (shift + size)) - (1 << shift);
+  offset = fragp->fr_offset;
+  /* Force misaligned offsets to 32-bit variant.  */
+  if (offset & low)
+    return -4;
+  if (offset & ~mask)
+    return 4;
+  return 2;
+}
+
+/* Return the size of a relaxable adr pseudo-instruction or PC-relative
+   load.  */
+static int
+relax_adr (fragS *fragp, asection *sec)
+{
+  addressT addr;
+  offsetT val;
+
+  /* Assume worst case for symbols not known to be in the same section.  */
+  if (!S_IS_DEFINED(fragp->fr_symbol)
+      || sec != S_GET_SEGMENT (fragp->fr_symbol))
+    return 4;
+
+  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  addr = fragp->fr_address + fragp->fr_fix;
+  addr = (addr + 4) & ~3;
+  /* Fix the insn as the 4-byte version if the target address is not
+     sufficiently aligned.  This is prevents an infinite loop when two
+     instructions have contradictory range/alignment requirements.  */
+  if (val & 3)
+    return -4;
+  val -= addr;
+  if (val < 0 || val > 1020)
+    return 4;
+  return 2;
+}
+
+/* Return the size of a relaxable add/sub immediate instruction.  */
+static int
+relax_addsub (fragS *fragp, asection *sec)
+{
+  char *buf;
+  int op;
+
+  buf = fragp->fr_literal + fragp->fr_fix;
+  op = bfd_get_16(sec->owner, buf);
+  if ((op & 0xf) == ((op >> 4) & 0xf))
+    return relax_immediate (fragp, 8, 0);
+  else
+    return relax_immediate (fragp, 3, 0);
+}
+
+
+/* Return the size of a relaxable branch instruction.  BITS is the
+   size of the offset field in the narrow instruction.  */
+
+static int
+relax_branch (fragS *fragp, asection *sec, int bits)
+{
+  addressT addr;
+  offsetT val;
+  offsetT limit;
+
+  /* Assume worst case for symbols not known to be in the same section.  */
+  if (!S_IS_DEFINED(fragp->fr_symbol)
+      || sec != S_GET_SEGMENT (fragp->fr_symbol))
+    return 4;
+
+  val = S_GET_VALUE(fragp->fr_symbol) + fragp->fr_offset;
+  addr = fragp->fr_address + fragp->fr_fix + 4;
+  val -= addr;
+
+  /* Offset is a signed value *2 */
+  limit = 1 << bits;
+  if (val >= limit || val < -limit)
+    return 4;
+  return 2;
+}
+
+
+/* Relax a machine dependent frag.  This returns the amount by which
+   the current size of the frag should change.  */
+
+int
+arm_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED)
+{
+  int oldsize;
+  int newsize;
+
+  oldsize = fragp->fr_var;
+  switch (fragp->fr_subtype)
+    {
+    case T_MNEM_ldr_pc2:
+      newsize = relax_adr(fragp, sec);
+      break;
+    case T_MNEM_ldr_pc:
+    case T_MNEM_ldr_sp:
+    case T_MNEM_str_sp:
+      newsize = relax_immediate(fragp, 8, 2);
+      break;
+    case T_MNEM_ldr:
+    case T_MNEM_str:
+      newsize = relax_immediate(fragp, 5, 2);
+      break;
+    case T_MNEM_ldrh:
+    case T_MNEM_strh:
+      newsize = relax_immediate(fragp, 5, 1);
+      break;
+    case T_MNEM_ldrb:
+    case T_MNEM_strb:
+      newsize = relax_immediate(fragp, 5, 0);
+      break;
+    case T_MNEM_adr:
+      newsize = relax_adr(fragp, sec);
+      break;
+    case T_MNEM_mov:
+    case T_MNEM_movs:
+    case T_MNEM_cmp:
+    case T_MNEM_cmn:
+      newsize = relax_immediate(fragp, 8, 0);
+      break;
+    case T_MNEM_b:
+      newsize = relax_branch(fragp, sec, 11);
+      break;
+    case T_MNEM_bcond:
+      newsize = relax_branch(fragp, sec, 8);
+      break;
+    case T_MNEM_add_sp:
+    case T_MNEM_add_pc:
+      newsize = relax_immediate (fragp, 8, 2);
+      break;
+    case T_MNEM_inc_sp:
+    case T_MNEM_dec_sp:
+      newsize = relax_immediate (fragp, 7, 2);
+      break;
+    case T_MNEM_addi:
+    case T_MNEM_addis:
+    case T_MNEM_subi:
+    case T_MNEM_subis:
+      newsize = relax_addsub (fragp, sec);
+      break;
+    default:
+      abort();
+    }
+  if (newsize < 0)
+    {
+      fragp->fr_var = -newsize;
+      md_convert_frag (sec->owner, sec, fragp);
+      frag_wane(fragp);
+      return -(newsize + oldsize);
+    }
+  fragp->fr_var = newsize;
+  return newsize - oldsize;
 }
 
 /* Round up a section size to the appropriate boundary.	 */
@@ -11476,7 +11982,10 @@ arm_force_relocation (struct fix * fixp)
   /* Resolve these relocations even if the symbol is extern or weak.  */
   if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
       || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
-      || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE)
+      || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
+      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
     return 0;
 
   return generic_force_reloc (fixp);
diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h
index 1def078..c2ae6d6 100644
--- a/gas/config/tc-arm.h
+++ b/gas/config/tc-arm.h
@@ -79,7 +79,9 @@ struct fix;
 
 #define TC_FORCE_RELOCATION(FIX) arm_force_relocation (FIX)
 
-#define md_convert_frag(b, s, f) { as_fatal (_("arm convert_frag\n")); }
+#define md_relax_frag(segment, fragp, stretch) \
+  arm_relax_frag(segment, fragp, stretch)
+extern int arm_relax_frag (asection *, struct frag *, long);
 
 #define md_cleanup() arm_cleanup ()
 
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 421db35..78690df 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2005-09-06  Paul Brook  <paul@codesourcery.com>
+
+	* gas/arm/thumb2_relax.d: New test.
+	* gas/arm/thumb2_relax.s: New test.
+	* gas/arm/thumb32.d: Adjust expected results to include relaxation.
+	* gas/arm/thumb32.s: Tweak for better coverage of relaxable
+	instructions.  Remove load/store tests.
+
 2005-09-02  Paul Brook  <paul@codesourcery.com>
 
 	* gas/arm/arm3-bad.s: New test.
diff --git a/gas/testsuite/gas/arm/thumb2_relax.d b/gas/testsuite/gas/arm/thumb2_relax.d
new file mode 100644
index 0000000..48cd1f2
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_relax.d
@@ -0,0 +1,155 @@
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> 7829      	ldrb	r1, \[r5, #0\]
+0+002 <[^>]+> f895 1023 	ldrb.w	r1, \[r5, #35\]
+0+006 <[^>]+> 7fe9      	ldrb	r1, \[r5, #31\]
+0+008 <[^>]+> f895 101f 	ldrb.w	r1, \[r5, #31\]
+0+00c <[^>]+> f815 1c1f 	ldrb.w	r1, \[r5, #-31\]
+0+010 <[^>]+> f815 1b1f 	ldrb.w	r1, \[r5\], #31
+0+014 <[^>]+> f815 1b1f 	ldrb.w	r1, \[r5\], #31
+0+018 <[^>]+> f815 1f1f 	ldrb.w	r1, \[r5, #31\]!
+0+01c <[^>]+> f815 1d1f 	ldrb.w	r1, \[r5, #-31\]!
+0+020 <[^>]+> 5d29      	ldrb	r1, \[r5, r4\]
+0+022 <[^>]+> f819 100c 	ldrb.w	r1, \[r9, ip\]
+0+026 <[^>]+> f89f 1014 	ldrb.w	r1, \[pc, #20\]	; 0+03c <[^>]+>
+0+02a <[^>]+> f89f 1010 	ldrb.w	r1, \[pc, #16\]	; 0+03c <[^>]+>
+0+02e <[^>]+> f89f 800c 	ldrb.w	r8, \[pc, #12\]	; 0+03c <[^>]+>
+0+032 <[^>]+> f89f 100a 	ldrb.w	r1, \[pc, #10\]	; 0+03e <[^>]+>
+0+036 <[^>]+> f81f 1038 	ldrb.w	r1, \[pc, #-56\]	; 0+000 <[^>]+>
+0+03a <[^>]+> 0000      	lsls	r0, r0, #0
+0+03c <[^>]+> bf00      	nop
+0+03e <[^>]+> f995 1000 	ldrsb.w	r1, \[r5\]
+0+042 <[^>]+> f995 1023 	ldrsb.w	r1, \[r5, #35\]
+0+046 <[^>]+> f995 101f 	ldrsb.w	r1, \[r5, #31\]
+0+04a <[^>]+> f995 101f 	ldrsb.w	r1, \[r5, #31\]
+0+04e <[^>]+> f915 1c1f 	ldrsb.w	r1, \[r5, #-31\]
+0+052 <[^>]+> f915 1b1f 	ldrsb.w	r1, \[r5\], #31
+0+056 <[^>]+> f915 1b1f 	ldrsb.w	r1, \[r5\], #31
+0+05a <[^>]+> f915 1f1f 	ldrsb.w	r1, \[r5, #31\]!
+0+05e <[^>]+> f915 1d1f 	ldrsb.w	r1, \[r5, #-31\]!
+0+062 <[^>]+> 5729      	ldrsb	r1, \[r5, r4\]
+0+064 <[^>]+> f919 100c 	ldrsb.w	r1, \[r9, ip\]
+0+068 <[^>]+> f99f 1010 	ldrsb.w	r1, \[pc, #16\]	; 0+07c <[^>]+>
+0+06c <[^>]+> f99f 100c 	ldrsb.w	r1, \[pc, #12\]	; 0+07c <[^>]+>
+0+070 <[^>]+> f99f 8008 	ldrsb.w	r8, \[pc, #8\]	; 0+07c <[^>]+>
+0+074 <[^>]+> f99f 1006 	ldrsb.w	r1, \[pc, #6\]	; 0+07e <[^>]+>
+0+078 <[^>]+> f91f 103e 	ldrsb.w	r1, \[pc, #-62\]	; 0+03e <[^>]+>
+0+07c <[^>]+> bf00      	nop
+0+07e <[^>]+> 8829      	ldrh	r1, \[r5, #0\]
+0+080 <[^>]+> f8b5 1042 	ldrh.w	r1, \[r5, #66\]
+0+084 <[^>]+> 8fe9      	ldrh	r1, \[r5, #62\]
+0+086 <[^>]+> f8b5 103e 	ldrh.w	r1, \[r5, #62\]
+0+08a <[^>]+> f835 1c3e 	ldrh.w	r1, \[r5, #-62\]
+0+08e <[^>]+> f835 1b3e 	ldrh.w	r1, \[r5\], #62
+0+092 <[^>]+> f835 1b3e 	ldrh.w	r1, \[r5\], #62
+0+096 <[^>]+> f835 1f3e 	ldrh.w	r1, \[r5, #62\]!
+0+09a <[^>]+> f835 1d3e 	ldrh.w	r1, \[r5, #-62\]!
+0+09e <[^>]+> 5b29      	ldrh	r1, \[r5, r4\]
+0+0a0 <[^>]+> f839 100c 	ldrh.w	r1, \[r9, ip\]
+0+0a4 <[^>]+> f8bf 1010 	ldrh.w	r1, \[pc, #16\]	; 0+0b8 <[^>]+>
+0+0a8 <[^>]+> f8bf 100c 	ldrh.w	r1, \[pc, #12\]	; 0+0b8 <[^>]+>
+0+0ac <[^>]+> f8bf 8008 	ldrh.w	r8, \[pc, #8\]	; 0+0b8 <[^>]+>
+0+0b0 <[^>]+> f8bf 1006 	ldrh.w	r1, \[pc, #6\]	; 0+0ba <[^>]+>
+0+0b4 <[^>]+> f83f 103a 	ldrh.w	r1, \[pc, #-58\]	; 0+07e <[^>]+>
+0+0b8 <[^>]+> bf00      	nop
+0+0ba <[^>]+> f9b5 1000 	ldrsh.w	r1, \[r5\]
+0+0be <[^>]+> f9b5 1042 	ldrsh.w	r1, \[r5, #66\]
+0+0c2 <[^>]+> f9b5 103e 	ldrsh.w	r1, \[r5, #62\]
+0+0c6 <[^>]+> f9b5 103e 	ldrsh.w	r1, \[r5, #62\]
+0+0ca <[^>]+> f935 1c3e 	ldrsh.w	r1, \[r5, #-62\]
+0+0ce <[^>]+> f935 1b3e 	ldrsh.w	r1, \[r5\], #62
+0+0d2 <[^>]+> f935 1b3e 	ldrsh.w	r1, \[r5\], #62
+0+0d6 <[^>]+> f935 1f3e 	ldrsh.w	r1, \[r5, #62\]!
+0+0da <[^>]+> f935 1d3e 	ldrsh.w	r1, \[r5, #-62\]!
+0+0de <[^>]+> 5f29      	ldrsh	r1, \[r5, r4\]
+0+0e0 <[^>]+> f939 100c 	ldrsh.w	r1, \[r9, ip\]
+0+0e4 <[^>]+> f9bf 1010 	ldrsh.w	r1, \[pc, #16\]	; 0+0f8 <[^>]+>
+0+0e8 <[^>]+> f9bf 100c 	ldrsh.w	r1, \[pc, #12\]	; 0+0f8 <[^>]+>
+0+0ec <[^>]+> f9bf 8008 	ldrsh.w	r8, \[pc, #8\]	; 0+0f8 <[^>]+>
+0+0f0 <[^>]+> f9bf 1006 	ldrsh.w	r1, \[pc, #6\]	; 0+0fa <[^>]+>
+0+0f4 <[^>]+> f93f 103e 	ldrsh.w	r1, \[pc, #-62\]	; 0+0ba <[^>]+>
+0+0f8 <[^>]+> bf00      	nop
+0+0fa <[^>]+> 6829      	ldr	r1, \[r5, #0\]
+0+0fc <[^>]+> f8d5 1080 	ldr.w	r1, \[r5, #128\]
+0+100 <[^>]+> 6fe9      	ldr	r1, \[r5, #124\]
+0+102 <[^>]+> f8d5 107c 	ldr.w	r1, \[r5, #124\]
+0+106 <[^>]+> f855 1c7c 	ldr.w	r1, \[r5, #-124\]
+0+10a <[^>]+> f855 1b7c 	ldr.w	r1, \[r5\], #124
+0+10e <[^>]+> f855 1b7c 	ldr.w	r1, \[r5\], #124
+0+112 <[^>]+> f855 1f7c 	ldr.w	r1, \[r5, #124\]!
+0+116 <[^>]+> f855 1d7c 	ldr.w	r1, \[r5, #-124\]!
+0+11a <[^>]+> 5929      	ldr	r1, \[r5, r4\]
+0+11c <[^>]+> f859 100c 	ldr.w	r1, \[r9, ip\]
+0+120 <[^>]+> 4904      	ldr	r1, \[pc, #16\]	\(0+134 <[^>]+>\)
+0+122 <[^>]+> f8df 1010 	ldr.w	r1, \[pc, #16\]	; 0+134 <[^>]+>
+0+126 <[^>]+> f8df 800c 	ldr.w	r8, \[pc, #12\]	; 0+134 <[^>]+>
+0+12a <[^>]+> f8df 100a 	ldr.w	r1, \[pc, #10\]	; 0+136 <[^>]+>
+0+12e <[^>]+> f85f 1036 	ldr.w	r1, \[pc, #-54\]	; 0+0fa <[^>]+>
+0+132 <[^>]+> 0000      	lsls	r0, r0, #0
+0+134 <[^>]+> bf00      	nop
+0+136 <[^>]+> 7029      	strb	r1, \[r5, #0\]
+0+138 <[^>]+> f885 1023 	strb.w	r1, \[r5, #35\]
+0+13c <[^>]+> 77e9      	strb	r1, \[r5, #31\]
+0+13e <[^>]+> f885 101f 	strb.w	r1, \[r5, #31\]
+0+142 <[^>]+> f805 1c1f 	strb.w	r1, \[r5, #-31\]
+0+146 <[^>]+> f805 1b1f 	strb.w	r1, \[r5\], #31
+0+14a <[^>]+> f805 1b1f 	strb.w	r1, \[r5\], #31
+0+14e <[^>]+> f805 1f1f 	strb.w	r1, \[r5, #31\]!
+0+152 <[^>]+> f805 1d1f 	strb.w	r1, \[r5, #-31\]!
+0+156 <[^>]+> 5529      	strb	r1, \[r5, r4\]
+0+158 <[^>]+> f809 100c 	strb.w	r1, \[r9, ip\]
+0+15c <[^>]+> f88f 1010 	strb.w	r1, \[pc, #16\]	; 0+170 <[^>]+>
+0+160 <[^>]+> f88f 100c 	strb.w	r1, \[pc, #12\]	; 0+170 <[^>]+>
+0+164 <[^>]+> f88f 8008 	strb.w	r8, \[pc, #8\]	; 0+170 <[^>]+>
+0+168 <[^>]+> f88f 1006 	strb.w	r1, \[pc, #6\]	; 0+172 <[^>]+>
+0+16c <[^>]+> f80f 103a 	strb.w	r1, \[pc, #-58\]	; 0+136 <[^>]+>
+0+170 <[^>]+> bf00      	nop
+0+172 <[^>]+> 8029      	strh	r1, \[r5, #0\]
+0+174 <[^>]+> f8a5 1042 	strh.w	r1, \[r5, #66\]
+0+178 <[^>]+> 87e9      	strh	r1, \[r5, #62\]
+0+17a <[^>]+> f8a5 103e 	strh.w	r1, \[r5, #62\]
+0+17e <[^>]+> f825 1c3e 	strh.w	r1, \[r5, #-62\]
+0+182 <[^>]+> f825 1b3e 	strh.w	r1, \[r5\], #62
+0+186 <[^>]+> f825 1b3e 	strh.w	r1, \[r5\], #62
+0+18a <[^>]+> f825 1f3e 	strh.w	r1, \[r5, #62\]!
+0+18e <[^>]+> f825 1d3e 	strh.w	r1, \[r5, #-62\]!
+0+192 <[^>]+> 5329      	strh	r1, \[r5, r4\]
+0+194 <[^>]+> f829 100c 	strh.w	r1, \[r9, ip\]
+0+198 <[^>]+> f8af 1010 	strh.w	r1, \[pc, #16\]	; 0+1ac <[^>]+>
+0+19c <[^>]+> f8af 100c 	strh.w	r1, \[pc, #12\]	; 0+1ac <[^>]+>
+0+1a0 <[^>]+> f8af 8008 	strh.w	r8, \[pc, #8\]	; 0+1ac <[^>]+>
+0+1a4 <[^>]+> f8af 1006 	strh.w	r1, \[pc, #6\]	; 0+1ae <[^>]+>
+0+1a8 <[^>]+> f82f 103a 	strh.w	r1, \[pc, #-58\]	; 0+172 <[^>]+>
+0+1ac <[^>]+> bf00      	nop
+0+1ae <[^>]+> 6029      	str	r1, \[r5, #0\]
+0+1b0 <[^>]+> f8c5 1080 	str.w	r1, \[r5, #128\]
+0+1b4 <[^>]+> 67e9      	str	r1, \[r5, #124\]
+0+1b6 <[^>]+> f8c5 107c 	str.w	r1, \[r5, #124\]
+0+1ba <[^>]+> f845 1c7c 	str.w	r1, \[r5, #-124\]
+0+1be <[^>]+> f845 1b7c 	str.w	r1, \[r5\], #124
+0+1c2 <[^>]+> f845 1b7c 	str.w	r1, \[r5\], #124
+0+1c6 <[^>]+> f845 1f7c 	str.w	r1, \[r5, #124\]!
+0+1ca <[^>]+> f845 1d7c 	str.w	r1, \[r5, #-124\]!
+0+1ce <[^>]+> 5129      	str	r1, \[r5, r4\]
+0+1d0 <[^>]+> f849 100c 	str.w	r1, \[r9, ip\]
+0+1d4 <[^>]+> f8cf 1010 	str.w	r1, \[pc, #16\]	; 0+1e8 <[^>]+>
+0+1d8 <[^>]+> f8cf 100c 	str.w	r1, \[pc, #12\]	; 0+1e8 <[^>]+>
+0+1dc <[^>]+> f8cf 8008 	str.w	r8, \[pc, #8\]	; 0+1e8 <[^>]+>
+0+1e0 <[^>]+> f8cf 1006 	str.w	r1, \[pc, #6\]	; 0+1ea <[^>]+>
+0+1e4 <[^>]+> f84f 103a 	str.w	r1, \[pc, #-58\]	; 0+1ae <[^>]+>
+0+1e8 <[^>]+> bf00      	nop
+0+1ea <[^>]+> a104      	add	r1, pc, #16	\(adr r1,0+1fc <[^>]+>\)
+0+1ec <[^>]+> f20f 010c 	addw	r1, pc, #12	; 0xc
+0+1f0 <[^>]+> f20f 0808 	addw	r8, pc, #8	; 0x8
+0+1f4 <[^>]+> f20f 0106 	addw	r1, pc, #6	; 0x6
+0+1f8 <[^>]+> f2af 0112 	subw	r1, pc, #18	; 0x12
+0+1fc <[^>]+> bf00      	nop
+0+1fe <[^>]+> bf00      	nop
+0+200 <[^>]+> f20f 0104 	addw	r1, pc, #4	; 0x4
+0+204 <[^>]+> f20f 0102 	addw	r1, pc, #2	; 0x2
+0+208 <[^>]+> bf00      	nop
+0+20a <[^>]+> bf00      	nop
diff --git a/gas/testsuite/gas/arm/thumb2_relax.s b/gas/testsuite/gas/arm/thumb2_relax.s
new file mode 100644
index 0000000..428e6ff
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_relax.s
@@ -0,0 +1,62 @@
+	.text
+	.thumb
+	.syntax unified
+thumb2_relax:
+	.macro	ls op w=".w"
+1:
+	\op	r1, [r5]
+	\op	r1, [r5, #(far_\op + 4)]
+	\op	r1, [r5, #far_\op]
+	\op\w	r1, [r5, #far_\op]
+	\op	r1, [r5, #-far_\op]
+	\op	r1, [r5], #far_\op
+	\op	r1, [r5], #far_\op
+	\op	r1, [r5, #far_\op]!
+	\op	r1, [r5, #-far_\op]!
+	\op	r1, [r5, r4]
+	\op	r1, [r9, ip]
+	\op	r1, 1f
+	\op\w	r1, 1f
+	\op	r8, 1f
+	\op	r1, 2f
+	\op	r1, 1b
+	.align 2
+1:
+	nop
+2:
+	.endm
+.equ far_ldrb, 0x1f
+.equ far_ldrsb, 0x1f
+.equ far_ldrh, 0x3e
+.equ far_ldrsh, 0x3e
+.equ far_ldr, 0x7c
+.equ far_strb, 0x1f
+.equ far_strh, 0x3e
+.equ far_str, 0x7c
+	ls	ldrb
+	ls	ldrsb
+	ls	ldrh
+	ls	ldrsh
+	ls	ldr
+	ls	strb
+	ls	strh
+	ls	str
+	.purgem ls
+1:
+	adr	r1, 1f
+	adr.w	r1, 1f
+	adr	r8, 1f
+	adr	r1, 2f
+	adr	r1, 1b
+.align 2
+1:
+	nop
+2:
+	nop
+	@ Relaxation with conflicting alignment requirements.
+	adr	r1, 1f
+	adr	r1, 2f
+1:
+	nop
+2:
+	nop
diff --git a/gas/testsuite/gas/arm/thumb32.d b/gas/testsuite/gas/arm/thumb32.d
index 2fa28c8..f6883a3 100644
--- a/gas/testsuite/gas/arm/thumb32.d
+++ b/gas/testsuite/gas/arm/thumb32.d
@@ -7,1019 +7,940 @@
 .*: +file format .*arm.*
 
 Disassembly of section .text:
-0+000 <[^>]+> f041 0000 	orr\.w	r0, r1, #0	; 0x0
-0+004 <[^>]+> f041 00a5 	orr\.w	r0, r1, #165	; 0xa5
-0+008 <[^>]+> f041 10a5 	orr\.w	r0, r1, #10813605	; 0xa500a5
-0+00c <[^>]+> f041 20a5 	orr\.w	r0, r1, #2768282880	; 0xa500a500
-0+010 <[^>]+> f041 30a5 	orr\.w	r0, r1, #2779096485	; 0xa5a5a5a5
-0+014 <[^>]+> f041 4000 	orr\.w	r0, r1, #2147483648	; 0x80000000
-0+018 <[^>]+> f041 4080 	orr\.w	r0, r1, #1073741824	; 0x40000000
-0+01c <[^>]+> f041 4020 	orr\.w	r0, r1, #2684354560	; 0xa0000000
-0+020 <[^>]+> f041 40a0 	orr\.w	r0, r1, #1342177280	; 0x50000000
-0+024 <[^>]+> f041 5020 	orr\.w	r0, r1, #671088640	; 0x28000000
-0+028 <[^>]+> f041 4014 	orr\.w	r0, r1, #2483027968	; 0x94000000
-0+02c <[^>]+> f041 4094 	orr\.w	r0, r1, #1241513984	; 0x4a000000
-0+030 <[^>]+> f041 4025 	orr\.w	r0, r1, #2768240640	; 0xa5000000
-0+034 <[^>]+> f041 40a5 	orr\.w	r0, r1, #1384120320	; 0x52800000
-0+038 <[^>]+> f041 5025 	orr\.w	r0, r1, #692060160	; 0x29400000
-0+03c <[^>]+> f041 50a5 	orr\.w	r0, r1, #346030080	; 0x14a00000
-0+040 <[^>]+> f041 6025 	orr\.w	r0, r1, #173015040	; 0xa500000
-0+044 <[^>]+> f041 60a5 	orr\.w	r0, r1, #86507520	; 0x5280000
-0+048 <[^>]+> f041 7025 	orr\.w	r0, r1, #43253760	; 0x2940000
-0+04c <[^>]+> f041 70a5 	orr\.w	r0, r1, #21626880	; 0x14a0000
-0+050 <[^>]+> f441 0025 	orr\.w	r0, r1, #10813440	; 0xa50000
-0+054 <[^>]+> f441 00a5 	orr\.w	r0, r1, #5406720	; 0x528000
-0+058 <[^>]+> f441 1025 	orr\.w	r0, r1, #2703360	; 0x294000
-0+05c <[^>]+> f441 10a5 	orr\.w	r0, r1, #1351680	; 0x14a000
-0+060 <[^>]+> f441 2025 	orr\.w	r0, r1, #675840	; 0xa5000
-0+064 <[^>]+> f441 20a5 	orr\.w	r0, r1, #337920	; 0x52800
-0+068 <[^>]+> f441 3025 	orr\.w	r0, r1, #168960	; 0x29400
-0+06c <[^>]+> f441 30a5 	orr\.w	r0, r1, #84480	; 0x14a00
-0+070 <[^>]+> f441 4025 	orr\.w	r0, r1, #42240	; 0xa500
-0+074 <[^>]+> f441 40a5 	orr\.w	r0, r1, #21120	; 0x5280
-0+078 <[^>]+> f441 5025 	orr\.w	r0, r1, #10560	; 0x2940
-0+07c <[^>]+> f441 50a5 	orr\.w	r0, r1, #5280	; 0x14a0
-0+080 <[^>]+> f441 6025 	orr\.w	r0, r1, #2640	; 0xa50
-0+084 <[^>]+> f441 60a5 	orr\.w	r0, r1, #1320	; 0x528
-0+088 <[^>]+> f441 7025 	orr\.w	r0, r1, #660	; 0x294
-0+08c <[^>]+> f441 70a5 	orr\.w	r0, r1, #330	; 0x14a
-0+090 <[^>]+> f110 0000 	adds\.w	r0, r0, #0	; 0x0
-0+094 <[^>]+> f110 0500 	adds\.w	r5, r0, #0	; 0x0
-0+098 <[^>]+> f115 0000 	adds\.w	r0, r5, #0	; 0x0
-0+09c <[^>]+> f110 0005 	adds\.w	r0, r0, #5	; 0x5
-0+0a0 <[^>]+> f110 0081 	adds\.w	r0, r0, #129	; 0x81
-0+0a4 <[^>]+> f110 0081 	adds\.w	r0, r0, #129	; 0x81
-0+0a8 <[^>]+> f110 057e 	adds\.w	r5, r0, #126	; 0x7e
-0+0ac <[^>]+> 1800      	adds	r0, r0, r0
-0+0ae <[^>]+> 1805      	adds	r5, r0, r0
-0+0b0 <[^>]+> 1828      	adds	r0, r5, r0
-0+0b2 <[^>]+> 1940      	adds	r0, r0, r5
-0+0b4 <[^>]+> 18d1      	adds	r1, r2, r3
-0+0b6 <[^>]+> 4480      	add	r8, r0
-0+0b8 <[^>]+> 4440      	add	r0, r8
-0+0ba <[^>]+> 4440      	add	r0, r8
-0+0bc <[^>]+> 4440      	add	r0, r8
-0+0be <[^>]+> eb00 0800 	add\.w	r8, r0, r0
-0+0c2 <[^>]+> 4401      	add	r1, r0
-0+0c4 <[^>]+> 4408      	add	r0, r1
-0+0c6 <[^>]+> f10f 0000 	add\.w	r0, pc, #0	; 0x0
-0+0ca <[^>]+> f10f 0500 	add\.w	r5, pc, #0	; 0x0
-0+0ce <[^>]+> f50f 7001 	add\.w	r0, pc, #516	; 0x204
-0+0d2 <[^>]+> f10d 0000 	add\.w	r0, sp, #0	; 0x0
-0+0d6 <[^>]+> f10d 0500 	add\.w	r5, sp, #0	; 0x0
-0+0da <[^>]+> f50d 7001 	add\.w	r0, sp, #516	; 0x204
-0+0de <[^>]+> f100 0d00 	add\.w	sp, r0, #0	; 0x0
-0+0e2 <[^>]+> f10d 0d00 	add\.w	sp, sp, #0	; 0x0
-0+0e6 <[^>]+> f500 7d82 	add\.w	sp, r0, #260	; 0x104
-0+0ea <[^>]+> f100 0000 	add\.w	r0, r0, #0	; 0x0
-0+0ee <[^>]+> f110 0000 	adds\.w	r0, r0, #0	; 0x0
-0+0f2 <[^>]+> f100 0900 	add\.w	r9, r0, #0	; 0x0
-0+0f6 <[^>]+> f109 0000 	add\.w	r0, r9, #0	; 0x0
-0+0fa <[^>]+> f100 0081 	add\.w	r0, r0, #129	; 0x81
-0+0fe <[^>]+> eb00 0000 	add\.w	r0, r0, r0
-0+102 <[^>]+> eb10 0000 	adds\.w	r0, r0, r0
-0+106 <[^>]+> eb00 0900 	add\.w	r9, r0, r0
-0+10a <[^>]+> eb09 0000 	add\.w	r0, r9, r0
-0+10e <[^>]+> eb00 0009 	add\.w	r0, r0, r9
-0+112 <[^>]+> eb09 080a 	add\.w	r8, r9, sl
-0+116 <[^>]+> eb09 484a 	add\.w	r8, r9, sl, lsl #17
-0+11a <[^>]+> eb08 081a 	add\.w	r8, r8, sl, lsr #32
-0+11e <[^>]+> eb08 485a 	add\.w	r8, r8, sl, lsr #17
-0+122 <[^>]+> eb09 082a 	add\.w	r8, r9, sl, asr #32
-0+126 <[^>]+> eb09 486a 	add\.w	r8, r9, sl, asr #17
-0+12a <[^>]+> eb09 083a 	add\.w	r8, r9, sl, rrx
-0+12e <[^>]+> eb09 487a 	add\.w	r8, r9, sl, ror #17
-0+132 <[^>]+> f1b0 0000 	subs\.w	r0, r0, #0	; 0x0
-0+136 <[^>]+> f1b0 0500 	subs\.w	r5, r0, #0	; 0x0
-0+13a <[^>]+> f1b5 0000 	subs\.w	r0, r5, #0	; 0x0
-0+13e <[^>]+> f1b0 0005 	subs\.w	r0, r0, #5	; 0x5
-0+142 <[^>]+> f1b0 0081 	subs\.w	r0, r0, #129	; 0x81
-0+146 <[^>]+> f1b0 0508 	subs\.w	r5, r0, #8	; 0x8
-0+14a <[^>]+> 1a00      	subs	r0, r0, r0
-0+14c <[^>]+> 1a05      	subs	r5, r0, r0
-0+14e <[^>]+> 1a28      	subs	r0, r5, r0
-0+150 <[^>]+> 1b40      	subs	r0, r0, r5
-0+152 <[^>]+> f5a0 7d82 	sub\.w	sp, r0, #260	; 0x104
-0+156 <[^>]+> f5ad 7d82 	sub\.w	sp, sp, #260	; 0x104
-0+15a <[^>]+> ebb8 0800 	subs\.w	r8, r8, r0
-0+15e <[^>]+> ebb0 0008 	subs\.w	r0, r0, r8
-0+162 <[^>]+> f5b0 7082 	subs\.w	r0, r0, #260	; 0x104
-0+166 <[^>]+> 4140      	adcs	r0, r0
-0+168 <[^>]+> 4145      	adcs	r5, r0
-0+16a <[^>]+> 4168      	adcs	r0, r5
-0+16c <[^>]+> 4168      	adcs	r0, r5
-0+16e <[^>]+> 4168      	adcs	r0, r5
-0+170 <[^>]+> eb45 0000 	adc\.w	r0, r5, r0
-0+174 <[^>]+> eb41 0002 	adc\.w	r0, r1, r2
-0+178 <[^>]+> eb40 0900 	adc\.w	r9, r0, r0
-0+17c <[^>]+> eb49 0000 	adc\.w	r0, r9, r0
-0+180 <[^>]+> eb40 0009 	adc\.w	r0, r0, r9
-0+184 <[^>]+> eb50 0000 	adcs\.w	r0, r0, r0
-0+188 <[^>]+> eb41 4062 	adc\.w	r0, r1, r2, asr #17
-0+18c <[^>]+> f141 0081 	adc\.w	r0, r1, #129	; 0x81
-0+190 <[^>]+> 4000      	ands	r0, r0
-0+192 <[^>]+> 4005      	ands	r5, r0
-0+194 <[^>]+> 4028      	ands	r0, r5
-0+196 <[^>]+> 4028      	ands	r0, r5
-0+198 <[^>]+> 4028      	ands	r0, r5
-0+19a <[^>]+> ea05 0000 	and\.w	r0, r5, r0
-0+19e <[^>]+> ea01 0002 	and\.w	r0, r1, r2
-0+1a2 <[^>]+> ea00 0900 	and\.w	r9, r0, r0
-0+1a6 <[^>]+> ea09 0000 	and\.w	r0, r9, r0
-0+1aa <[^>]+> ea00 0009 	and\.w	r0, r0, r9
-0+1ae <[^>]+> ea10 0000 	ands\.w	r0, r0, r0
-0+1b2 <[^>]+> ea01 4062 	and\.w	r0, r1, r2, asr #17
-0+1b6 <[^>]+> f001 0081 	and\.w	r0, r1, #129	; 0x81
-0+1ba <[^>]+> 4380      	bics	r0, r0
-0+1bc <[^>]+> 4385      	bics	r5, r0
-0+1be <[^>]+> 43a8      	bics	r0, r5
-0+1c0 <[^>]+> 43a8      	bics	r0, r5
-0+1c2 <[^>]+> ea35 0000 	bics\.w	r0, r5, r0
-0+1c6 <[^>]+> ea25 0000 	bic\.w	r0, r5, r0
-0+1ca <[^>]+> ea21 0002 	bic\.w	r0, r1, r2
-0+1ce <[^>]+> ea20 0900 	bic\.w	r9, r0, r0
-0+1d2 <[^>]+> ea29 0000 	bic\.w	r0, r9, r0
-0+1d6 <[^>]+> ea20 0009 	bic\.w	r0, r0, r9
-0+1da <[^>]+> ea30 0000 	bics\.w	r0, r0, r0
-0+1de <[^>]+> ea21 4062 	bic\.w	r0, r1, r2, asr #17
-0+1e2 <[^>]+> f021 0081 	bic\.w	r0, r1, #129	; 0x81
-0+1e6 <[^>]+> 4040      	eors	r0, r0
-0+1e8 <[^>]+> 4045      	eors	r5, r0
-0+1ea <[^>]+> 4068      	eors	r0, r5
-0+1ec <[^>]+> 4068      	eors	r0, r5
-0+1ee <[^>]+> 4068      	eors	r0, r5
-0+1f0 <[^>]+> ea85 0000 	eor\.w	r0, r5, r0
-0+1f4 <[^>]+> ea81 0002 	eor\.w	r0, r1, r2
-0+1f8 <[^>]+> ea80 0900 	eor\.w	r9, r0, r0
-0+1fc <[^>]+> ea89 0000 	eor\.w	r0, r9, r0
-0+200 <[^>]+> ea80 0009 	eor\.w	r0, r0, r9
-0+204 <[^>]+> ea90 0000 	eors\.w	r0, r0, r0
-0+208 <[^>]+> ea81 4062 	eor\.w	r0, r1, r2, asr #17
-0+20c <[^>]+> f081 0081 	eor\.w	r0, r1, #129	; 0x81
-0+210 <[^>]+> 4300      	orrs	r0, r0
-0+212 <[^>]+> 4305      	orrs	r5, r0
-0+214 <[^>]+> 4328      	orrs	r0, r5
-0+216 <[^>]+> 4328      	orrs	r0, r5
-0+218 <[^>]+> 4328      	orrs	r0, r5
-0+21a <[^>]+> ea45 0000 	orr\.w	r0, r5, r0
-0+21e <[^>]+> ea41 0002 	orr\.w	r0, r1, r2
-0+222 <[^>]+> ea40 0900 	orr\.w	r9, r0, r0
-0+226 <[^>]+> ea49 0000 	orr\.w	r0, r9, r0
-0+22a <[^>]+> ea40 0009 	orr\.w	r0, r0, r9
-0+22e <[^>]+> ea50 0000 	orrs\.w	r0, r0, r0
-0+232 <[^>]+> ea41 4062 	orr\.w	r0, r1, r2, asr #17
-0+236 <[^>]+> f041 0081 	orr\.w	r0, r1, #129	; 0x81
-0+23a <[^>]+> ebd0 0000 	rsbs	r0, r0, r0
-0+23e <[^>]+> ebd5 0500 	rsbs	r5, r5, r0
-0+242 <[^>]+> ebd0 0005 	rsbs	r0, r0, r5
-0+246 <[^>]+> ebd0 0005 	rsbs	r0, r0, r5
-0+24a <[^>]+> ebd5 0000 	rsbs	r0, r5, r0
-0+24e <[^>]+> ebc5 0000 	rsb	r0, r5, r0
-0+252 <[^>]+> ebc1 0002 	rsb	r0, r1, r2
-0+256 <[^>]+> ebc0 0900 	rsb	r9, r0, r0
-0+25a <[^>]+> ebc9 0000 	rsb	r0, r9, r0
-0+25e <[^>]+> ebc0 0009 	rsb	r0, r0, r9
-0+262 <[^>]+> ebd0 0000 	rsbs	r0, r0, r0
-0+266 <[^>]+> ebc1 4062 	rsb	r0, r1, r2, asr #17
-0+26a <[^>]+> f1c1 0081 	rsb	r0, r1, #129	; 0x81
-0+26e <[^>]+> 4180      	sbcs	r0, r0
-0+270 <[^>]+> 4185      	sbcs	r5, r0
-0+272 <[^>]+> 41a8      	sbcs	r0, r5
-0+274 <[^>]+> 41a8      	sbcs	r0, r5
-0+276 <[^>]+> eb75 0000 	sbcs\.w	r0, r5, r0
-0+27a <[^>]+> eb65 0000 	sbc\.w	r0, r5, r0
-0+27e <[^>]+> eb61 0002 	sbc\.w	r0, r1, r2
-0+282 <[^>]+> eb60 0900 	sbc\.w	r9, r0, r0
-0+286 <[^>]+> eb69 0000 	sbc\.w	r0, r9, r0
-0+28a <[^>]+> eb60 0009 	sbc\.w	r0, r0, r9
-0+28e <[^>]+> eb70 0000 	sbcs\.w	r0, r0, r0
-0+292 <[^>]+> eb61 4062 	sbc\.w	r0, r1, r2, asr #17
-0+296 <[^>]+> f161 0081 	sbc\.w	r0, r1, #129	; 0x81
-0+29a <[^>]+> f36f 0000 	bfc	r0, #0, #1
-0+29e <[^>]+> f36f 0900 	bfc	r9, #0, #1
-0+2a2 <[^>]+> f36f 0900 	bfc	r9, #0, #1
-0+2a6 <[^>]+> f36f 5055 	bfc	r0, #21, #1
-0+2aa <[^>]+> f36f 0011 	bfc	r0, #0, #18
-0+2ae <[^>]+> f360 0000 	bfi	r0, r0, #0, #1
-0+2b2 <[^>]+> f360 0900 	bfi	r9, r0, #0, #1
-0+2b6 <[^>]+> f369 0000 	bfi	r0, r9, #0, #1
-0+2ba <[^>]+> f360 5055 	bfi	r0, r0, #21, #1
-0+2be <[^>]+> f360 0011 	bfi	r0, r0, #0, #18
-0+2c2 <[^>]+> f340 0000 	sbfx	r0, r0, #0, #1
-0+2c6 <[^>]+> f3c0 0900 	ubfx	r9, r0, #0, #1
-0+2ca <[^>]+> f349 0000 	sbfx	r0, r9, #0, #1
-0+2ce <[^>]+> f3c0 5040 	ubfx	r0, r0, #21, #1
-0+2d2 <[^>]+> f340 0011 	sbfx	r0, r0, #0, #18
-0+2d6 <[^>]+> d0fe      	beq\.n	0+2d6 <[^>]+>
-0+2d8 <[^>]+> d02a      	beq\.n	0+330 <[^>]+>
-0+2da <[^>]+> d1fc      	bne\.n	0+2d6 <[^>]+>
-0+2dc <[^>]+> d128      	bne\.n	0+330 <[^>]+>
-0+2de <[^>]+> d2fa      	bcs\.n	0+2d6 <[^>]+>
-0+2e0 <[^>]+> d226      	bcs\.n	0+330 <[^>]+>
-0+2e2 <[^>]+> d2f8      	bcs\.n	0+2d6 <[^>]+>
-0+2e4 <[^>]+> d224      	bcs\.n	0+330 <[^>]+>
-0+2e6 <[^>]+> d3f6      	bcc\.n	0+2d6 <[^>]+>
-0+2e8 <[^>]+> d322      	bcc\.n	0+330 <[^>]+>
-0+2ea <[^>]+> d3f4      	bcc\.n	0+2d6 <[^>]+>
-0+2ec <[^>]+> d320      	bcc\.n	0+330 <[^>]+>
-0+2ee <[^>]+> d3f2      	bcc\.n	0+2d6 <[^>]+>
-0+2f0 <[^>]+> d31e      	bcc\.n	0+330 <[^>]+>
-0+2f2 <[^>]+> d4f0      	bmi\.n	0+2d6 <[^>]+>
-0+2f4 <[^>]+> d41c      	bmi\.n	0+330 <[^>]+>
-0+2f6 <[^>]+> d5ee      	bpl\.n	0+2d6 <[^>]+>
-0+2f8 <[^>]+> d51a      	bpl\.n	0+330 <[^>]+>
-0+2fa <[^>]+> d6ec      	bvs\.n	0+2d6 <[^>]+>
-0+2fc <[^>]+> d618      	bvs\.n	0+330 <[^>]+>
-0+2fe <[^>]+> d7ea      	bvc\.n	0+2d6 <[^>]+>
-0+300 <[^>]+> d716      	bvc\.n	0+330 <[^>]+>
-0+302 <[^>]+> d8e8      	bhi\.n	0+2d6 <[^>]+>
-0+304 <[^>]+> d814      	bhi\.n	0+330 <[^>]+>
-0+306 <[^>]+> d9e6      	bls\.n	0+2d6 <[^>]+>
-0+308 <[^>]+> d912      	bls\.n	0+330 <[^>]+>
-0+30a <[^>]+> d7e4      	bvc\.n	0+2d6 <[^>]+>
-0+30c <[^>]+> d710      	bvc\.n	0+330 <[^>]+>
-0+30e <[^>]+> d8e2      	bhi\.n	0+2d6 <[^>]+>
-0+310 <[^>]+> d80e      	bhi\.n	0+330 <[^>]+>
-0+312 <[^>]+> d9e0      	bls\.n	0+2d6 <[^>]+>
-0+314 <[^>]+> d90c      	bls\.n	0+330 <[^>]+>
-0+316 <[^>]+> dade      	bge\.n	0+2d6 <[^>]+>
-0+318 <[^>]+> da0a      	bge\.n	0+330 <[^>]+>
-0+31a <[^>]+> dbdc      	blt\.n	0+2d6 <[^>]+>
-0+31c <[^>]+> db08      	blt\.n	0+330 <[^>]+>
-0+31e <[^>]+> dcda      	bgt\.n	0+2d6 <[^>]+>
-0+320 <[^>]+> dc06      	bgt\.n	0+330 <[^>]+>
-0+322 <[^>]+> ddd8      	ble\.n	0+2d6 <[^>]+>
-0+324 <[^>]+> dd04      	ble\.n	0+330 <[^>]+>
-0+326 <[^>]+> e7d6      	b\.n	0+2d6 <[^>]+>
-0+328 <[^>]+> e002      	b\.n	0+330 <[^>]+>
-0+32a <[^>]+> e7d4      	b\.n	0+2d6 <[^>]+>
-0+32c <[^>]+> e000      	b\.n	0+330 <[^>]+>
-0+32e <[^>]+> 46c0      	nop			\(mov r8, r8\)
-0+330 <[^>]+> f43f affe 	beq\.w	0+330 <[^>]+>
-0+334 <[^>]+> f000 8058 	beq\.w	0+3e8 <[^>]+>
-0+338 <[^>]+> f47f affa 	bne\.w	0+330 <[^>]+>
-0+33c <[^>]+> f040 8054 	bne\.w	0+3e8 <[^>]+>
-0+340 <[^>]+> f4bf aff6 	bcs\.w	0+330 <[^>]+>
-0+344 <[^>]+> f080 8050 	bcs\.w	0+3e8 <[^>]+>
-0+348 <[^>]+> f4bf aff2 	bcs\.w	0+330 <[^>]+>
-0+34c <[^>]+> f080 804c 	bcs\.w	0+3e8 <[^>]+>
-0+350 <[^>]+> f4ff afee 	bcc\.w	0+330 <[^>]+>
-0+354 <[^>]+> f0c0 8048 	bcc\.w	0+3e8 <[^>]+>
-0+358 <[^>]+> f4ff afea 	bcc\.w	0+330 <[^>]+>
-0+35c <[^>]+> f0c0 8044 	bcc\.w	0+3e8 <[^>]+>
-0+360 <[^>]+> f4ff afe6 	bcc\.w	0+330 <[^>]+>
-0+364 <[^>]+> f0c0 8040 	bcc\.w	0+3e8 <[^>]+>
-0+368 <[^>]+> f53f afe2 	bmi\.w	0+330 <[^>]+>
-0+36c <[^>]+> f100 803c 	bmi\.w	0+3e8 <[^>]+>
-0+370 <[^>]+> f57f afde 	bpl\.w	0+330 <[^>]+>
-0+374 <[^>]+> f140 8038 	bpl\.w	0+3e8 <[^>]+>
-0+378 <[^>]+> f5bf afda 	bvs\.w	0+330 <[^>]+>
-0+37c <[^>]+> f180 8034 	bvs\.w	0+3e8 <[^>]+>
-0+380 <[^>]+> f5ff afd6 	bvc\.w	0+330 <[^>]+>
-0+384 <[^>]+> f1c0 8030 	bvc\.w	0+3e8 <[^>]+>
-0+388 <[^>]+> f63f afd2 	bhi\.w	0+330 <[^>]+>
-0+38c <[^>]+> f200 802c 	bhi\.w	0+3e8 <[^>]+>
-0+390 <[^>]+> f67f afce 	bls\.w	0+330 <[^>]+>
-0+394 <[^>]+> f240 8028 	bls\.w	0+3e8 <[^>]+>
-0+398 <[^>]+> f5ff afca 	bvc\.w	0+330 <[^>]+>
-0+39c <[^>]+> f1c0 8024 	bvc\.w	0+3e8 <[^>]+>
-0+3a0 <[^>]+> f63f afc6 	bhi\.w	0+330 <[^>]+>
-0+3a4 <[^>]+> f200 8020 	bhi\.w	0+3e8 <[^>]+>
-0+3a8 <[^>]+> f67f afc2 	bls\.w	0+330 <[^>]+>
-0+3ac <[^>]+> f240 801c 	bls\.w	0+3e8 <[^>]+>
-0+3b0 <[^>]+> f6bf afbe 	bge\.w	0+330 <[^>]+>
-0+3b4 <[^>]+> f280 8018 	bge\.w	0+3e8 <[^>]+>
-0+3b8 <[^>]+> f6ff afba 	blt\.w	0+330 <[^>]+>
-0+3bc <[^>]+> f2c0 8014 	blt\.w	0+3e8 <[^>]+>
-0+3c0 <[^>]+> f73f afb6 	bgt\.w	0+330 <[^>]+>
-0+3c4 <[^>]+> f300 8010 	bgt\.w	0+3e8 <[^>]+>
-0+3c8 <[^>]+> f77f afb2 	ble\.w	0+330 <[^>]+>
-0+3cc <[^>]+> f340 800c 	ble\.w	0+3e8 <[^>]+>
-0+3d0 <[^>]+> f7ff bfae 	b\.w	0+330 <[^>]+>
-0+3d4 <[^>]+> f000 b808 	b\.w	0+3e8 <[^>]+>
-0+3d8 <[^>]+> f7ff ffaa 	bl	0+330 <[^>]+>
-0+3dc <[^>]+> f000 f804 	bl	0+3e8 <[^>]+>
-0+3e0 <[^>]+> f7ff efa6 	blx	0+330 <[^>]+>
-0+3e4 <[^>]+> f000 e800 	blx	0+3e8 <[^>]+>
-0+3e8 <[^>]+> 4748      	bx	r9
-0+3ea <[^>]+> 4780      	blx	r0
-0+3ec <[^>]+> 47c8      	blx	r9
-0+3ee <[^>]+> f3c0 8f00 	bxj	r0
-0+3f2 <[^>]+> f3c9 8f00 	bxj	r9
-0+3f6 <[^>]+> fab0 f080 	clz	r0, r0
-0+3fa <[^>]+> fab0 f980 	clz	r9, r0
-0+3fe <[^>]+> fab9 f089 	clz	r0, r9
-0+402 <[^>]+> b661      	cpsie	f
-0+404 <[^>]+> b672      	cpsid	i
-0+406 <[^>]+> b664      	cpsie	a
-0+408 <[^>]+> f3af 8620 	cpsid\.w	f
-0+40c <[^>]+> f3af 8440 	cpsie\.w	i
-0+410 <[^>]+> f3af 8680 	cpsid\.w	a
-0+414 <[^>]+> f3af 8540 	cpsie	i, #0
-0+418 <[^>]+> f3af 8751 	cpsid	i, #17
-0+41c <[^>]+> f3af 8100 	cps	#0
-0+420 <[^>]+> f3af 8111 	cps	#17
-0+424 <[^>]+> 4600      	mov	r0, r0
-0+426 <[^>]+> 4681      	mov	r9, r0
-0+428 <[^>]+> 4648      	mov	r0, r9
-0+42a <[^>]+> ea4f 0000 	mov\.w	r0, r0
-0+42e <[^>]+> ea4f 0900 	mov\.w	r9, r0
-0+432 <[^>]+> ea4f 0009 	mov\.w	r0, r9
-0+436 <[^>]+> b910      	cbnz	r0, 0+43e <[^>]+>
-0+438 <[^>]+> b105      	cbz	r5, 0+43c <[^>]+>
-0+43a <[^>]+> bf00      	nop
-0+43c <[^>]+> bf10      	yield
-0+43e <[^>]+> bf20      	wfe
-0+440 <[^>]+> bf30      	wfi
-0+442 <[^>]+> bf40      	sev
-0+444 <[^>]+> f3af 8000 	nop\.w
-0+448 <[^>]+> f3af 8001 	yield\.w
-0+44c <[^>]+> f3af 8002 	wfe\.w
-0+450 <[^>]+> f3af 8003 	wfi\.w
-0+454 <[^>]+> f3af 9004 	sev\.w
-0+458 <[^>]+> bf90      	nop	\{9\}
-0+45a <[^>]+> f3af 8081 	nop\.w	\{129\}
-0+45e <[^>]+> bf08      	it	eq
-0+460 <[^>]+> bf00      	nop
-0+462 <[^>]+> bf18      	it	ne
-0+464 <[^>]+> bf00      	nop
-0+466 <[^>]+> bf28      	it	cs
-0+468 <[^>]+> bf00      	nop
-0+46a <[^>]+> bf28      	it	cs
-0+46c <[^>]+> bf00      	nop
-0+46e <[^>]+> bf38      	it	cc
-0+470 <[^>]+> bf00      	nop
-0+472 <[^>]+> bf38      	it	cc
-0+474 <[^>]+> bf00      	nop
-0+476 <[^>]+> bf38      	it	cc
-0+478 <[^>]+> bf00      	nop
-0+47a <[^>]+> bf48      	it	mi
-0+47c <[^>]+> bf00      	nop
-0+47e <[^>]+> bf58      	it	pl
-0+480 <[^>]+> bf00      	nop
-0+482 <[^>]+> bf68      	it	vs
-0+484 <[^>]+> bf00      	nop
-0+486 <[^>]+> bf78      	it	vc
-0+488 <[^>]+> bf00      	nop
-0+48a <[^>]+> bf88      	it	hi
-0+48c <[^>]+> bf00      	nop
-0+48e <[^>]+> bfa8      	it	ge
-0+490 <[^>]+> bf00      	nop
-0+492 <[^>]+> bfb8      	it	lt
-0+494 <[^>]+> bf00      	nop
-0+496 <[^>]+> bfc8      	it	gt
-0+498 <[^>]+> bf00      	nop
-0+49a <[^>]+> bfd8      	it	le
-0+49c <[^>]+> bf00      	nop
-0+49e <[^>]+> bfe8      	it	al
-0+4a0 <[^>]+> bf00      	nop
-0+4a2 <[^>]+> bf04      	itt	eq
-0+4a4 <[^>]+> bf00      	nop
-0+4a6 <[^>]+> bf00      	nop
-0+4a8 <[^>]+> bf0c      	ite	eq
-0+4aa <[^>]+> bf00      	nop
-0+4ac <[^>]+> bf00      	nop
-0+4ae <[^>]+> bf02      	ittt	eq
-0+4b0 <[^>]+> bf00      	nop
-0+4b2 <[^>]+> bf00      	nop
-0+4b4 <[^>]+> bf00      	nop
-0+4b6 <[^>]+> bf0a      	itet	eq
-0+4b8 <[^>]+> bf00      	nop
-0+4ba <[^>]+> bf00      	nop
-0+4bc <[^>]+> bf00      	nop
-0+4be <[^>]+> bf06      	itte	eq
-0+4c0 <[^>]+> bf00      	nop
-0+4c2 <[^>]+> bf00      	nop
-0+4c4 <[^>]+> bf00      	nop
-0+4c6 <[^>]+> bf0e      	itee	eq
-0+4c8 <[^>]+> bf00      	nop
-0+4ca <[^>]+> bf00      	nop
-0+4cc <[^>]+> bf00      	nop
-0+4ce <[^>]+> bf01      	itttt	eq
-0+4d0 <[^>]+> bf00      	nop
-0+4d2 <[^>]+> bf00      	nop
-0+4d4 <[^>]+> bf00      	nop
-0+4d6 <[^>]+> bf00      	nop
-0+4d8 <[^>]+> bf09      	itett	eq
-0+4da <[^>]+> bf00      	nop
-0+4dc <[^>]+> bf00      	nop
-0+4de <[^>]+> bf00      	nop
-0+4e0 <[^>]+> bf00      	nop
-0+4e2 <[^>]+> bf05      	ittet	eq
-0+4e4 <[^>]+> bf00      	nop
-0+4e6 <[^>]+> bf00      	nop
-0+4e8 <[^>]+> bf00      	nop
-0+4ea <[^>]+> bf00      	nop
-0+4ec <[^>]+> bf03      	ittte	eq
-0+4ee <[^>]+> bf00      	nop
-0+4f0 <[^>]+> bf00      	nop
-0+4f2 <[^>]+> bf00      	nop
-0+4f4 <[^>]+> bf00      	nop
-0+4f6 <[^>]+> bf07      	ittee	eq
-0+4f8 <[^>]+> bf00      	nop
-0+4fa <[^>]+> bf00      	nop
-0+4fc <[^>]+> bf00      	nop
-0+4fe <[^>]+> bf00      	nop
-0+500 <[^>]+> bf0b      	itete	eq
-0+502 <[^>]+> bf00      	nop
-0+504 <[^>]+> bf00      	nop
-0+506 <[^>]+> bf00      	nop
-0+508 <[^>]+> bf00      	nop
-0+50a <[^>]+> bf0d      	iteet	eq
-0+50c <[^>]+> bf00      	nop
-0+50e <[^>]+> bf00      	nop
-0+510 <[^>]+> bf00      	nop
-0+512 <[^>]+> bf00      	nop
-0+514 <[^>]+> bf0f      	iteee	eq
-0+516 <[^>]+> bf00      	nop
-0+518 <[^>]+> bf00      	nop
-0+51a <[^>]+> bf00      	nop
-0+51c <[^>]+> bf00      	nop
-0+51e <[^>]+> bf1c      	itt	ne
-0+520 <[^>]+> bf00      	nop
-0+522 <[^>]+> bf00      	nop
-0+524 <[^>]+> bf14      	ite	ne
-0+526 <[^>]+> bf00      	nop
-0+528 <[^>]+> bf00      	nop
-0+52a <[^>]+> bf1e      	ittt	ne
-0+52c <[^>]+> bf00      	nop
-0+52e <[^>]+> bf00      	nop
-0+530 <[^>]+> bf00      	nop
-0+532 <[^>]+> bf16      	itet	ne
-0+534 <[^>]+> bf00      	nop
-0+536 <[^>]+> bf00      	nop
-0+538 <[^>]+> bf00      	nop
-0+53a <[^>]+> bf1a      	itte	ne
-0+53c <[^>]+> bf00      	nop
-0+53e <[^>]+> bf00      	nop
-0+540 <[^>]+> bf00      	nop
-0+542 <[^>]+> bf12      	itee	ne
-0+544 <[^>]+> bf00      	nop
-0+546 <[^>]+> bf00      	nop
-0+548 <[^>]+> bf00      	nop
-0+54a <[^>]+> bf1f      	itttt	ne
-0+54c <[^>]+> bf00      	nop
-0+54e <[^>]+> bf00      	nop
-0+550 <[^>]+> bf00      	nop
-0+552 <[^>]+> bf00      	nop
-0+554 <[^>]+> bf17      	itett	ne
-0+556 <[^>]+> bf00      	nop
-0+558 <[^>]+> bf00      	nop
-0+55a <[^>]+> bf00      	nop
-0+55c <[^>]+> bf00      	nop
-0+55e <[^>]+> bf1b      	ittet	ne
-0+560 <[^>]+> bf00      	nop
-0+562 <[^>]+> bf00      	nop
-0+564 <[^>]+> bf00      	nop
-0+566 <[^>]+> bf00      	nop
-0+568 <[^>]+> bf1d      	ittte	ne
-0+56a <[^>]+> bf00      	nop
-0+56c <[^>]+> bf00      	nop
-0+56e <[^>]+> bf00      	nop
-0+570 <[^>]+> bf00      	nop
-0+572 <[^>]+> bf19      	ittee	ne
-0+574 <[^>]+> bf00      	nop
-0+576 <[^>]+> bf00      	nop
-0+578 <[^>]+> bf00      	nop
-0+57a <[^>]+> bf00      	nop
-0+57c <[^>]+> bf15      	itete	ne
-0+57e <[^>]+> bf00      	nop
-0+580 <[^>]+> bf00      	nop
-0+582 <[^>]+> bf00      	nop
-0+584 <[^>]+> bf00      	nop
-0+586 <[^>]+> bf13      	iteet	ne
-0+588 <[^>]+> bf00      	nop
-0+58a <[^>]+> bf00      	nop
-0+58c <[^>]+> bf00      	nop
-0+58e <[^>]+> bf00      	nop
-0+590 <[^>]+> bf11      	iteee	ne
-0+592 <[^>]+> bf00      	nop
-0+594 <[^>]+> bf00      	nop
-0+596 <[^>]+> bf00      	nop
-0+598 <[^>]+> bf00      	nop
-0+59a <[^>]+> f895 1000 	ldrb\.w	r1, \[r5\]
-0+59e <[^>]+> f895 1330 	ldrb\.w	r1, \[r5, #816\]
-0+5a2 <[^>]+> f815 1c30 	ldrb\.w	r1, \[r5, #-48\]
-0+5a6 <[^>]+> f815 1b30 	ldrb\.w	r1, \[r5\], #48
-0+5aa <[^>]+> f815 1930 	ldrb\.w	r1, \[r5\], #-48
-0+5ae <[^>]+> f815 1f30 	ldrb\.w	r1, \[r5, #48\]!
-0+5b2 <[^>]+> f815 1d30 	ldrb\.w	r1, \[r5, #-48\]!
-0+5b6 <[^>]+> 5d29      	ldrb	r1, \[r5, r4\]
-0+5b8 <[^>]+> f819 100c 	ldrb\.w	r1, \[r9, ip\]
-0+5bc <[^>]+> f89f 10ac 	ldrb\.w	r1, \[pc, #172\]	; 0+66c <[^>]+>
-0+5c0 <[^>]+> f81f 102a 	ldrb\.w	r1, \[pc, #-42\]	; 0+59a <[^>]+>
-0+5c4 <[^>]+> f995 1000 	ldrsb\.w	r1, \[r5\]
-0+5c8 <[^>]+> f995 1330 	ldrsb\.w	r1, \[r5, #816\]
-0+5cc <[^>]+> f915 1c30 	ldrsb\.w	r1, \[r5, #-48\]
-0+5d0 <[^>]+> f915 1b30 	ldrsb\.w	r1, \[r5\], #48
-0+5d4 <[^>]+> f915 1930 	ldrsb\.w	r1, \[r5\], #-48
-0+5d8 <[^>]+> f915 1f30 	ldrsb\.w	r1, \[r5, #48\]!
-0+5dc <[^>]+> f915 1d30 	ldrsb\.w	r1, \[r5, #-48\]!
-0+5e0 <[^>]+> 5729      	ldrsb	r1, \[r5, r4\]
-0+5e2 <[^>]+> f919 100c 	ldrsb\.w	r1, \[r9, ip\]
-0+5e6 <[^>]+> f99f 1084 	ldrsb\.w	r1, \[pc, #132\]	; 0+66c <[^>]+>
-0+5ea <[^>]+> f91f 1052 	ldrsb\.w	r1, \[pc, #-82\]	; 0+59a <[^>]+>
-0+5ee <[^>]+> f8b5 1000 	ldrh\.w	r1, \[r5\]
-0+5f2 <[^>]+> f8b5 1330 	ldrh\.w	r1, \[r5, #816\]
-0+5f6 <[^>]+> f835 1c30 	ldrh\.w	r1, \[r5, #-48\]
-0+5fa <[^>]+> f835 1b30 	ldrh\.w	r1, \[r5\], #48
-0+5fe <[^>]+> f835 1930 	ldrh\.w	r1, \[r5\], #-48
-0+602 <[^>]+> f835 1f30 	ldrh\.w	r1, \[r5, #48\]!
-0+606 <[^>]+> f835 1d30 	ldrh\.w	r1, \[r5, #-48\]!
-0+60a <[^>]+> 5b29      	ldrh	r1, \[r5, r4\]
-0+60c <[^>]+> f839 100c 	ldrh\.w	r1, \[r9, ip\]
-0+610 <[^>]+> f8bf 1058 	ldrh\.w	r1, \[pc, #88\]	; 0+66c <[^>]+>
-0+614 <[^>]+> f83f 107e 	ldrh\.w	r1, \[pc, #-126\]	; 0+59a <[^>]+>
-0+618 <[^>]+> f9b5 1000 	ldrsh\.w	r1, \[r5\]
-0+61c <[^>]+> f9b5 1330 	ldrsh\.w	r1, \[r5, #816\]
-0+620 <[^>]+> f935 1c30 	ldrsh\.w	r1, \[r5, #-48\]
-0+624 <[^>]+> f935 1b30 	ldrsh\.w	r1, \[r5\], #48
-0+628 <[^>]+> f935 1930 	ldrsh\.w	r1, \[r5\], #-48
-0+62c <[^>]+> f935 1f30 	ldrsh\.w	r1, \[r5, #48\]!
-0+630 <[^>]+> f935 1d30 	ldrsh\.w	r1, \[r5, #-48\]!
-0+634 <[^>]+> 5f29      	ldrsh	r1, \[r5, r4\]
-0+636 <[^>]+> f939 100c 	ldrsh\.w	r1, \[r9, ip\]
-0+63a <[^>]+> f9bf 1030 	ldrsh\.w	r1, \[pc, #48\]	; 0+66c <[^>]+>
-0+63e <[^>]+> f93f 10a6 	ldrsh\.w	r1, \[pc, #-166\]	; 0+59a <[^>]+>
-0+642 <[^>]+> f8d5 1000 	ldr\.w	r1, \[r5\]
-0+646 <[^>]+> f8d5 1330 	ldr\.w	r1, \[r5, #816\]
-0+64a <[^>]+> f855 1c30 	ldr\.w	r1, \[r5, #-48\]
-0+64e <[^>]+> f855 1b30 	ldr\.w	r1, \[r5\], #48
-0+652 <[^>]+> f855 1930 	ldr\.w	r1, \[r5\], #-48
-0+656 <[^>]+> f855 1f30 	ldr\.w	r1, \[r5, #48\]!
-0+65a <[^>]+> f855 1d30 	ldr\.w	r1, \[r5, #-48\]!
-0+65e <[^>]+> 5929      	ldr	r1, \[r5, r4\]
-0+660 <[^>]+> f859 100c 	ldr\.w	r1, \[r9, ip\]
-0+664 <[^>]+> f8df 1004 	ldr\.w	r1, \[pc, #4\]	; 0+66c <[^>]+>
-0+668 <[^>]+> f85f 10d2 	ldr\.w	r1, \[pc, #-210\]	; 0+59a <[^>]+>
-0+66c <[^>]+> f885 1000 	strb\.w	r1, \[r5\]
-0+670 <[^>]+> f885 1330 	strb\.w	r1, \[r5, #816\]
-0+674 <[^>]+> f805 1c30 	strb\.w	r1, \[r5, #-48\]
-0+678 <[^>]+> f805 1b30 	strb\.w	r1, \[r5\], #48
-0+67c <[^>]+> f805 1930 	strb\.w	r1, \[r5\], #-48
-0+680 <[^>]+> f805 1f30 	strb\.w	r1, \[r5, #48\]!
-0+684 <[^>]+> f805 1d30 	strb\.w	r1, \[r5, #-48\]!
-0+688 <[^>]+> 5529      	strb	r1, \[r5, r4\]
-0+68a <[^>]+> f809 100c 	strb\.w	r1, \[r9, ip\]
-0+68e <[^>]+> f88f 1086 	strb\.w	r1, \[pc, #134\]	; 0+716 <[^>]+>
-0+692 <[^>]+> f80f 1028 	strb\.w	r1, \[pc, #-40\]	; 0+66c <[^>]+>
-0+696 <[^>]+> f8a5 1000 	strh\.w	r1, \[r5\]
-0+69a <[^>]+> f8a5 1330 	strh\.w	r1, \[r5, #816\]
-0+69e <[^>]+> f825 1c30 	strh\.w	r1, \[r5, #-48\]
-0+6a2 <[^>]+> f825 1b30 	strh\.w	r1, \[r5\], #48
-0+6a6 <[^>]+> f825 1930 	strh\.w	r1, \[r5\], #-48
-0+6aa <[^>]+> f825 1f30 	strh\.w	r1, \[r5, #48\]!
-0+6ae <[^>]+> f825 1d30 	strh\.w	r1, \[r5, #-48\]!
-0+6b2 <[^>]+> 5329      	strh	r1, \[r5, r4\]
-0+6b4 <[^>]+> f829 100c 	strh\.w	r1, \[r9, ip\]
-0+6b8 <[^>]+> f8af 105a 	strh\.w	r1, \[pc, #90\]	; 0+716 <[^>]+>
-0+6bc <[^>]+> f82f 1054 	strh\.w	r1, \[pc, #-84\]	; 0+66c <[^>]+>
-0+6c0 <[^>]+> f8c5 1000 	str\.w	r1, \[r5\]
-0+6c4 <[^>]+> f8c5 1330 	str\.w	r1, \[r5, #816\]
-0+6c8 <[^>]+> f845 1c30 	str\.w	r1, \[r5, #-48\]
-0+6cc <[^>]+> f845 1b30 	str\.w	r1, \[r5\], #48
-0+6d0 <[^>]+> f845 1930 	str\.w	r1, \[r5\], #-48
-0+6d4 <[^>]+> f845 1f30 	str\.w	r1, \[r5, #48\]!
-0+6d8 <[^>]+> f845 1d30 	str\.w	r1, \[r5, #-48\]!
-0+6dc <[^>]+> 5129      	str	r1, \[r5, r4\]
-0+6de <[^>]+> f849 100c 	str\.w	r1, \[r9, ip\]
-0+6e2 <[^>]+> f8cf 1032 	str\.w	r1, \[pc, #50\]	; 0+716 <[^>]+>
-0+6e6 <[^>]+> f84f 107c 	str\.w	r1, \[pc, #-124\]	; 0+66c <[^>]+>
-0+6ea <[^>]+> f895 f000 	pld	\[r5\]
-0+6ee <[^>]+> f895 f330 	pld	\[r5, #816\]
-0+6f2 <[^>]+> f815 fc30 	pld	\[r5, #-48\]
-0+6f6 <[^>]+> f815 fb30 	pld	\[r5\], #48
-0+6fa <[^>]+> f815 f930 	pld	\[r5\], #-48
-0+6fe <[^>]+> f815 ff30 	pld	\[r5, #48\]!
-0+702 <[^>]+> f815 fd30 	pld	\[r5, #-48\]!
-0+706 <[^>]+> f815 f000 	pld	\[r5, r0\]
-0+70a <[^>]+> f819 f000 	pld	\[r9, r0\]
-0+70e <[^>]+> f89f f006 	pld	\[pc, #6\]	; 0+716 <[^>]+>
-0+712 <[^>]+> f81f f0a8 	pld	\[pc, #-168\]	; 0+66c <[^>]+>
-0+716 <[^>]+> e9d5 2300 	ldrd	r2, r3, \[r5\]
-0+71a <[^>]+> e9d5 230c 	ldrd	r2, r3, \[r5, #48\]
-0+71e <[^>]+> e955 230c 	ldrd	r2, r3, \[r5, #-48\]
-0+722 <[^>]+> e9c5 2300 	strd	r2, r3, \[r5\]
-0+726 <[^>]+> e9c5 230c 	strd	r2, r3, \[r5, #48\]
-0+72a <[^>]+> e945 230c 	strd	r2, r3, \[r5, #-48\]
-0+72e <[^>]+> f835 1e00 	ldrht	r1, \[r5\]
-0+732 <[^>]+> f835 1e30 	ldrht	r1, \[r5, #48\]
-0+736 <[^>]+> f915 1e00 	ldrsbt	r1, \[r5\]
-0+73a <[^>]+> f915 1e30 	ldrsbt	r1, \[r5, #48\]
-0+73e <[^>]+> f835 1e00 	ldrht	r1, \[r5\]
-0+742 <[^>]+> f835 1e30 	ldrht	r1, \[r5, #48\]
-0+746 <[^>]+> f935 1e00 	ldrsht	r1, \[r5\]
-0+74a <[^>]+> f935 1e30 	ldrsht	r1, \[r5, #48\]
-0+74e <[^>]+> f855 1e00 	ldrt	r1, \[r5\]
-0+752 <[^>]+> f855 1e30 	ldrt	r1, \[r5, #48\]
-0+756 <[^>]+> e8d4 1f4f 	ldrexb	r1, \[r4\]
-0+75a <[^>]+> e8d4 1f5f 	ldrexh	r1, \[r4\]
-0+75e <[^>]+> e854 1f00 	ldrex	r1, \[r4\]
-0+762 <[^>]+> e8d4 127f 	ldrexd	r1, r2, \[r4\]
-0+766 <[^>]+> e8c4 2f41 	strexb	r1, r2, \[r4\]
-0+76a <[^>]+> e8c4 2f51 	strexh	r1, r2, \[r4\]
-0+76e <[^>]+> e844 2100 	strex	r1, r2, \[r4\]
-0+772 <[^>]+> e8c4 2371 	strexd	r1, r2, r3, \[r4\]
-0+776 <[^>]+> e854 1f81 	ldrex	r1, \[r4, #516\]
-0+77a <[^>]+> e844 2181 	strex	r1, r2, \[r4, #516\]
-0+77e <[^>]+> c80e      	ldmia	r0!, \{r1, r2, r3\}
-0+780 <[^>]+> ca07      	ldmia	r2!, \{r0, r1, r2\}
-0+782 <[^>]+> e892 0007 	ldmia\.w	r2, \{r0, r1, r2\}
-0+786 <[^>]+> e899 0007 	ldmia\.w	r9, \{r0, r1, r2\}
-0+78a <[^>]+> e890 0580 	ldmia\.w	r0, \{r7, r8, sl\}
-0+78e <[^>]+> e8b0 0580 	ldmia\.w	r0!, \{r7, r8, sl\}
-0+792 <[^>]+> c00e      	stmia	r0!, \{r1, r2, r3\}
-0+794 <[^>]+> c20b      	stmia	r2!, \{r0, r1, r3\}
-0+796 <[^>]+> e8a2 000b 	stmia\.w	r2!, \{r0, r1, r3\}
-0+79a <[^>]+> e889 0007 	stmia\.w	r9, \{r0, r1, r2\}
-0+79e <[^>]+> e880 0580 	stmia\.w	r0, \{r7, r8, sl\}
-0+7a2 <[^>]+> e8a0 0580 	stmia\.w	r0!, \{r7, r8, sl\}
-0+7a6 <[^>]+> e910 0580 	ldmdb	r0, \{r7, r8, sl\}
-0+7aa <[^>]+> e900 0580 	stmdb	r0, \{r7, r8, sl\}
-0+7ae <[^>]+> fb00 0000 	mla	r0, r0, r0, r0
-0+7b2 <[^>]+> fb00 0010 	mls	r0, r0, r0, r0
-0+7b6 <[^>]+> fb00 0900 	mla	r9, r0, r0, r0
-0+7ba <[^>]+> fb09 0000 	mla	r0, r9, r0, r0
-0+7be <[^>]+> fb00 0009 	mla	r0, r0, r9, r0
-0+7c2 <[^>]+> fb00 9000 	mla	r0, r0, r0, r9
-0+7c6 <[^>]+> 4200      	tst	r0, r0
-0+7c8 <[^>]+> 4200      	tst	r0, r0
-0+7ca <[^>]+> 4205      	tst	r5, r0
-0+7cc <[^>]+> 4228      	tst	r0, r5
-0+7ce <[^>]+> ea10 4f65 	tst\.w	r0, r5, asr #17
-0+7d2 <[^>]+> ea10 0f00 	tst\.w	r0, r0
-0+7d6 <[^>]+> ea19 0f00 	tst\.w	r9, r0
-0+7da <[^>]+> ea10 0f09 	tst\.w	r0, r9
-0+7de <[^>]+> f010 0f81 	tst\.w	r0, #129	; 0x81
-0+7e2 <[^>]+> f015 0f81 	tst\.w	r5, #129	; 0x81
-0+7e6 <[^>]+> ea90 0f00 	teq	r0, r0
-0+7ea <[^>]+> ea90 0f00 	teq	r0, r0
-0+7ee <[^>]+> ea95 0f00 	teq	r5, r0
-0+7f2 <[^>]+> ea90 0f05 	teq	r0, r5
-0+7f6 <[^>]+> ea90 4f65 	teq	r0, r5, asr #17
-0+7fa <[^>]+> ea90 0f00 	teq	r0, r0
-0+7fe <[^>]+> ea99 0f00 	teq	r9, r0
-0+802 <[^>]+> ea90 0f09 	teq	r0, r9
-0+806 <[^>]+> f090 0f81 	teq	r0, #129	; 0x81
-0+80a <[^>]+> f095 0f81 	teq	r5, #129	; 0x81
-0+80e <[^>]+> 4280      	cmp	r0, r0
-0+810 <[^>]+> 4280      	cmp	r0, r0
-0+812 <[^>]+> 4285      	cmp	r5, r0
-0+814 <[^>]+> 42a8      	cmp	r0, r5
-0+816 <[^>]+> ebb0 4f65 	cmp\.w	r0, r5, asr #17
-0+81a <[^>]+> ebb0 0f00 	cmp\.w	r0, r0
-0+81e <[^>]+> 4581      	cmp	r9, r0
-0+820 <[^>]+> ebb0 0f09 	cmp\.w	r0, r9
-0+824 <[^>]+> f1b0 0f81 	cmp\.w	r0, #129	; 0x81
-0+828 <[^>]+> f1b5 0f81 	cmp\.w	r5, #129	; 0x81
-0+82c <[^>]+> 42c0      	cmn	r0, r0
-0+82e <[^>]+> 42c0      	cmn	r0, r0
-0+830 <[^>]+> 42c5      	cmn	r5, r0
-0+832 <[^>]+> 42e8      	cmn	r0, r5
-0+834 <[^>]+> eb10 4f65 	cmn\.w	r0, r5, asr #17
-0+838 <[^>]+> eb10 0f00 	cmn\.w	r0, r0
-0+83c <[^>]+> eb19 0f00 	cmn\.w	r9, r0
-0+840 <[^>]+> eb10 0f09 	cmn\.w	r0, r9
-0+844 <[^>]+> f110 0f81 	cmn\.w	r0, #129	; 0x81
-0+848 <[^>]+> f115 0f81 	cmn\.w	r5, #129	; 0x81
-0+84c <[^>]+> 1c00      	adds	r0, r0, #0
-0+84e <[^>]+> 4600      	mov	r0, r0
-0+850 <[^>]+> 1c05      	adds	r5, r0, #0
-0+852 <[^>]+> 4628      	mov	r0, r5
-0+854 <[^>]+> ea4f 4065 	mov\.w	r0, r5, asr #17
-0+858 <[^>]+> ea4f 0000 	mov\.w	r0, r0
-0+85c <[^>]+> ea5f 0900 	movs\.w	r9, r0
-0+860 <[^>]+> ea5f 0009 	movs\.w	r0, r9
-0+864 <[^>]+> f04f 0081 	mov\.w	r0, #129	; 0x81
-0+868 <[^>]+> f04f 0581 	mov\.w	r5, #129	; 0x81
-0+86c <[^>]+> 43c0      	mvns	r0, r0
-0+86e <[^>]+> ea6f 0000 	mvn\.w	r0, r0
-0+872 <[^>]+> 43c5      	mvns	r5, r0
-0+874 <[^>]+> ea6f 0005 	mvn\.w	r0, r5
-0+878 <[^>]+> ea6f 4065 	mvn\.w	r0, r5, asr #17
-0+87c <[^>]+> ea6f 0000 	mvn\.w	r0, r0
-0+880 <[^>]+> ea7f 0900 	mvns\.w	r9, r0
-0+884 <[^>]+> ea7f 0009 	mvns\.w	r0, r9
-0+888 <[^>]+> f06f 0081 	mvn\.w	r0, #129	; 0x81
-0+88c <[^>]+> f06f 0581 	mvn\.w	r5, #129	; 0x81
-0+890 <[^>]+> f240 0000 	movw	r0, #0	; 0x0
-0+894 <[^>]+> f2c0 0000 	movt	r0, #0	; 0x0
-0+898 <[^>]+> f240 0900 	movw	r9, #0	; 0x0
-0+89c <[^>]+> f249 0000 	movw	r0, #36864	; 0x9000
-0+8a0 <[^>]+> f640 0000 	movw	r0, #2048	; 0x800
-0+8a4 <[^>]+> f240 5000 	movw	r0, #1280	; 0x500
-0+8a8 <[^>]+> f240 0081 	movw	r0, #129	; 0x81
-0+8ac <[^>]+> f64f 70ff 	movw	r0, #65535	; 0xffff
-0+8b0 <[^>]+> f3ef 8000 	mrs	r0, SPSR
-0+8b4 <[^>]+> f3ff 8000 	mrs	r0, CPSR
-0+8b8 <[^>]+> f3ef 8900 	mrs	r9, SPSR
-0+8bc <[^>]+> f3ff 8900 	mrs	r9, CPSR
-0+8c0 <[^>]+> f380 8100 	msr	SPSR_c, r0
-0+8c4 <[^>]+> f390 8100 	msr	CPSR_c, r0
-0+8c8 <[^>]+> f389 8100 	msr	SPSR_c, r9
-0+8cc <[^>]+> f380 8200 	msr	SPSR_x, r0
-0+8d0 <[^>]+> f380 8400 	msr	SPSR_s, r0
-0+8d4 <[^>]+> f380 8800 	msr	SPSR_f, r0
-0+8d8 <[^>]+> fb00 f000 	mul\.w	r0, r0, r0
-0+8dc <[^>]+> fb09 f000 	mul\.w	r0, r9, r0
-0+8e0 <[^>]+> fb00 f009 	mul\.w	r0, r0, r9
-0+8e4 <[^>]+> fb00 f000 	mul\.w	r0, r0, r0
-0+8e8 <[^>]+> fb00 f909 	mul\.w	r9, r0, r9
-0+8ec <[^>]+> 4345      	muls	r5, r0
-0+8ee <[^>]+> 4345      	muls	r5, r0
-0+8f0 <[^>]+> 4368      	muls	r0, r5
-0+8f2 <[^>]+> fb80 0100 	smull	r0, r1, r0, r0
-0+8f6 <[^>]+> fba0 0100 	umull	r0, r1, r0, r0
-0+8fa <[^>]+> fbc0 0100 	smlal	r0, r1, r0, r0
-0+8fe <[^>]+> fbe0 0100 	umlal	r0, r1, r0, r0
-0+902 <[^>]+> fb80 9000 	smull	r9, r0, r0, r0
-0+906 <[^>]+> fb80 0900 	smull	r0, r9, r0, r0
-0+90a <[^>]+> fb89 0100 	smull	r0, r1, r9, r0
-0+90e <[^>]+> fb80 0109 	smull	r0, r1, r0, r9
-0+912 <[^>]+> 4240      	negs	r0, r0
-0+914 <[^>]+> 4268      	negs	r0, r5
-0+916 <[^>]+> 4245      	negs	r5, r0
-0+918 <[^>]+> f1d0 0000 	rsbs	r0, r0, #0	; 0x0
-0+91c <[^>]+> f1d0 0500 	rsbs	r5, r0, #0	; 0x0
-0+920 <[^>]+> f1d5 0000 	rsbs	r0, r5, #0	; 0x0
-0+924 <[^>]+> f1c9 0000 	rsb	r0, r9, #0	; 0x0
-0+928 <[^>]+> f1c0 0900 	rsb	r9, r0, #0	; 0x0
-0+92c <[^>]+> f1d9 0000 	rsbs	r0, r9, #0	; 0x0
-0+930 <[^>]+> f1d0 0900 	rsbs	r9, r0, #0	; 0x0
-0+934 <[^>]+> eac0 0000 	pkhbt	r0, r0, r0
-0+938 <[^>]+> eac0 0900 	pkhbt	r9, r0, r0
-0+93c <[^>]+> eac9 0000 	pkhbt	r0, r9, r0
-0+940 <[^>]+> eac0 0009 	pkhbt	r0, r0, r9
-0+944 <[^>]+> eac0 5000 	pkhbt	r0, r0, r0, lsl #20
-0+948 <[^>]+> eac0 00c0 	pkhbt	r0, r0, r0, lsl #3
-0+94c <[^>]+> eac2 0103 	pkhbt	r1, r2, r3
-0+950 <[^>]+> eac2 4163 	pkhtb	r1, r2, r3, asr #17
-0+954 <[^>]+> b401      	push	\{r0\}
-0+956 <[^>]+> bc01      	pop	\{r0\}
-0+958 <[^>]+> b502      	push	\{r1, lr\}
-0+95a <[^>]+> bd02      	pop	\{r1, pc\}
-0+95c <[^>]+> e92d 1f00 	stmdb	sp!, \{r8, r9, sl, fp, ip\}
-0+960 <[^>]+> e8bd 1f00 	ldmia\.w	sp!, \{r8, r9, sl, fp, ip\}
-0+964 <[^>]+> fa92 f113 	qadd16	r1, r2, r3
-0+968 <[^>]+> fa82 f113 	qadd8	r1, r2, r3
-0+96c <[^>]+> faa2 f113 	qaddsubx	r1, r2, r3
-0+970 <[^>]+> fad2 f113 	qsub16	r1, r2, r3
-0+974 <[^>]+> fac2 f113 	qsub8	r1, r2, r3
-0+978 <[^>]+> fae2 f113 	qsubaddx	r1, r2, r3
-0+97c <[^>]+> fa92 f103 	sadd16	r1, r2, r3
-0+980 <[^>]+> fa82 f103 	sadd8	r1, r2, r3
-0+984 <[^>]+> faa2 f103 	saddsubx	r1, r2, r3
-0+988 <[^>]+> fad2 f103 	ssub16	r1, r2, r3
-0+98c <[^>]+> fac2 f103 	ssub8	r1, r2, r3
-0+990 <[^>]+> fae2 f103 	ssubaddx	r1, r2, r3
-0+994 <[^>]+> fa92 f123 	shadd16	r1, r2, r3
-0+998 <[^>]+> fa82 f123 	shadd8	r1, r2, r3
-0+99c <[^>]+> faa2 f123 	shaddsubx	r1, r2, r3
-0+9a0 <[^>]+> fad2 f123 	shsub16	r1, r2, r3
-0+9a4 <[^>]+> fac2 f123 	shsub8	r1, r2, r3
-0+9a8 <[^>]+> fae2 f123 	shsubaddx	r1, r2, r3
-0+9ac <[^>]+> fa92 f143 	uadd16	r1, r2, r3
-0+9b0 <[^>]+> fa82 f143 	uadd8	r1, r2, r3
-0+9b4 <[^>]+> faa2 f143 	uaddsubx	r1, r2, r3
-0+9b8 <[^>]+> fad2 f143 	usub16	r1, r2, r3
-0+9bc <[^>]+> fac2 f143 	usub8	r1, r2, r3
-0+9c0 <[^>]+> fae2 f143 	usubaddx	r1, r2, r3
-0+9c4 <[^>]+> fa92 f163 	uhadd16	r1, r2, r3
-0+9c8 <[^>]+> fa82 f163 	uhadd8	r1, r2, r3
-0+9cc <[^>]+> faa2 f163 	uhaddsubx	r1, r2, r3
-0+9d0 <[^>]+> fad2 f163 	uhsub16	r1, r2, r3
-0+9d4 <[^>]+> fac2 f163 	uhsub8	r1, r2, r3
-0+9d8 <[^>]+> fae2 f163 	uhsubaddx	r1, r2, r3
-0+9dc <[^>]+> fa92 f153 	uqadd16	r1, r2, r3
-0+9e0 <[^>]+> fa82 f153 	uqadd8	r1, r2, r3
-0+9e4 <[^>]+> faa2 f153 	uqaddsubx	r1, r2, r3
-0+9e8 <[^>]+> fad2 f153 	uqsub16	r1, r2, r3
-0+9ec <[^>]+> fac2 f153 	uqsub8	r1, r2, r3
-0+9f0 <[^>]+> fae2 f153 	uqsubaddx	r1, r2, r3
-0+9f4 <[^>]+> faa2 f183 	sel	r1, r2, r3
-0+9f8 <[^>]+> ba00      	rev	r0, r0
-0+9fa <[^>]+> fa90 f080 	rev\.w	r0, r0
-0+9fe <[^>]+> ba28      	rev	r0, r5
-0+a00 <[^>]+> ba05      	rev	r5, r0
-0+a02 <[^>]+> fa99 f089 	rev\.w	r0, r9
-0+a06 <[^>]+> fa90 f980 	rev\.w	r9, r0
-0+a0a <[^>]+> ba40      	rev16	r0, r0
-0+a0c <[^>]+> fa90 f090 	rev16\.w	r0, r0
-0+a10 <[^>]+> ba68      	rev16	r0, r5
-0+a12 <[^>]+> ba45      	rev16	r5, r0
-0+a14 <[^>]+> fa99 f099 	rev16\.w	r0, r9
-0+a18 <[^>]+> fa90 f990 	rev16\.w	r9, r0
-0+a1c <[^>]+> bac0      	revsh	r0, r0
-0+a1e <[^>]+> fa90 f0b0 	revsh\.w	r0, r0
-0+a22 <[^>]+> bae8      	revsh	r0, r5
-0+a24 <[^>]+> bac5      	revsh	r5, r0
-0+a26 <[^>]+> fa99 f0b9 	revsh\.w	r0, r9
-0+a2a <[^>]+> fa90 f9b0 	revsh\.w	r9, r0
-0+a2e <[^>]+> fa90 f0a0 	rbit	r0, r0
-0+a32 <[^>]+> fa90 f0a0 	rbit	r0, r0
-0+a36 <[^>]+> fa95 f0a0 	rbit	r0, r5
-0+a3a <[^>]+> fa90 f5a0 	rbit	r5, r0
-0+a3e <[^>]+> fa99 f0a0 	rbit	r0, r9
-0+a42 <[^>]+> fa90 f9a0 	rbit	r9, r0
-0+a46 <[^>]+> 0440      	lsls	r0, r0, #17
-0+a48 <[^>]+> 0380      	lsls	r0, r0, #14
-0+a4a <[^>]+> 0445      	lsls	r5, r0, #17
-0+a4c <[^>]+> 03a8      	lsls	r0, r5, #14
-0+a4e <[^>]+> 4080      	lsls	r0, r0
-0+a50 <[^>]+> 40a8      	lsls	r0, r5
-0+a52 <[^>]+> 40a8      	lsls	r0, r5
-0+a54 <[^>]+> ea4f 4949 	mov\.w	r9, r9, lsl #17
-0+a58 <[^>]+> ea4f 3989 	mov\.w	r9, r9, lsl #14
-0+a5c <[^>]+> ea5f 4049 	movs\.w	r0, r9, lsl #17
-0+a60 <[^>]+> ea4f 3980 	mov\.w	r9, r0, lsl #14
-0+a64 <[^>]+> fa00 f000 	lsl\.w	r0, r0, r0
-0+a68 <[^>]+> fa09 f909 	lsl\.w	r9, r9, r9
-0+a6c <[^>]+> fa19 f900 	lsls\.w	r9, r9, r0
-0+a70 <[^>]+> fa00 f009 	lsl\.w	r0, r0, r9
-0+a74 <[^>]+> fa00 f005 	lsl\.w	r0, r0, r5
-0+a78 <[^>]+> fa11 f002 	lsls\.w	r0, r1, r2
-0+a7c <[^>]+> 0c40      	lsrs	r0, r0, #17
-0+a7e <[^>]+> 0b80      	lsrs	r0, r0, #14
-0+a80 <[^>]+> 0c45      	lsrs	r5, r0, #17
-0+a82 <[^>]+> 0ba8      	lsrs	r0, r5, #14
-0+a84 <[^>]+> 40c0      	lsrs	r0, r0
-0+a86 <[^>]+> 40e8      	lsrs	r0, r5
-0+a88 <[^>]+> 40e8      	lsrs	r0, r5
-0+a8a <[^>]+> ea4f 4959 	mov\.w	r9, r9, lsr #17
-0+a8e <[^>]+> ea4f 3999 	mov\.w	r9, r9, lsr #14
-0+a92 <[^>]+> ea5f 4059 	movs\.w	r0, r9, lsr #17
-0+a96 <[^>]+> ea4f 3990 	mov\.w	r9, r0, lsr #14
-0+a9a <[^>]+> fa20 f000 	lsr\.w	r0, r0, r0
-0+a9e <[^>]+> fa29 f909 	lsr\.w	r9, r9, r9
-0+aa2 <[^>]+> fa39 f900 	lsrs\.w	r9, r9, r0
-0+aa6 <[^>]+> fa20 f009 	lsr\.w	r0, r0, r9
-0+aaa <[^>]+> fa20 f005 	lsr\.w	r0, r0, r5
-0+aae <[^>]+> fa31 f002 	lsrs\.w	r0, r1, r2
-0+ab2 <[^>]+> 1440      	asrs	r0, r0, #17
-0+ab4 <[^>]+> 1380      	asrs	r0, r0, #14
-0+ab6 <[^>]+> 1445      	asrs	r5, r0, #17
-0+ab8 <[^>]+> 13a8      	asrs	r0, r5, #14
-0+aba <[^>]+> 4100      	asrs	r0, r0
-0+abc <[^>]+> 4128      	asrs	r0, r5
-0+abe <[^>]+> 4128      	asrs	r0, r5
-0+ac0 <[^>]+> ea4f 4969 	mov\.w	r9, r9, asr #17
-0+ac4 <[^>]+> ea4f 39a9 	mov\.w	r9, r9, asr #14
-0+ac8 <[^>]+> ea5f 4069 	movs\.w	r0, r9, asr #17
-0+acc <[^>]+> ea4f 39a0 	mov\.w	r9, r0, asr #14
-0+ad0 <[^>]+> fa40 f000 	asr\.w	r0, r0, r0
-0+ad4 <[^>]+> fa49 f909 	asr\.w	r9, r9, r9
-0+ad8 <[^>]+> fa59 f900 	asrs\.w	r9, r9, r0
-0+adc <[^>]+> fa40 f009 	asr\.w	r0, r0, r9
-0+ae0 <[^>]+> fa40 f005 	asr\.w	r0, r0, r5
-0+ae4 <[^>]+> fa51 f002 	asrs\.w	r0, r1, r2
-0+ae8 <[^>]+> ea5f 4070 	movs\.w	r0, r0, ror #17
-0+aec <[^>]+> ea5f 30b0 	movs\.w	r0, r0, ror #14
-0+af0 <[^>]+> ea5f 4570 	movs\.w	r5, r0, ror #17
-0+af4 <[^>]+> ea5f 30b5 	movs\.w	r0, r5, ror #14
-0+af8 <[^>]+> 41c0      	rors	r0, r0
-0+afa <[^>]+> 41e8      	rors	r0, r5
-0+afc <[^>]+> 41e8      	rors	r0, r5
-0+afe <[^>]+> ea4f 4979 	mov\.w	r9, r9, ror #17
-0+b02 <[^>]+> ea4f 39b9 	mov\.w	r9, r9, ror #14
-0+b06 <[^>]+> ea5f 4079 	movs\.w	r0, r9, ror #17
-0+b0a <[^>]+> ea4f 39b0 	mov\.w	r9, r0, ror #14
-0+b0e <[^>]+> fa60 f000 	ror\.w	r0, r0, r0
-0+b12 <[^>]+> fa69 f909 	ror\.w	r9, r9, r9
-0+b16 <[^>]+> fa79 f900 	rors\.w	r9, r9, r0
-0+b1a <[^>]+> fa60 f009 	ror\.w	r0, r0, r9
-0+b1e <[^>]+> fa60 f005 	ror\.w	r0, r0, r5
-0+b22 <[^>]+> fa71 f002 	rors\.w	r0, r1, r2
-0+b26 <[^>]+> f7f0 8000 	smi	#0	; 0x0
-0+b2a <[^>]+> f7fd 8bca 	smi	#43981	; 0xabcd
-0+b2e <[^>]+> fb10 0000 	smlabb	r0, r0, r0, r0
-0+b32 <[^>]+> fb10 0900 	smlabb	r9, r0, r0, r0
-0+b36 <[^>]+> fb19 0000 	smlabb	r0, r9, r0, r0
-0+b3a <[^>]+> fb10 0009 	smlabb	r0, r0, r9, r0
-0+b3e <[^>]+> fb10 9000 	smlabb	r0, r0, r0, r9
-0+b42 <[^>]+> fb10 0020 	smlatb	r0, r0, r0, r0
-0+b46 <[^>]+> fb10 0010 	smlabt	r0, r0, r0, r0
-0+b4a <[^>]+> fb10 0030 	smlatt	r0, r0, r0, r0
-0+b4e <[^>]+> fb30 0000 	smlawb	r0, r0, r0, r0
-0+b52 <[^>]+> fb30 0010 	smlawt	r0, r0, r0, r0
-0+b56 <[^>]+> fb20 0000 	smlad	r0, r0, r0, r0
-0+b5a <[^>]+> fb20 0010 	smladx	r0, r0, r0, r0
-0+b5e <[^>]+> fb40 0000 	smlsd	r0, r0, r0, r0
-0+b62 <[^>]+> fb40 0010 	smlsdx	r0, r0, r0, r0
-0+b66 <[^>]+> fb50 0000 	smmla	r0, r0, r0, r0
-0+b6a <[^>]+> fb50 0010 	smmlar	r0, r0, r0, r0
-0+b6e <[^>]+> fb60 0000 	smmls	r0, r0, r0, r0
-0+b72 <[^>]+> fb60 0010 	smmlsr	r0, r0, r0, r0
-0+b76 <[^>]+> fb70 0000 	usada8	r0, r0, r0, r0
-0+b7a <[^>]+> fbc0 0080 	smlalbb	r0, r0, r0, r0
-0+b7e <[^>]+> fbc0 9080 	smlalbb	r9, r0, r0, r0
-0+b82 <[^>]+> fbc0 0980 	smlalbb	r0, r9, r0, r0
-0+b86 <[^>]+> fbc9 0080 	smlalbb	r0, r0, r9, r0
-0+b8a <[^>]+> fbc0 0089 	smlalbb	r0, r0, r0, r9
-0+b8e <[^>]+> fbc0 00a0 	smlaltb	r0, r0, r0, r0
-0+b92 <[^>]+> fbc0 0090 	smlalbt	r0, r0, r0, r0
-0+b96 <[^>]+> fbc0 00b0 	smlaltt	r0, r0, r0, r0
-0+b9a <[^>]+> fbc0 00c0 	smlald	r0, r0, r0, r0
-0+b9e <[^>]+> fbc0 00d0 	smlaldx	r0, r0, r0, r0
-0+ba2 <[^>]+> fbd0 00c0 	smlsld	r0, r0, r0, r0
-0+ba6 <[^>]+> fbd0 00d0 	smlsldx	r0, r0, r0, r0
-0+baa <[^>]+> fbe0 0060 	umaal	r0, r0, r0, r0
-0+bae <[^>]+> fb10 f000 	smulbb	r0, r0, r0
-0+bb2 <[^>]+> fb10 f900 	smulbb	r9, r0, r0
-0+bb6 <[^>]+> fb19 f000 	smulbb	r0, r9, r0
-0+bba <[^>]+> fb10 f009 	smulbb	r0, r0, r9
-0+bbe <[^>]+> fb10 f020 	smultb	r0, r0, r0
-0+bc2 <[^>]+> fb10 f010 	smulbt	r0, r0, r0
-0+bc6 <[^>]+> fb10 f030 	smultt	r0, r0, r0
-0+bca <[^>]+> fb30 f000 	smulwb	r0, r0, r0
-0+bce <[^>]+> fb30 f010 	smulwt	r0, r0, r0
-0+bd2 <[^>]+> fb50 f000 	smmul	r0, r0, r0
-0+bd6 <[^>]+> fb50 f010 	smmulr	r0, r0, r0
-0+bda <[^>]+> fb20 f000 	smuad	r0, r0, r0
-0+bde <[^>]+> fb20 f010 	smuadx	r0, r0, r0
-0+be2 <[^>]+> fb40 f000 	smusd	r0, r0, r0
-0+be6 <[^>]+> fb40 f010 	smusdx	r0, r0, r0
-0+bea <[^>]+> fb70 f000 	usad8	r0, r0, r0
-0+bee <[^>]+> f300 0000 	ssat	r0, #0, r0
-0+bf2 <[^>]+> f300 0000 	ssat	r0, #0, r0
-0+bf6 <[^>]+> f300 0000 	ssat	r0, #0, r0
-0+bfa <[^>]+> f300 0900 	ssat	r9, #0, r0
-0+bfe <[^>]+> f300 0011 	ssat	r0, #17, r0
-0+c02 <[^>]+> f309 0000 	ssat	r0, #0, r9
-0+c06 <[^>]+> f300 7000 	ssat	r0, #0, r0, lsl #28
-0+c0a <[^>]+> f320 00c0 	ssat	r0, #0, r0, asr #3
-0+c0e <[^>]+> f320 0000 	ssat16	r0, #0, r0
-0+c12 <[^>]+> f320 0900 	ssat16	r9, #0, r0
-0+c16 <[^>]+> f320 0009 	ssat16	r0, #9, r0
-0+c1a <[^>]+> f329 0000 	ssat16	r0, #0, r9
-0+c1e <[^>]+> f380 0000 	usat	r0, #0, r0
-0+c22 <[^>]+> f380 0000 	usat	r0, #0, r0
-0+c26 <[^>]+> f380 0000 	usat	r0, #0, r0
-0+c2a <[^>]+> f380 0900 	usat	r9, #0, r0
-0+c2e <[^>]+> f380 0011 	usat	r0, #17, r0
-0+c32 <[^>]+> f389 0000 	usat	r0, #0, r9
-0+c36 <[^>]+> f380 7000 	usat	r0, #0, r0, lsl #28
-0+c3a <[^>]+> f3a0 00c0 	usat	r0, #0, r0, asr #3
-0+c3e <[^>]+> f3a0 0000 	usat16	r0, #0, r0
-0+c42 <[^>]+> f3a0 0900 	usat16	r9, #0, r0
-0+c46 <[^>]+> f3a0 0009 	usat16	r0, #9, r0
-0+c4a <[^>]+> f3a9 0000 	usat16	r0, #0, r9
-0+c4e <[^>]+> b240      	sxtb	r0, r0
-0+c50 <[^>]+> b240      	sxtb	r0, r0
-0+c52 <[^>]+> b245      	sxtb	r5, r0
-0+c54 <[^>]+> b268      	sxtb	r0, r5
-0+c56 <[^>]+> fa4f f182 	sxtb\.w	r1, r2
-0+c5a <[^>]+> fa4f f192 	sxtb\.w	r1, r2, ror #8
-0+c5e <[^>]+> fa4f f1a2 	sxtb\.w	r1, r2, ror #16
-0+c62 <[^>]+> fa4f f1b2 	sxtb\.w	r1, r2, ror #24
-0+c66 <[^>]+> fa2f f182 	sxtb16	r1, r2
-0+c6a <[^>]+> fa2f f889 	sxtb16	r8, r9
-0+c6e <[^>]+> b211      	sxth	r1, r2
-0+c70 <[^>]+> fa0f f889 	sxth\.w	r8, r9
-0+c74 <[^>]+> b2d1      	uxtb	r1, r2
-0+c76 <[^>]+> fa5f f889 	uxtb\.w	r8, r9
-0+c7a <[^>]+> fa3f f182 	uxtb16	r1, r2
-0+c7e <[^>]+> fa3f f889 	uxtb16	r8, r9
-0+c82 <[^>]+> b291      	uxth	r1, r2
-0+c84 <[^>]+> fa1f f889 	uxth\.w	r8, r9
-0+c88 <[^>]+> fa40 f080 	sxtab	r0, r0, r0
-0+c8c <[^>]+> fa40 f080 	sxtab	r0, r0, r0
-0+c90 <[^>]+> fa40 f990 	sxtab	r9, r0, r0, ror #8
-0+c94 <[^>]+> fa49 f0a0 	sxtab	r0, r9, r0, ror #16
-0+c98 <[^>]+> fa40 f0b9 	sxtab	r0, r0, r9, ror #24
-0+c9c <[^>]+> fa22 f183 	sxtab16	r1, r2, r3
-0+ca0 <[^>]+> fa02 f183 	sxtah	r1, r2, r3
-0+ca4 <[^>]+> fa52 f183 	uxtab	r1, r2, r3
-0+ca8 <[^>]+> fa32 f183 	uxtab16	r1, r2, r3
-0+cac <[^>]+> fa12 f183 	uxtah	r1, r2, r3
-0+cb0 <[^>]+> f89f 12aa 	ldrb\.w	r1, \[pc, #682\]	; 0+f5e <[^>]+>
-0+cb4 <[^>]+> f89f 1155 	ldrb\.w	r1, \[pc, #341\]	; 0+e0d <[^>]+>
-0+cb8 <[^>]+> f81f 12aa 	ldrb\.w	r1, \[pc, #-682\]	; 0+a12 <[^>]+>
-0+cbc <[^>]+> f81f 1155 	ldrb\.w	r1, \[pc, #-341\]	; 0+b6b <[^>]+>
-0+cc0 <[^>]+> f99f 12aa 	ldrsb\.w	r1, \[pc, #682\]	; 0+f6e <[^>]+>
-0+cc4 <[^>]+> f99f 1155 	ldrsb\.w	r1, \[pc, #341\]	; 0+e1d <[^>]+>
-0+cc8 <[^>]+> f91f 12aa 	ldrsb\.w	r1, \[pc, #-682\]	; 0+a22 <[^>]+>
-0+ccc <[^>]+> f91f 1155 	ldrsb\.w	r1, \[pc, #-341\]	; 0+b7b <[^>]+>
-0+cd0 <[^>]+> f8bf 12aa 	ldrh\.w	r1, \[pc, #682\]	; 0+f7e <[^>]+>
-0+cd4 <[^>]+> f8bf 1155 	ldrh\.w	r1, \[pc, #341\]	; 0+e2d <[^>]+>
-0+cd8 <[^>]+> f83f 12aa 	ldrh\.w	r1, \[pc, #-682\]	; 0+a32 <[^>]+>
-0+cdc <[^>]+> f83f 1155 	ldrh\.w	r1, \[pc, #-341\]	; 0+b8b <[^>]+>
-0+ce0 <[^>]+> f9bf 12aa 	ldrsh\.w	r1, \[pc, #682\]	; 0+f8e <[^>]+>
-0+ce4 <[^>]+> f9bf 1155 	ldrsh\.w	r1, \[pc, #341\]	; 0+e3d <[^>]+>
-0+ce8 <[^>]+> f93f 12aa 	ldrsh\.w	r1, \[pc, #-682\]	; 0+a42 <[^>]+>
-0+cec <[^>]+> f93f 1155 	ldrsh\.w	r1, \[pc, #-341\]	; 0+b9b <[^>]+>
-0+cf0 <[^>]+> f8df 12aa 	ldr\.w	r1, \[pc, #682\]	; 0+f9e <[^>]+>
-0+cf4 <[^>]+> f8df 1155 	ldr\.w	r1, \[pc, #341\]	; 0+e4d <[^>]+>
-0+cf8 <[^>]+> f85f 12aa 	ldr\.w	r1, \[pc, #-682\]	; 0+a52 <[^>]+>
-0+cfc <[^>]+> f85f 1155 	ldr\.w	r1, \[pc, #-341\]	; 0+bab <[^>]+>
-0+d00 <[^>]+> f200 0900 	addw	r9, r0, #0	; 0x0
-0+d04 <[^>]+> f60f 76ff 	addw	r6, pc, #4095	; 0xfff
-0+d08 <[^>]+> f6a9 2685 	subw	r6, r9, #2693	; 0xa85
-0+d0c <[^>]+> f2a9 567a 	subw	r6, r9, #1402	; 0x57a
-0+d10 <[^>]+> e8df f006 	tbb	\[pc, r6\]
-0+d14 <[^>]+> e8d0 f009 	tbb	\[r0, r9\]
-0+d18 <[^>]+> e8df f017 	tbh	\[pc, r7, lsl #1\]
-0+d1c <[^>]+> e8d0 f018 	tbh	\[r0, r8, lsl #1\]
-0+d20 <[^>]+> f84d 8d04 	str.w	r8, \[sp, #-4\]!
-0+d24 <[^>]+> f85d 8b04 	ldr.w	r8, \[sp\], #4
-0+d28 <[^>]+> e930 0580 	ldmdb	r0!, \{r7, r8, sl\}
-0+d2c <[^>]+> e920 0580 	stmdb	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> f041 0000 	orr\.w	r0, r1, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f041 00a5 	orr\.w	r0, r1, #165	; 0xa5
+0[0-9a-f]+ <[^>]+> f041 10a5 	orr\.w	r0, r1, #10813605	; 0xa500a5
+0[0-9a-f]+ <[^>]+> f041 20a5 	orr\.w	r0, r1, #2768282880	; 0xa500a500
+0[0-9a-f]+ <[^>]+> f041 30a5 	orr\.w	r0, r1, #2779096485	; 0xa5a5a5a5
+0[0-9a-f]+ <[^>]+> f041 4000 	orr\.w	r0, r1, #2147483648	; 0x80000000
+0[0-9a-f]+ <[^>]+> f041 4080 	orr\.w	r0, r1, #1073741824	; 0x40000000
+0[0-9a-f]+ <[^>]+> f041 4020 	orr\.w	r0, r1, #2684354560	; 0xa0000000
+0[0-9a-f]+ <[^>]+> f041 40a0 	orr\.w	r0, r1, #1342177280	; 0x50000000
+0[0-9a-f]+ <[^>]+> f041 5020 	orr\.w	r0, r1, #671088640	; 0x28000000
+0[0-9a-f]+ <[^>]+> f041 4014 	orr\.w	r0, r1, #2483027968	; 0x94000000
+0[0-9a-f]+ <[^>]+> f041 4094 	orr\.w	r0, r1, #1241513984	; 0x4a000000
+0[0-9a-f]+ <[^>]+> f041 4025 	orr\.w	r0, r1, #2768240640	; 0xa5000000
+0[0-9a-f]+ <[^>]+> f041 40a5 	orr\.w	r0, r1, #1384120320	; 0x52800000
+0[0-9a-f]+ <[^>]+> f041 5025 	orr\.w	r0, r1, #692060160	; 0x29400000
+0[0-9a-f]+ <[^>]+> f041 50a5 	orr\.w	r0, r1, #346030080	; 0x14a00000
+0[0-9a-f]+ <[^>]+> f041 6025 	orr\.w	r0, r1, #173015040	; 0xa500000
+0[0-9a-f]+ <[^>]+> f041 60a5 	orr\.w	r0, r1, #86507520	; 0x5280000
+0[0-9a-f]+ <[^>]+> f041 7025 	orr\.w	r0, r1, #43253760	; 0x2940000
+0[0-9a-f]+ <[^>]+> f041 70a5 	orr\.w	r0, r1, #21626880	; 0x14a0000
+0[0-9a-f]+ <[^>]+> f441 0025 	orr\.w	r0, r1, #10813440	; 0xa50000
+0[0-9a-f]+ <[^>]+> f441 00a5 	orr\.w	r0, r1, #5406720	; 0x528000
+0[0-9a-f]+ <[^>]+> f441 1025 	orr\.w	r0, r1, #2703360	; 0x294000
+0[0-9a-f]+ <[^>]+> f441 10a5 	orr\.w	r0, r1, #1351680	; 0x14a000
+0[0-9a-f]+ <[^>]+> f441 2025 	orr\.w	r0, r1, #675840	; 0xa5000
+0[0-9a-f]+ <[^>]+> f441 20a5 	orr\.w	r0, r1, #337920	; 0x52800
+0[0-9a-f]+ <[^>]+> f441 3025 	orr\.w	r0, r1, #168960	; 0x29400
+0[0-9a-f]+ <[^>]+> f441 30a5 	orr\.w	r0, r1, #84480	; 0x14a00
+0[0-9a-f]+ <[^>]+> f441 4025 	orr\.w	r0, r1, #42240	; 0xa500
+0[0-9a-f]+ <[^>]+> f441 40a5 	orr\.w	r0, r1, #21120	; 0x5280
+0[0-9a-f]+ <[^>]+> f441 5025 	orr\.w	r0, r1, #10560	; 0x2940
+0[0-9a-f]+ <[^>]+> f441 50a5 	orr\.w	r0, r1, #5280	; 0x14a0
+0[0-9a-f]+ <[^>]+> f441 6025 	orr\.w	r0, r1, #2640	; 0xa50
+0[0-9a-f]+ <[^>]+> f441 60a5 	orr\.w	r0, r1, #1320	; 0x528
+0[0-9a-f]+ <[^>]+> f441 7025 	orr\.w	r0, r1, #660	; 0x294
+0[0-9a-f]+ <[^>]+> f441 70a5 	orr\.w	r0, r1, #330	; 0x14a
+0[0-9a-f]+ <[^>]+> 3000      	adds	r0, #0
+0[0-9a-f]+ <[^>]+> 1c05      	adds	r5, r0, #0
+0[0-9a-f]+ <[^>]+> 1c28      	adds	r0, r5, #0
+0[0-9a-f]+ <[^>]+> 1d50      	adds	r0, r2, #5
+0[0-9a-f]+ <[^>]+> 3081      	adds	r0, #129
+0[0-9a-f]+ <[^>]+> 3081      	adds	r0, #129
+0[0-9a-f]+ <[^>]+> 357e      	adds	r5, #126
+0[0-9a-f]+ <[^>]+> 1800      	adds	r0, r0, r0
+0[0-9a-f]+ <[^>]+> 1805      	adds	r5, r0, r0
+0[0-9a-f]+ <[^>]+> 1828      	adds	r0, r5, r0
+0[0-9a-f]+ <[^>]+> 1940      	adds	r0, r0, r5
+0[0-9a-f]+ <[^>]+> 18d1      	adds	r1, r2, r3
+0[0-9a-f]+ <[^>]+> 4480      	add	r8, r0
+0[0-9a-f]+ <[^>]+> 4440      	add	r0, r8
+0[0-9a-f]+ <[^>]+> 4440      	add	r0, r8
+0[0-9a-f]+ <[^>]+> 4440      	add	r0, r8
+0[0-9a-f]+ <[^>]+> eb00 0800 	add\.w	r8, r0, r0
+0[0-9a-f]+ <[^>]+> 4401      	add	r1, r0
+0[0-9a-f]+ <[^>]+> 4408      	add	r0, r1
+0[0-9a-f]+ <[^>]+> a000      	add	r0, pc, #0	\(adr r0,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a500      	add	r5, pc, #0	\(adr r5,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a081      	add	r0, pc, #516	\(adr r0,[0-9a-f]+ <[^>]+>\)
+0[0-9a-f]+ <[^>]+> a800      	add	r0, sp, #0
+0[0-9a-f]+ <[^>]+> ad00      	add	r5, sp, #0
+0[0-9a-f]+ <[^>]+> a881      	add	r0, sp, #516
+0[0-9a-f]+ <[^>]+> b000      	add	sp, #0
+0[0-9a-f]+ <[^>]+> b000      	add	sp, #0
+0[0-9a-f]+ <[^>]+> b041      	add	sp, #260
+0[0-9a-f]+ <[^>]+> f100 0000 	add\.w	r0, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f110 0000 	adds\.w	r0, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f100 0900 	add\.w	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f109 0000 	add\.w	r0, r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f100 0081 	add\.w	r0, r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f513 3580 	adds\.w	r5, r3, #65536	; 0x10000
+0[0-9a-f]+ <[^>]+> f10d 0001 	add\.w	r0, sp, #1	; 0x1
+0[0-9a-f]+ <[^>]+> f10d 0900 	add\.w	r9, sp, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f10d 0d04 	add\.w	sp, sp, #4	; 0x4
+0[0-9a-f]+ <[^>]+> eb00 0000 	add\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb10 0000 	adds\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb00 0900 	add\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eb09 0000 	add\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eb00 0009 	add\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eb09 080a 	add\.w	r8, r9, sl
+0[0-9a-f]+ <[^>]+> eb09 484a 	add\.w	r8, r9, sl, lsl #17
+0[0-9a-f]+ <[^>]+> eb08 081a 	add\.w	r8, r8, sl, lsr #32
+0[0-9a-f]+ <[^>]+> eb08 485a 	add\.w	r8, r8, sl, lsr #17
+0[0-9a-f]+ <[^>]+> eb09 082a 	add\.w	r8, r9, sl, asr #32
+0[0-9a-f]+ <[^>]+> eb09 486a 	add\.w	r8, r9, sl, asr #17
+0[0-9a-f]+ <[^>]+> eb09 083a 	add\.w	r8, r9, sl, rrx
+0[0-9a-f]+ <[^>]+> eb09 487a 	add\.w	r8, r9, sl, ror #17
+0[0-9a-f]+ <[^>]+> 3800      	subs	r0, #0
+0[0-9a-f]+ <[^>]+> 1e05      	subs	r5, r0, #0
+0[0-9a-f]+ <[^>]+> 1e28      	subs	r0, r5, #0
+0[0-9a-f]+ <[^>]+> 1f50      	subs	r0, r2, #5
+0[0-9a-f]+ <[^>]+> 3881      	subs	r0, #129
+0[0-9a-f]+ <[^>]+> 3d08      	subs	r5, #8
+0[0-9a-f]+ <[^>]+> 1a00      	subs	r0, r0, r0
+0[0-9a-f]+ <[^>]+> 1a05      	subs	r5, r0, r0
+0[0-9a-f]+ <[^>]+> 1a28      	subs	r0, r5, r0
+0[0-9a-f]+ <[^>]+> 1b40      	subs	r0, r0, r5
+0[0-9a-f]+ <[^>]+> b0c1      	sub	sp, #260
+0[0-9a-f]+ <[^>]+> b0c1      	sub	sp, #260
+0[0-9a-f]+ <[^>]+> ebb8 0800 	subs\.w	r8, r8, r0
+0[0-9a-f]+ <[^>]+> ebb0 0008 	subs\.w	r0, r0, r8
+0[0-9a-f]+ <[^>]+> f5b0 7082 	subs\.w	r0, r0, #260	; 0x104
+0[0-9a-f]+ <[^>]+> f1b2 0104 	subs\.w	r1, r2, #4	; 0x4
+0[0-9a-f]+ <[^>]+> f5b3 3580 	subs\.w	r5, r3, #65536	; 0x10000
+0[0-9a-f]+ <[^>]+> f1ad 0104 	sub\.w	r1, sp, #4	; 0x4
+0[0-9a-f]+ <[^>]+> f1ad 0900 	sub\.w	r9, sp, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1ad 0d04 	sub\.w	sp, sp, #4	; 0x4
+0[0-9a-f]+ <[^>]+> 4140      	adcs	r0, r0
+0[0-9a-f]+ <[^>]+> 4145      	adcs	r5, r0
+0[0-9a-f]+ <[^>]+> 4168      	adcs	r0, r5
+0[0-9a-f]+ <[^>]+> 4168      	adcs	r0, r5
+0[0-9a-f]+ <[^>]+> 4168      	adcs	r0, r5
+0[0-9a-f]+ <[^>]+> eb45 0000 	adc\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> eb41 0002 	adc\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> eb40 0900 	adc\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eb49 0000 	adc\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eb40 0009 	adc\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eb50 0000 	adcs\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb41 4062 	adc\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f141 0081 	adc\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4000      	ands	r0, r0
+0[0-9a-f]+ <[^>]+> 4005      	ands	r5, r0
+0[0-9a-f]+ <[^>]+> 4028      	ands	r0, r5
+0[0-9a-f]+ <[^>]+> 4028      	ands	r0, r5
+0[0-9a-f]+ <[^>]+> 4028      	ands	r0, r5
+0[0-9a-f]+ <[^>]+> ea05 0000 	and\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea01 0002 	and\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea00 0900 	and\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea09 0000 	and\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea00 0009 	and\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea10 0000 	ands\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea01 4062 	and\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f001 0081 	and\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4380      	bics	r0, r0
+0[0-9a-f]+ <[^>]+> 4385      	bics	r5, r0
+0[0-9a-f]+ <[^>]+> 43a8      	bics	r0, r5
+0[0-9a-f]+ <[^>]+> 43a8      	bics	r0, r5
+0[0-9a-f]+ <[^>]+> ea35 0000 	bics\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea25 0000 	bic\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea21 0002 	bic\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea20 0900 	bic\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea29 0000 	bic\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea20 0009 	bic\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea30 0000 	bics\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea21 4062 	bic\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f021 0081 	bic\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4040      	eors	r0, r0
+0[0-9a-f]+ <[^>]+> 4045      	eors	r5, r0
+0[0-9a-f]+ <[^>]+> 4068      	eors	r0, r5
+0[0-9a-f]+ <[^>]+> 4068      	eors	r0, r5
+0[0-9a-f]+ <[^>]+> 4068      	eors	r0, r5
+0[0-9a-f]+ <[^>]+> ea85 0000 	eor\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea81 0002 	eor\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea80 0900 	eor\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea89 0000 	eor\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea80 0009 	eor\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea90 0000 	eors\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea81 4062 	eor\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f081 0081 	eor\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4300      	orrs	r0, r0
+0[0-9a-f]+ <[^>]+> 4305      	orrs	r5, r0
+0[0-9a-f]+ <[^>]+> 4328      	orrs	r0, r5
+0[0-9a-f]+ <[^>]+> 4328      	orrs	r0, r5
+0[0-9a-f]+ <[^>]+> 4328      	orrs	r0, r5
+0[0-9a-f]+ <[^>]+> ea45 0000 	orr\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ea41 0002 	orr\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea40 0900 	orr\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ea49 0000 	orr\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ea40 0009 	orr\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ea50 0000 	orrs\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ea41 4062 	orr\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f041 0081 	orr\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> ebd0 0000 	rsbs	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ebd5 0500 	rsbs	r5, r5, r0
+0[0-9a-f]+ <[^>]+> ebd0 0005 	rsbs	r0, r0, r5
+0[0-9a-f]+ <[^>]+> ebd0 0005 	rsbs	r0, r0, r5
+0[0-9a-f]+ <[^>]+> ebd5 0000 	rsbs	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ebc5 0000 	rsb	r0, r5, r0
+0[0-9a-f]+ <[^>]+> ebc1 0002 	rsb	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ebc0 0900 	rsb	r9, r0, r0
+0[0-9a-f]+ <[^>]+> ebc9 0000 	rsb	r0, r9, r0
+0[0-9a-f]+ <[^>]+> ebc0 0009 	rsb	r0, r0, r9
+0[0-9a-f]+ <[^>]+> ebd0 0000 	rsbs	r0, r0, r0
+0[0-9a-f]+ <[^>]+> ebc1 4062 	rsb	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f1c1 0081 	rsb	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4180      	sbcs	r0, r0
+0[0-9a-f]+ <[^>]+> 4185      	sbcs	r5, r0
+0[0-9a-f]+ <[^>]+> 41a8      	sbcs	r0, r5
+0[0-9a-f]+ <[^>]+> 41a8      	sbcs	r0, r5
+0[0-9a-f]+ <[^>]+> eb75 0000 	sbcs\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> eb65 0000 	sbc\.w	r0, r5, r0
+0[0-9a-f]+ <[^>]+> eb61 0002 	sbc\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> eb60 0900 	sbc\.w	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eb69 0000 	sbc\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eb60 0009 	sbc\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eb70 0000 	sbcs\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eb61 4062 	sbc\.w	r0, r1, r2, asr #17
+0[0-9a-f]+ <[^>]+> f161 0081 	sbc\.w	r0, r1, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f36f 0000 	bfc	r0, #0, #1
+0[0-9a-f]+ <[^>]+> f36f 0900 	bfc	r9, #0, #1
+0[0-9a-f]+ <[^>]+> f36f 0900 	bfc	r9, #0, #1
+0[0-9a-f]+ <[^>]+> f36f 5055 	bfc	r0, #21, #1
+0[0-9a-f]+ <[^>]+> f36f 0011 	bfc	r0, #0, #18
+0[0-9a-f]+ <[^>]+> f360 0000 	bfi	r0, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f360 0900 	bfi	r9, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f369 0000 	bfi	r0, r9, #0, #1
+0[0-9a-f]+ <[^>]+> f360 5055 	bfi	r0, r0, #21, #1
+0[0-9a-f]+ <[^>]+> f360 0011 	bfi	r0, r0, #0, #18
+0[0-9a-f]+ <[^>]+> f340 0000 	sbfx	r0, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f3c0 0900 	ubfx	r9, r0, #0, #1
+0[0-9a-f]+ <[^>]+> f349 0000 	sbfx	r0, r9, #0, #1
+0[0-9a-f]+ <[^>]+> f3c0 5040 	ubfx	r0, r0, #21, #1
+0[0-9a-f]+ <[^>]+> f340 0011 	sbfx	r0, r0, #0, #18
+0[0-9a-f]+ <[^>]+> d0fe      	beq\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d02a      	beq\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d1fc      	bne\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d128      	bne\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d2fa      	bcs\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d226      	bcs\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d2f8      	bcs\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d224      	bcs\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f6      	bcc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d322      	bcc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f4      	bcc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d320      	bcc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d3f2      	bcc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d31e      	bcc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d4f0      	bmi\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d41c      	bmi\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d5ee      	bpl\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d51a      	bpl\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d6ec      	bvs\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d618      	bvs\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d7ea      	bvc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d716      	bvc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d8e8      	bhi\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d814      	bhi\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d9e6      	bls\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d912      	bls\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d7e4      	bvc\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d710      	bvc\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d8e2      	bhi\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d80e      	bhi\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> d9e0      	bls\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> d90c      	bls\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> dade      	bge\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> da0a      	bge\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> dbdc      	blt\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> db08      	blt\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> dcda      	bgt\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> dc06      	bgt\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> ddd8      	ble\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> dd04      	ble\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> e7d6      	b\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> e002      	b\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> e7d4      	b\.n	0+2ca <[^>]+>
+0[0-9a-f]+ <[^>]+> e000      	b\.n	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> 46c0      	nop			\(mov r8, r8\)
+0[0-9a-f]+ <[^>]+> f43f affe 	beq\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 8058 	beq\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f47f affa 	bne\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f040 8054 	bne\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4bf aff6 	bcs\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f080 8050 	bcs\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4bf aff2 	bcs\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f080 804c 	bcs\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afee 	bcc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8048 	bcc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afea 	bcc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8044 	bcc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f4ff afe6 	bcc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f0c0 8040 	bcc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f53f afe2 	bmi\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f100 803c 	bmi\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f57f afde 	bpl\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f140 8038 	bpl\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f5bf afda 	bvs\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f180 8034 	bvs\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f5ff afd6 	bvc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f1c0 8030 	bvc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f63f afd2 	bhi\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 802c 	bhi\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f67f afce 	bls\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f240 8028 	bls\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f5ff afca 	bvc\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f1c0 8024 	bvc\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f63f afc6 	bhi\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 8020 	bhi\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f67f afc2 	bls\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f240 801c 	bls\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f6bf afbe 	bge\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f280 8018 	bge\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f6ff afba 	blt\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f2c0 8014 	blt\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f73f afb6 	bgt\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f300 8010 	bgt\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f77f afb2 	ble\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f340 800c 	ble\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff bfae 	b\.w	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 b808 	b\.w	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff ffaa 	bl	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 f804 	bl	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> f7ff efa6 	blx	0+324 <[^>]+>
+0[0-9a-f]+ <[^>]+> f000 e800 	blx	0+3dc <[^>]+>
+0[0-9a-f]+ <[^>]+> 4748      	bx	r9
+0[0-9a-f]+ <[^>]+> 4780      	blx	r0
+0[0-9a-f]+ <[^>]+> 47c8      	blx	r9
+0[0-9a-f]+ <[^>]+> f3c0 8f00 	bxj	r0
+0[0-9a-f]+ <[^>]+> f3c9 8f00 	bxj	r9
+0[0-9a-f]+ <[^>]+> fab0 f080 	clz	r0, r0
+0[0-9a-f]+ <[^>]+> fab0 f980 	clz	r9, r0
+0[0-9a-f]+ <[^>]+> fab9 f089 	clz	r0, r9
+0[0-9a-f]+ <[^>]+> b661      	cpsie	f
+0[0-9a-f]+ <[^>]+> b672      	cpsid	i
+0[0-9a-f]+ <[^>]+> b664      	cpsie	a
+0[0-9a-f]+ <[^>]+> f3af 8620 	cpsid\.w	f
+0[0-9a-f]+ <[^>]+> f3af 8440 	cpsie\.w	i
+0[0-9a-f]+ <[^>]+> f3af 8680 	cpsid\.w	a
+0[0-9a-f]+ <[^>]+> f3af 8540 	cpsie	i, #0
+0[0-9a-f]+ <[^>]+> f3af 8751 	cpsid	i, #17
+0[0-9a-f]+ <[^>]+> f3af 8100 	cps	#0
+0[0-9a-f]+ <[^>]+> f3af 8111 	cps	#17
+0[0-9a-f]+ <[^>]+> 4600      	mov	r0, r0
+0[0-9a-f]+ <[^>]+> 4681      	mov	r9, r0
+0[0-9a-f]+ <[^>]+> 4648      	mov	r0, r9
+0[0-9a-f]+ <[^>]+> ea4f 0000 	mov\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea4f 0900 	mov\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea4f 0009 	mov\.w	r0, r9
+0[0-9a-f]+ <[^>]+> b910      	cbnz	r0, 0+432 <[^>]+>
+0[0-9a-f]+ <[^>]+> b105      	cbz	r5, 0+430 <[^>]+>
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf10      	yield
+0[0-9a-f]+ <[^>]+> bf20      	wfe
+0[0-9a-f]+ <[^>]+> bf30      	wfi
+0[0-9a-f]+ <[^>]+> bf40      	sev
+0[0-9a-f]+ <[^>]+> f3af 8000 	nop\.w
+0[0-9a-f]+ <[^>]+> f3af 8001 	yield\.w
+0[0-9a-f]+ <[^>]+> f3af 8002 	wfe\.w
+0[0-9a-f]+ <[^>]+> f3af 8003 	wfi\.w
+0[0-9a-f]+ <[^>]+> f3af 9004 	sev\.w
+0[0-9a-f]+ <[^>]+> bf90      	nop	\{9\}
+0[0-9a-f]+ <[^>]+> f3af 8081 	nop\.w	\{129\}
+0[0-9a-f]+ <[^>]+> bf08      	it	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf18      	it	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf28      	it	cs
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf28      	it	cs
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf38      	it	cc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf38      	it	cc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf38      	it	cc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf48      	it	mi
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf58      	it	pl
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf68      	it	vs
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf78      	it	vc
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf88      	it	hi
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfa8      	it	ge
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfb8      	it	lt
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfc8      	it	gt
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfd8      	it	le
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bfe8      	it	al
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf04      	itt	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0c      	ite	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf02      	ittt	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0a      	itet	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf06      	itte	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0e      	itee	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf01      	itttt	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf09      	itett	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf05      	ittet	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf03      	ittte	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf07      	ittee	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0b      	itete	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0d      	iteet	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf0f      	iteee	eq
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1c      	itt	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf14      	ite	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1e      	ittt	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf16      	itet	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1a      	itte	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf12      	itee	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1f      	itttt	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf17      	itett	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1b      	ittet	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf1d      	ittte	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf19      	ittee	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf15      	itete	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf13      	iteet	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf11      	iteee	ne
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> bf00      	nop
+0[0-9a-f]+ <[^>]+> f895 f000 	pld	\[r5\]
+0[0-9a-f]+ <[^>]+> f895 f330 	pld	\[r5, #816\]
+0[0-9a-f]+ <[^>]+> f815 fc30 	pld	\[r5, #-48\]
+0[0-9a-f]+ <[^>]+> f815 fb30 	pld	\[r5\], #48
+0[0-9a-f]+ <[^>]+> f815 f930 	pld	\[r5\], #-48
+0[0-9a-f]+ <[^>]+> f815 ff30 	pld	\[r5, #48\]!
+0[0-9a-f]+ <[^>]+> f815 fd30 	pld	\[r5, #-48\]!
+0[0-9a-f]+ <[^>]+> f815 f000 	pld	\[r5, r0\]
+0[0-9a-f]+ <[^>]+> f819 f000 	pld	\[r9, r0\]
+0[0-9a-f]+ <[^>]+> f89f f006 	pld	\[pc, #6\]	; 0+5ba <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f f02a 	pld	\[pc, #-42\]	; 0+58e <[^>]+>
+0[0-9a-f]+ <[^>]+> e9d5 2300 	ldrd	r2, r3, \[r5\]
+0[0-9a-f]+ <[^>]+> e9d5 230c 	ldrd	r2, r3, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> e955 230c 	ldrd	r2, r3, \[r5, #-48\]
+0[0-9a-f]+ <[^>]+> e9c5 2300 	strd	r2, r3, \[r5\]
+0[0-9a-f]+ <[^>]+> e9c5 230c 	strd	r2, r3, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> e945 230c 	strd	r2, r3, \[r5, #-48\]
+0[0-9a-f]+ <[^>]+> f835 1e00 	ldrht	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f835 1e30 	ldrht	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f915 1e00 	ldrsbt	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f915 1e30 	ldrsbt	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f835 1e00 	ldrht	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f835 1e30 	ldrht	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f935 1e00 	ldrsht	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f935 1e30 	ldrsht	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> f855 1e00 	ldrt	r1, \[r5\]
+0[0-9a-f]+ <[^>]+> f855 1e30 	ldrt	r1, \[r5, #48\]
+0[0-9a-f]+ <[^>]+> e8d4 1f4f 	ldrexb	r1, \[r4\]
+0[0-9a-f]+ <[^>]+> e8d4 1f5f 	ldrexh	r1, \[r4\]
+0[0-9a-f]+ <[^>]+> e854 1f00 	ldrex	r1, \[r4\]
+0[0-9a-f]+ <[^>]+> e8d4 127f 	ldrexd	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e8c4 2f41 	strexb	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e8c4 2f51 	strexh	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e844 2100 	strex	r1, r2, \[r4\]
+0[0-9a-f]+ <[^>]+> e8c4 2371 	strexd	r1, r2, r3, \[r4\]
+0[0-9a-f]+ <[^>]+> e854 1f81 	ldrex	r1, \[r4, #516\]
+0[0-9a-f]+ <[^>]+> e844 2181 	strex	r1, r2, \[r4, #516\]
+0[0-9a-f]+ <[^>]+> c80e      	ldmia	r0!, \{r1, r2, r3\}
+0[0-9a-f]+ <[^>]+> ca07      	ldmia	r2!, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e892 0007 	ldmia\.w	r2, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e899 0007 	ldmia\.w	r9, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e890 0580 	ldmia\.w	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e8b0 0580 	ldmia\.w	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> c00e      	stmia	r0!, \{r1, r2, r3\}
+0[0-9a-f]+ <[^>]+> c20b      	stmia	r2!, \{r0, r1, r3\}
+0[0-9a-f]+ <[^>]+> e8a2 000b 	stmia\.w	r2!, \{r0, r1, r3\}
+0[0-9a-f]+ <[^>]+> e889 0007 	stmia\.w	r9, \{r0, r1, r2\}
+0[0-9a-f]+ <[^>]+> e880 0580 	stmia\.w	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e8a0 0580 	stmia\.w	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e910 0580 	ldmdb	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e900 0580 	stmdb	r0, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> fb00 0000 	mla	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 0010 	mls	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 0900 	mla	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb09 0000 	mla	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 0009 	mla	r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb00 9000 	mla	r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> 4200      	tst	r0, r0
+0[0-9a-f]+ <[^>]+> 4200      	tst	r0, r0
+0[0-9a-f]+ <[^>]+> 4205      	tst	r5, r0
+0[0-9a-f]+ <[^>]+> 4228      	tst	r0, r5
+0[0-9a-f]+ <[^>]+> ea10 4f65 	tst\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea10 0f00 	tst\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea19 0f00 	tst\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea10 0f09 	tst\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f010 0f81 	tst\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f015 0f81 	tst\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> ea90 0f00 	teq	r0, r0
+0[0-9a-f]+ <[^>]+> ea90 0f00 	teq	r0, r0
+0[0-9a-f]+ <[^>]+> ea95 0f00 	teq	r5, r0
+0[0-9a-f]+ <[^>]+> ea90 0f05 	teq	r0, r5
+0[0-9a-f]+ <[^>]+> ea90 4f65 	teq	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea90 0f00 	teq	r0, r0
+0[0-9a-f]+ <[^>]+> ea99 0f00 	teq	r9, r0
+0[0-9a-f]+ <[^>]+> ea90 0f09 	teq	r0, r9
+0[0-9a-f]+ <[^>]+> f090 0f81 	teq	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f095 0f81 	teq	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 4280      	cmp	r0, r0
+0[0-9a-f]+ <[^>]+> 4280      	cmp	r0, r0
+0[0-9a-f]+ <[^>]+> 4285      	cmp	r5, r0
+0[0-9a-f]+ <[^>]+> 42a8      	cmp	r0, r5
+0[0-9a-f]+ <[^>]+> ebb0 4f65 	cmp\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ebb0 0f00 	cmp\.w	r0, r0
+0[0-9a-f]+ <[^>]+> 4581      	cmp	r9, r0
+0[0-9a-f]+ <[^>]+> ebb0 0f09 	cmp\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f1b0 0f81 	cmp\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f1b5 0f81 	cmp\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 42c0      	cmn	r0, r0
+0[0-9a-f]+ <[^>]+> 42c0      	cmn	r0, r0
+0[0-9a-f]+ <[^>]+> 42c5      	cmn	r5, r0
+0[0-9a-f]+ <[^>]+> 42e8      	cmn	r0, r5
+0[0-9a-f]+ <[^>]+> eb10 4f65 	cmn\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> eb10 0f00 	cmn\.w	r0, r0
+0[0-9a-f]+ <[^>]+> eb19 0f00 	cmn\.w	r9, r0
+0[0-9a-f]+ <[^>]+> eb10 0f09 	cmn\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f110 0f81 	cmn\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f115 0f81 	cmn\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 1c00      	adds	r0, r0, #0
+0[0-9a-f]+ <[^>]+> 4600      	mov	r0, r0
+0[0-9a-f]+ <[^>]+> 1c05      	adds	r5, r0, #0
+0[0-9a-f]+ <[^>]+> 4628      	mov	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4065 	mov\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea4f 0000 	mov\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea5f 0900 	movs\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea5f 0009 	movs\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f04f 0081 	mov\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f04f 0581 	mov\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> 43c0      	mvns	r0, r0
+0[0-9a-f]+ <[^>]+> ea6f 0000 	mvn\.w	r0, r0
+0[0-9a-f]+ <[^>]+> 43c5      	mvns	r5, r0
+0[0-9a-f]+ <[^>]+> ea6f 0005 	mvn\.w	r0, r5
+0[0-9a-f]+ <[^>]+> ea6f 4065 	mvn\.w	r0, r5, asr #17
+0[0-9a-f]+ <[^>]+> ea6f 0000 	mvn\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ea7f 0900 	mvns\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ea7f 0009 	mvns\.w	r0, r9
+0[0-9a-f]+ <[^>]+> f06f 0081 	mvn\.w	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f06f 0581 	mvn\.w	r5, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f240 0000 	movw	r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f2c0 0000 	movt	r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f240 0900 	movw	r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f249 0000 	movw	r0, #36864	; 0x9000
+0[0-9a-f]+ <[^>]+> f640 0000 	movw	r0, #2048	; 0x800
+0[0-9a-f]+ <[^>]+> f240 5000 	movw	r0, #1280	; 0x500
+0[0-9a-f]+ <[^>]+> f240 0081 	movw	r0, #129	; 0x81
+0[0-9a-f]+ <[^>]+> f64f 70ff 	movw	r0, #65535	; 0xffff
+0[0-9a-f]+ <[^>]+> f3ef 8000 	mrs	r0, SPSR
+0[0-9a-f]+ <[^>]+> f3ff 8000 	mrs	r0, CPSR
+0[0-9a-f]+ <[^>]+> f3ef 8900 	mrs	r9, SPSR
+0[0-9a-f]+ <[^>]+> f3ff 8900 	mrs	r9, CPSR
+0[0-9a-f]+ <[^>]+> f380 8100 	msr	SPSR_c, r0
+0[0-9a-f]+ <[^>]+> f390 8100 	msr	CPSR_c, r0
+0[0-9a-f]+ <[^>]+> f389 8100 	msr	SPSR_c, r9
+0[0-9a-f]+ <[^>]+> f380 8200 	msr	SPSR_x, r0
+0[0-9a-f]+ <[^>]+> f380 8400 	msr	SPSR_s, r0
+0[0-9a-f]+ <[^>]+> f380 8800 	msr	SPSR_f, r0
+0[0-9a-f]+ <[^>]+> fb00 f000 	mul\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb09 f000 	mul\.w	r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb00 f009 	mul\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb00 f000 	mul\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb00 f909 	mul\.w	r9, r0, r9
+0[0-9a-f]+ <[^>]+> 4345      	muls	r5, r0
+0[0-9a-f]+ <[^>]+> 4345      	muls	r5, r0
+0[0-9a-f]+ <[^>]+> 4368      	muls	r0, r5
+0[0-9a-f]+ <[^>]+> fb80 0100 	smull	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fba0 0100 	umull	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0100 	smlal	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fbe0 0100 	umlal	r0, r1, r0, r0
+0[0-9a-f]+ <[^>]+> fb80 9000 	smull	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb80 0900 	smull	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb89 0100 	smull	r0, r1, r9, r0
+0[0-9a-f]+ <[^>]+> fb80 0109 	smull	r0, r1, r0, r9
+0[0-9a-f]+ <[^>]+> 4240      	negs	r0, r0
+0[0-9a-f]+ <[^>]+> 4268      	negs	r0, r5
+0[0-9a-f]+ <[^>]+> 4245      	negs	r5, r0
+0[0-9a-f]+ <[^>]+> f1d0 0000 	rsbs	r0, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d0 0500 	rsbs	r5, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d5 0000 	rsbs	r0, r5, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1c9 0000 	rsb	r0, r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1c0 0900 	rsb	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d9 0000 	rsbs	r0, r9, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f1d0 0900 	rsbs	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> eac0 0000 	pkhbt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> eac0 0900 	pkhbt	r9, r0, r0
+0[0-9a-f]+ <[^>]+> eac9 0000 	pkhbt	r0, r9, r0
+0[0-9a-f]+ <[^>]+> eac0 0009 	pkhbt	r0, r0, r9
+0[0-9a-f]+ <[^>]+> eac0 5000 	pkhbt	r0, r0, r0, lsl #20
+0[0-9a-f]+ <[^>]+> eac0 00c0 	pkhbt	r0, r0, r0, lsl #3
+0[0-9a-f]+ <[^>]+> eac2 0103 	pkhbt	r1, r2, r3
+0[0-9a-f]+ <[^>]+> eac2 4163 	pkhtb	r1, r2, r3, asr #17
+0[0-9a-f]+ <[^>]+> b401      	push	\{r0\}
+0[0-9a-f]+ <[^>]+> bc01      	pop	\{r0\}
+0[0-9a-f]+ <[^>]+> b502      	push	\{r1, lr\}
+0[0-9a-f]+ <[^>]+> bd02      	pop	\{r1, pc\}
+0[0-9a-f]+ <[^>]+> e92d 1f00 	stmdb	sp!, \{r8, r9, sl, fp, ip\}
+0[0-9a-f]+ <[^>]+> e8bd 1f00 	ldmia\.w	sp!, \{r8, r9, sl, fp, ip\}
+0[0-9a-f]+ <[^>]+> fa92 f113 	qadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f113 	qadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f113 	qaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f113 	qsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f113 	qsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f113 	qsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f103 	sadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f103 	sadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f103 	saddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f103 	ssub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f103 	ssub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f103 	ssubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f123 	shadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f123 	shadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f123 	shaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f123 	shsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f123 	shsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f123 	shsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f143 	uadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f143 	uadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f143 	uaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f143 	usub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f143 	usub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f143 	usubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f163 	uhadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f163 	uhadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f163 	uhaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f163 	uhsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f163 	uhsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f163 	uhsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa92 f153 	uqadd16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa82 f153 	uqadd8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f153 	uqaddsubx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fad2 f153 	uqsub16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fac2 f153 	uqsub8	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fae2 f153 	uqsubaddx	r1, r2, r3
+0[0-9a-f]+ <[^>]+> faa2 f183 	sel	r1, r2, r3
+0[0-9a-f]+ <[^>]+> ba00      	rev	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f080 	rev\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ba28      	rev	r0, r5
+0[0-9a-f]+ <[^>]+> ba05      	rev	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f089 	rev\.w	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f980 	rev\.w	r9, r0
+0[0-9a-f]+ <[^>]+> ba40      	rev16	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f090 	rev16\.w	r0, r0
+0[0-9a-f]+ <[^>]+> ba68      	rev16	r0, r5
+0[0-9a-f]+ <[^>]+> ba45      	rev16	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f099 	rev16\.w	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f990 	rev16\.w	r9, r0
+0[0-9a-f]+ <[^>]+> bac0      	revsh	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f0b0 	revsh\.w	r0, r0
+0[0-9a-f]+ <[^>]+> bae8      	revsh	r0, r5
+0[0-9a-f]+ <[^>]+> bac5      	revsh	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f0b9 	revsh\.w	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f9b0 	revsh\.w	r9, r0
+0[0-9a-f]+ <[^>]+> fa90 f0a0 	rbit	r0, r0
+0[0-9a-f]+ <[^>]+> fa90 f0a0 	rbit	r0, r0
+0[0-9a-f]+ <[^>]+> fa95 f0a0 	rbit	r0, r5
+0[0-9a-f]+ <[^>]+> fa90 f5a0 	rbit	r5, r0
+0[0-9a-f]+ <[^>]+> fa99 f0a0 	rbit	r0, r9
+0[0-9a-f]+ <[^>]+> fa90 f9a0 	rbit	r9, r0
+0[0-9a-f]+ <[^>]+> 0440      	lsls	r0, r0, #17
+0[0-9a-f]+ <[^>]+> 0380      	lsls	r0, r0, #14
+0[0-9a-f]+ <[^>]+> 0445      	lsls	r5, r0, #17
+0[0-9a-f]+ <[^>]+> 03a8      	lsls	r0, r5, #14
+0[0-9a-f]+ <[^>]+> 4080      	lsls	r0, r0
+0[0-9a-f]+ <[^>]+> 40a8      	lsls	r0, r5
+0[0-9a-f]+ <[^>]+> 40a8      	lsls	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4949 	mov\.w	r9, r9, lsl #17
+0[0-9a-f]+ <[^>]+> ea4f 3989 	mov\.w	r9, r9, lsl #14
+0[0-9a-f]+ <[^>]+> ea5f 4049 	movs\.w	r0, r9, lsl #17
+0[0-9a-f]+ <[^>]+> ea4f 3980 	mov\.w	r9, r0, lsl #14
+0[0-9a-f]+ <[^>]+> fa00 f000 	lsl\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa09 f909 	lsl\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa19 f900 	lsls\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa00 f009 	lsl\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa00 f005 	lsl\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa11 f002 	lsls\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> 0c40      	lsrs	r0, r0, #17
+0[0-9a-f]+ <[^>]+> 0b80      	lsrs	r0, r0, #14
+0[0-9a-f]+ <[^>]+> 0c45      	lsrs	r5, r0, #17
+0[0-9a-f]+ <[^>]+> 0ba8      	lsrs	r0, r5, #14
+0[0-9a-f]+ <[^>]+> 40c0      	lsrs	r0, r0
+0[0-9a-f]+ <[^>]+> 40e8      	lsrs	r0, r5
+0[0-9a-f]+ <[^>]+> 40e8      	lsrs	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4959 	mov\.w	r9, r9, lsr #17
+0[0-9a-f]+ <[^>]+> ea4f 3999 	mov\.w	r9, r9, lsr #14
+0[0-9a-f]+ <[^>]+> ea5f 4059 	movs\.w	r0, r9, lsr #17
+0[0-9a-f]+ <[^>]+> ea4f 3990 	mov\.w	r9, r0, lsr #14
+0[0-9a-f]+ <[^>]+> fa20 f000 	lsr\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa29 f909 	lsr\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa39 f900 	lsrs\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa20 f009 	lsr\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa20 f005 	lsr\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa31 f002 	lsrs\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> 1440      	asrs	r0, r0, #17
+0[0-9a-f]+ <[^>]+> 1380      	asrs	r0, r0, #14
+0[0-9a-f]+ <[^>]+> 1445      	asrs	r5, r0, #17
+0[0-9a-f]+ <[^>]+> 13a8      	asrs	r0, r5, #14
+0[0-9a-f]+ <[^>]+> 4100      	asrs	r0, r0
+0[0-9a-f]+ <[^>]+> 4128      	asrs	r0, r5
+0[0-9a-f]+ <[^>]+> 4128      	asrs	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4969 	mov\.w	r9, r9, asr #17
+0[0-9a-f]+ <[^>]+> ea4f 39a9 	mov\.w	r9, r9, asr #14
+0[0-9a-f]+ <[^>]+> ea5f 4069 	movs\.w	r0, r9, asr #17
+0[0-9a-f]+ <[^>]+> ea4f 39a0 	mov\.w	r9, r0, asr #14
+0[0-9a-f]+ <[^>]+> fa40 f000 	asr\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa49 f909 	asr\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa59 f900 	asrs\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa40 f009 	asr\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa40 f005 	asr\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa51 f002 	asrs\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> ea5f 4070 	movs\.w	r0, r0, ror #17
+0[0-9a-f]+ <[^>]+> ea5f 30b0 	movs\.w	r0, r0, ror #14
+0[0-9a-f]+ <[^>]+> ea5f 4570 	movs\.w	r5, r0, ror #17
+0[0-9a-f]+ <[^>]+> ea5f 30b5 	movs\.w	r0, r5, ror #14
+0[0-9a-f]+ <[^>]+> 41c0      	rors	r0, r0
+0[0-9a-f]+ <[^>]+> 41e8      	rors	r0, r5
+0[0-9a-f]+ <[^>]+> 41e8      	rors	r0, r5
+0[0-9a-f]+ <[^>]+> ea4f 4979 	mov\.w	r9, r9, ror #17
+0[0-9a-f]+ <[^>]+> ea4f 39b9 	mov\.w	r9, r9, ror #14
+0[0-9a-f]+ <[^>]+> ea5f 4079 	movs\.w	r0, r9, ror #17
+0[0-9a-f]+ <[^>]+> ea4f 39b0 	mov\.w	r9, r0, ror #14
+0[0-9a-f]+ <[^>]+> fa60 f000 	ror\.w	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa69 f909 	ror\.w	r9, r9, r9
+0[0-9a-f]+ <[^>]+> fa79 f900 	rors\.w	r9, r9, r0
+0[0-9a-f]+ <[^>]+> fa60 f009 	ror\.w	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fa60 f005 	ror\.w	r0, r0, r5
+0[0-9a-f]+ <[^>]+> fa71 f002 	rors\.w	r0, r1, r2
+0[0-9a-f]+ <[^>]+> f7f0 8000 	smi	#0	; 0x0
+0[0-9a-f]+ <[^>]+> f7fd 8bca 	smi	#43981	; 0xabcd
+0[0-9a-f]+ <[^>]+> fb10 0000 	smlabb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0900 	smlabb	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb19 0000 	smlabb	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0009 	smlabb	r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb10 9000 	smlabb	r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb10 0020 	smlatb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0010 	smlabt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 0030 	smlatt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 0000 	smlawb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 0010 	smlawt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 0000 	smlad	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 0010 	smladx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 0000 	smlsd	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 0010 	smlsdx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 0000 	smmla	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 0010 	smmlar	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb60 0000 	smmls	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb60 0010 	smmlsr	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb70 0000 	usada8	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0080 	smlalbb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 9080 	smlalbb	r9, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0980 	smlalbb	r0, r9, r0, r0
+0[0-9a-f]+ <[^>]+> fbc9 0080 	smlalbb	r0, r0, r9, r0
+0[0-9a-f]+ <[^>]+> fbc0 0089 	smlalbb	r0, r0, r0, r9
+0[0-9a-f]+ <[^>]+> fbc0 00a0 	smlaltb	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 0090 	smlalbt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00b0 	smlaltt	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00c0 	smlald	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbc0 00d0 	smlaldx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbd0 00c0 	smlsld	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbd0 00d0 	smlsldx	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fbe0 0060 	umaal	r0, r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f000 	smulbb	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f900 	smulbb	r9, r0, r0
+0[0-9a-f]+ <[^>]+> fb19 f000 	smulbb	r0, r9, r0
+0[0-9a-f]+ <[^>]+> fb10 f009 	smulbb	r0, r0, r9
+0[0-9a-f]+ <[^>]+> fb10 f020 	smultb	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f010 	smulbt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb10 f030 	smultt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 f000 	smulwb	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb30 f010 	smulwt	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 f000 	smmul	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb50 f010 	smmulr	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 f000 	smuad	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb20 f010 	smuadx	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 f000 	smusd	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb40 f010 	smusdx	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fb70 f000 	usad8	r0, r0, r0
+0[0-9a-f]+ <[^>]+> f300 0000 	ssat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0000 	ssat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0000 	ssat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0900 	ssat	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f300 0011 	ssat	r0, #17, r0
+0[0-9a-f]+ <[^>]+> f309 0000 	ssat	r0, #0, r9
+0[0-9a-f]+ <[^>]+> f300 7000 	ssat	r0, #0, r0, lsl #28
+0[0-9a-f]+ <[^>]+> f320 00c0 	ssat	r0, #0, r0, asr #3
+0[0-9a-f]+ <[^>]+> f320 0000 	ssat16	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f320 0900 	ssat16	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f320 0009 	ssat16	r0, #9, r0
+0[0-9a-f]+ <[^>]+> f329 0000 	ssat16	r0, #0, r9
+0[0-9a-f]+ <[^>]+> f380 0000 	usat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0000 	usat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0000 	usat	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0900 	usat	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f380 0011 	usat	r0, #17, r0
+0[0-9a-f]+ <[^>]+> f389 0000 	usat	r0, #0, r9
+0[0-9a-f]+ <[^>]+> f380 7000 	usat	r0, #0, r0, lsl #28
+0[0-9a-f]+ <[^>]+> f3a0 00c0 	usat	r0, #0, r0, asr #3
+0[0-9a-f]+ <[^>]+> f3a0 0000 	usat16	r0, #0, r0
+0[0-9a-f]+ <[^>]+> f3a0 0900 	usat16	r9, #0, r0
+0[0-9a-f]+ <[^>]+> f3a0 0009 	usat16	r0, #9, r0
+0[0-9a-f]+ <[^>]+> f3a9 0000 	usat16	r0, #0, r9
+0[0-9a-f]+ <[^>]+> b240      	sxtb	r0, r0
+0[0-9a-f]+ <[^>]+> b240      	sxtb	r0, r0
+0[0-9a-f]+ <[^>]+> b245      	sxtb	r5, r0
+0[0-9a-f]+ <[^>]+> b268      	sxtb	r0, r5
+0[0-9a-f]+ <[^>]+> fa4f f182 	sxtb\.w	r1, r2
+0[0-9a-f]+ <[^>]+> fa4f f192 	sxtb\.w	r1, r2, ror #8
+0[0-9a-f]+ <[^>]+> fa4f f1a2 	sxtb\.w	r1, r2, ror #16
+0[0-9a-f]+ <[^>]+> fa4f f1b2 	sxtb\.w	r1, r2, ror #24
+0[0-9a-f]+ <[^>]+> fa2f f182 	sxtb16	r1, r2
+0[0-9a-f]+ <[^>]+> fa2f f889 	sxtb16	r8, r9
+0[0-9a-f]+ <[^>]+> b211      	sxth	r1, r2
+0[0-9a-f]+ <[^>]+> fa0f f889 	sxth\.w	r8, r9
+0[0-9a-f]+ <[^>]+> b2d1      	uxtb	r1, r2
+0[0-9a-f]+ <[^>]+> fa5f f889 	uxtb\.w	r8, r9
+0[0-9a-f]+ <[^>]+> fa3f f182 	uxtb16	r1, r2
+0[0-9a-f]+ <[^>]+> fa3f f889 	uxtb16	r8, r9
+0[0-9a-f]+ <[^>]+> b291      	uxth	r1, r2
+0[0-9a-f]+ <[^>]+> fa1f f889 	uxth\.w	r8, r9
+0[0-9a-f]+ <[^>]+> fa40 f080 	sxtab	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa40 f080 	sxtab	r0, r0, r0
+0[0-9a-f]+ <[^>]+> fa40 f990 	sxtab	r9, r0, r0, ror #8
+0[0-9a-f]+ <[^>]+> fa49 f0a0 	sxtab	r0, r9, r0, ror #16
+0[0-9a-f]+ <[^>]+> fa40 f0b9 	sxtab	r0, r0, r9, ror #24
+0[0-9a-f]+ <[^>]+> fa22 f183 	sxtab16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa02 f183 	sxtah	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa52 f183 	uxtab	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa32 f183 	uxtab16	r1, r2, r3
+0[0-9a-f]+ <[^>]+> fa12 f183 	uxtah	r1, r2, r3
+0[0-9a-f]+ <[^>]+> f89f 12aa 	ldrb\.w	r1, \[pc, #682\]	; 0+e02 <[^>]+>
+0[0-9a-f]+ <[^>]+> f89f 1155 	ldrb\.w	r1, \[pc, #341\]	; 0+cb1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 12aa 	ldrb\.w	r1, \[pc, #-682\]	; 0+8b6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f81f 1155 	ldrb\.w	r1, \[pc, #-341\]	; 0+a0f <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 12aa 	ldrsb\.w	r1, \[pc, #682\]	; 0+e12 <[^>]+>
+0[0-9a-f]+ <[^>]+> f99f 1155 	ldrsb\.w	r1, \[pc, #341\]	; 0+cc1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 12aa 	ldrsb\.w	r1, \[pc, #-682\]	; 0+8c6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f91f 1155 	ldrsb\.w	r1, \[pc, #-341\]	; 0+a1f <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 12aa 	ldrh\.w	r1, \[pc, #682\]	; 0+e22 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8bf 1155 	ldrh\.w	r1, \[pc, #341\]	; 0+cd1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 12aa 	ldrh\.w	r1, \[pc, #-682\]	; 0+8d6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f83f 1155 	ldrh\.w	r1, \[pc, #-341\]	; 0+a2f <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 12aa 	ldrsh\.w	r1, \[pc, #682\]	; 0+e32 <[^>]+>
+0[0-9a-f]+ <[^>]+> f9bf 1155 	ldrsh\.w	r1, \[pc, #341\]	; 0+ce1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 12aa 	ldrsh\.w	r1, \[pc, #-682\]	; 0+8e6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f93f 1155 	ldrsh\.w	r1, \[pc, #-341\]	; 0+a3f <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 12aa 	ldr\.w	r1, \[pc, #682\]	; 0+e42 <[^>]+>
+0[0-9a-f]+ <[^>]+> f8df 1155 	ldr\.w	r1, \[pc, #341\]	; 0+cf1 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 12aa 	ldr\.w	r1, \[pc, #-682\]	; 0+8f6 <[^>]+>
+0[0-9a-f]+ <[^>]+> f85f 1155 	ldr\.w	r1, \[pc, #-341\]	; 0+a4f <[^>]+>
+0[0-9a-f]+ <[^>]+> f200 0900 	addw	r9, r0, #0	; 0x0
+0[0-9a-f]+ <[^>]+> f60f 76ff 	addw	r6, pc, #4095	; 0xfff
+0[0-9a-f]+ <[^>]+> f6a9 2685 	subw	r6, r9, #2693	; 0xa85
+0[0-9a-f]+ <[^>]+> f2a9 567a 	subw	r6, r9, #1402	; 0x57a
+0[0-9a-f]+ <[^>]+> e8df f006 	tbb	\[pc, r6\]
+0[0-9a-f]+ <[^>]+> e8d0 f009 	tbb	\[r0, r9\]
+0[0-9a-f]+ <[^>]+> e8df f017 	tbh	\[pc, r7, lsl #1\]
+0[0-9a-f]+ <[^>]+> e8d0 f018 	tbh	\[r0, r8, lsl #1\]
+0[0-9a-f]+ <[^>]+> f84d 8d04 	str.w	r8, \[sp, #-4\]!
+0[0-9a-f]+ <[^>]+> f85d 8b04 	ldr.w	r8, \[sp\], #4
+0[0-9a-f]+ <[^>]+> e930 0580 	ldmdb	r0!, \{r7, r8, sl\}
+0[0-9a-f]+ <[^>]+> e920 0580 	stmdb	r0!, \{r7, r8, sl\}
diff --git a/gas/testsuite/gas/arm/thumb32.s b/gas/testsuite/gas/arm/thumb32.s
index be9f95f..7a60f51 100644
--- a/gas/testsuite/gas/arm/thumb32.s
+++ b/gas/testsuite/gas/arm/thumb32.s
@@ -42,10 +42,11 @@ encode_thumb32_immediate:
 	orr	r0, r1, #0xa5 << 1
 
 add_sub:
-	adds	r0, r0, #0	@ format 1
+	@ Should be format 1, Some have equivalent format 2 encodings
+	adds	r0, r0, #0
 	adds	r5, r0, #0
 	adds	r0, r5, #0
-	adds	r0, r0, #5
+	adds	r0, r2, #5
 
 	adds	r0, #129	@ format 2
 	adds	r0, r0, #129
@@ -83,6 +84,10 @@ add_sub:
 	add.w	r9, r0, #0
 	add.w	r0, r9, #0
 	add.w	r0, r0, #129
+	adds	r5, r3, #0x10000
+	add	r0, sp, #1
+	add	r9, sp, #0
+	add.w	sp, sp, #4
 
 	add.w	r0, r0, r0	@ T32 format 2
 	adds.w	r0, r0, r0
@@ -102,7 +107,7 @@ add_sub:
 	subs	r0, r0, #0	@ format 1
 	subs	r5, r0, #0
 	subs	r0, r5, #0
-	subs	r0, r0, #5
+	subs	r0, r2, #5
 
 	subs	r0, r0, #129
 	subs	r5, #8
@@ -118,6 +123,11 @@ add_sub:
 	subs	r8, r0		@ T32 format 2
 	subs	r0, r8
 	subs	r0, #260	@ T32 format 1
+	subs.w	r1, r2, #4
+	subs	r5, r3, #0x10000
+	sub	r1, sp, #4
+	sub	r9, sp, #0
+	sub.w	sp, sp, #4
 
 arit3:
 	.macro arit3 op ops opw opsw
@@ -197,27 +207,27 @@ branches:
 	@ bl, blx have no short form.
 	.balign 4
 1:
-	bra	beq
-	bra	bne
-	bra	bcs
-	bra	bhs
-	bra	bcc
-	bra	bul
-	bra	blo
-	bra	bmi
-	bra	bpl
-	bra	bvs
-	bra	bvc
-	bra	bhi
-	bra	bls
-	bra	bvc
-	bra	bhi
-	bra	bls
-	bra	bge
-	bra	blt
-	bra	bgt
-	bra	ble
-	bra	b
+	bra	beq.w
+	bra	bne.w
+	bra	bcs.w
+	bra	bhs.w
+	bra	bcc.w
+	bra	bul.w
+	bra	blo.w
+	bra	bmi.w
+	bra	bpl.w
+	bra	bvs.w
+	bra	bvc.w
+	bra	bhi.w
+	bra	bls.w
+	bra	bvc.w
+	bra	bhi.w
+	bra	bls.w
+	bra	bge.w
+	bra	blt.w
+	bra	bgt.w
+	bra	ble.w
+	bra	b.w
 	bra	bl
 	bra	blx
 	.balign 4
@@ -347,30 +357,7 @@ it:
 	it3 ne eq e e e
 
 ldst:
-	.macro	ls op
-	\op	r1, [r5]
-	\op	r1, [r5, #0x330]
-	\op	r1, [r5, #-0x30]
-	\op	r1, [r5], #0x30
-	\op	r1, [r5], #-0x30
-	\op	r1, [r5, #0x30]!
-	\op	r1, [r5, #-0x30]!
-	\op	r1, [r5, r4]
-	\op	r1, [r9, ip]
-	\op	r1, 1f
-	\op	r1, 1b
-	.endm
-1:
-	ls	ldrb
-	ls	ldrsb
-	ls	ldrh
-	ls	ldrsh
-	ls	ldr
 1:
-	ls	strb
-	ls	strh
-	ls	str
-
 	pld	[r5]
 	pld	[r5, #0x330]
 	pld	[r5, #-0x30]
@@ -402,8 +389,6 @@ ldst:
 	ldrt	r1, [r5]
 	ldrt	r1, [r5, #0x30]
 
-	.purgem ls
-
 ldxstx:
 	ldrexb	r1, [r4]
 	ldrexh	r1, [r4]
@@ -454,8 +439,8 @@ tst_teq_cmp_cmn_mov_mvn:
 	\opw	r0, r0
 	\ops	r9, r0
 	\opsw	r0, r9
-	\op	r0, #129
-	\op	r5, #129
+	\opw	r0, #129
+	\opw	r5, #129
 	.endm
 
 	mt	tst tsts tst.w tsts.w
author	Paul Brook <paul@codesourcery.com>	2005-09-06 16:59:24 +0000
committer	Paul Brook <paul@codesourcery.com>	2005-09-06 16:59:24 +0000
commit	0110f2b896d40a2ab1d19b85f7990d1c1a45792a (patch)
tree	0b9fef94c8cfa8d6ff26146fd8578e43db60f1b6 /gas
parent	9a64e435419869030e27d54f0433810b8b56d1ac (diff)
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