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| author | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2014-11-20 15:28:52 +0000 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2014-11-20 15:28:52 +0000 |
| commit | 5c47e525893b06db772d8b1c043233a173101c8c (patch) | |
| tree | d880e94983b0cae5a50739d8e1dbc8abc9f7f434 /gas/config | |
| parent | 0cfb07174869f3542a96619fb36a85398af35da2 (diff) | |
| download | gdb-5c47e525893b06db772d8b1c043233a173101c8c.zip gdb-5c47e525893b06db772d8b1c043233a173101c8c.tar.gz gdb-5c47e525893b06db772d8b1c043233a173101c8c.tar.bz2 | |
[AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.
* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
registers are in the GP register set. Adjust warnings. Use correct
field member for address register.
* testsuite/gas/aarch64/diagnostic.l: Update.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-aarch64.c | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 41378f5..c8824e5 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5490,7 +5490,7 @@ programmer_friendly_fixup (aarch64_instruction *instr) return TRUE; } -/* Check for loads and stores that will cause unpredictable behavior */ +/* Check for loads and stores that will cause unpredictable behavior. */ static void warn_unpredictable_ldst (aarch64_instruction *instr, char *str) @@ -5504,17 +5504,24 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) case ldst_imm9: case ldst_unscaled: case ldst_unpriv: - if (opnds[0].reg.regno == opnds[1].reg.regno + /* Loading/storing the base register is unpredictable if writeback. */ + if ((aarch64_get_operand_class (opnds[0].type) + == AARCH64_OPND_CLASS_INT_REG) + && opnds[0].reg.regno == opnds[1].addr.base_regno && opnds[1].addr.writeback) - as_warn (_("unpredictable register after writeback -- `%s'"), str); + as_warn (_("unpredictable transfer with writeback -- `%s'"), str); break; case ldstpair_off: case ldstnapair_offs: case ldstpair_indexed: - if ((opnds[0].reg.regno == opnds[2].reg.regno - || opnds[1].reg.regno == opnds[2].reg.regno) + /* Loading/storing the base register is unpredictable if writeback. */ + if ((aarch64_get_operand_class (opnds[0].type) + == AARCH64_OPND_CLASS_INT_REG) + && (opnds[0].reg.regno == opnds[2].addr.base_regno + || opnds[1].reg.regno == opnds[2].addr.base_regno) && opnds[2].addr.writeback) - as_warn (_("unpredictable register after writeback -- `%s'"), str); + as_warn (_("unpredictable transfer with writeback -- `%s'"), str); + /* Load operations must load different registers. */ if ((opcode->opcode & (1 << 22)) && opnds[0].reg.regno == opnds[1].reg.regno) as_warn (_("unpredictable load of register pair -- `%s'"), str); |