From 5c47e525893b06db772d8b1c043233a173101c8c Mon Sep 17 00:00:00 2001 From: Richard Earnshaw Date: Thu, 20 Nov 2014 15:28:52 +0000 Subject: [AArch64] Fix mis-detection of unpredictable load/store operations with FP regs. * config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer registers are in the GP register set. Adjust warnings. Use correct field member for address register. * testsuite/gas/aarch64/diagnostic.l: Update. --- gas/config/tc-aarch64.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) (limited to 'gas/config') diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 41378f5..c8824e5 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5490,7 +5490,7 @@ programmer_friendly_fixup (aarch64_instruction *instr) return TRUE; } -/* Check for loads and stores that will cause unpredictable behavior */ +/* Check for loads and stores that will cause unpredictable behavior. */ static void warn_unpredictable_ldst (aarch64_instruction *instr, char *str) @@ -5504,17 +5504,24 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) case ldst_imm9: case ldst_unscaled: case ldst_unpriv: - if (opnds[0].reg.regno == opnds[1].reg.regno + /* Loading/storing the base register is unpredictable if writeback. */ + if ((aarch64_get_operand_class (opnds[0].type) + == AARCH64_OPND_CLASS_INT_REG) + && opnds[0].reg.regno == opnds[1].addr.base_regno && opnds[1].addr.writeback) - as_warn (_("unpredictable register after writeback -- `%s'"), str); + as_warn (_("unpredictable transfer with writeback -- `%s'"), str); break; case ldstpair_off: case ldstnapair_offs: case ldstpair_indexed: - if ((opnds[0].reg.regno == opnds[2].reg.regno - || opnds[1].reg.regno == opnds[2].reg.regno) + /* Loading/storing the base register is unpredictable if writeback. */ + if ((aarch64_get_operand_class (opnds[0].type) + == AARCH64_OPND_CLASS_INT_REG) + && (opnds[0].reg.regno == opnds[2].addr.base_regno + || opnds[1].reg.regno == opnds[2].addr.base_regno) && opnds[2].addr.writeback) - as_warn (_("unpredictable register after writeback -- `%s'"), str); + as_warn (_("unpredictable transfer with writeback -- `%s'"), str); + /* Load operations must load different registers. */ if ((opcode->opcode & (1 << 22)) && opnds[0].reg.regno == opnds[1].reg.regno) as_warn (_("unpredictable load of register pair -- `%s'"), str); -- cgit v1.1