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| author | Joseph Myers <joseph@codesourcery.com> | 2009-02-03 18:16:04 +0000 |
|---|---|---|
| committer | Joseph Myers <joseph@codesourcery.com> | 2009-02-03 18:16:04 +0000 |
| commit | 52b6b6b972d426d44aa9ada61cf7f052d350a3cc (patch) | |
| tree | c4dbf41fdece504534dfb283a5f7a7036e4c4af7 /gas/config | |
| parent | a53fddce83af312fd3aa023c66b007b9e3937805 (diff) | |
| download | gdb-52b6b6b972d426d44aa9ada61cf7f052d350a3cc.zip gdb-52b6b6b972d426d44aa9ada61cf7f052d350a3cc.tar.gz gdb-52b6b6b972d426d44aa9ada61cf7f052d350a3cc.tar.bz2 | |
bfd:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
* archures.c (bfd_mach_mips_xlr): Define.
* bfd-in2.h: Regenerate.
* cpu-mips.c (I_xlr): Define.
(arch_info_struct): Add XLR entry.
* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
(mips_set_isa_flags): Handle bfd_mach_mips_xlr
(mips_mach_extensions): Add XLR entry.
binutils:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.
gas:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
M_MSGWAIT and M_MSGWAIT_T.
(mips_cpu_info_table): Add XLR entry.
* doc/c-mips.texi (-march): Document xlr.
gas/testsuite:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* gas/mips/mips.exp (xlr): New architecture.
(xlr-ext): Run test.
* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.
include/elf:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (E_MIPS_MACH_XLR): Define.
include/opcode:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips.h (INSN_XLR): Define.
(INSN_CHIP_MASK): Update.
(CPU_XLR): Define.
(OPCODE_IS_MEMBER): Update.
(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
opcodes:
2009-02-03 Sandip Matte <sandip@rmicorp.com>
* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
(mips_arch_choices): Add XLR entry.
* mips-opc.c (XLR): Define.
(mips_builtin_opcodes): Add XLR instructions.
Diffstat (limited to 'gas/config')
| -rw-r--r-- | gas/config/tc-mips.c | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 1d4193c..c139ea1 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -6042,6 +6042,43 @@ macro (struct mips_cl_insn *ip) macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg); break; + case M_MSGSND: + { + unsigned long temp = (treg << 16) | (0x01); + macro_build (NULL, "c2", "C", temp); + } + /* AT is not used, just return */ + return; + + case M_MSGLD: + { + unsigned long temp = (0x02); + macro_build (NULL, "c2", "C", temp); + } + /* AT is not used, just return */ + return; + + case M_MSGLD_T: + { + unsigned long temp = (treg << 16) | (0x02); + macro_build (NULL, "c2", "C", temp); + } + /* AT is not used, just return */ + return; + + case M_MSGWAIT: + macro_build (NULL, "c2", "C", 3); + /* AT is not used, just return */ + return; + + case M_MSGWAIT_T: + { + unsigned long temp = (treg << 16) | 0x03; + macro_build (NULL, "c2", "C", temp); + } + /* AT is not used, just return */ + return; + case M_J_A: /* The j instruction may not be used in PIC code, since it requires an absolute address. We convert it to a b @@ -15196,6 +15233,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] = /* Cavium Networks Octeon CPU core */ { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON }, + /* RMI Xlr */ + { "xlr", 0, ISA_MIPS64, CPU_XLR }, + /* End marker */ { NULL, 0, 0, 0 } }; |