bfd:

2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
	* archures.c (bfd_mach_mips_xlr): Define.
	* bfd-in2.h: Regenerate.
	* cpu-mips.c (I_xlr): Define.
	(arch_info_struct): Add XLR entry.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
	(mips_set_isa_flags): Handle bfd_mach_mips_xlr
	(mips_mach_extensions): Add XLR entry.

binutils:
2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.

gas:
2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
	M_MSGWAIT and M_MSGWAIT_T.
	(mips_cpu_info_table): Add XLR entry.
	* doc/c-mips.texi (-march): Document xlr.

gas/testsuite:
2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* gas/mips/mips.exp (xlr): New architecture.
	(xlr-ext): Run test.
	* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.

include/elf:
2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* mips.h (E_MIPS_MACH_XLR): Define.

include/opcode:
2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* mips.h (INSN_XLR): Define.
	(INSN_CHIP_MASK): Update.
	(CPU_XLR): Define.
	(OPCODE_IS_MEMBER): Update.
	(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.

opcodes:
2009-02-03  Sandip Matte  <sandip@rmicorp.com>

	* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
	(mips_arch_choices): Add XLR entry.
	* mips-opc.c (XLR): Define.
	(mips_builtin_opcodes): Add XLR instructions.

22 files changed, 237 insertions, 4 deletions

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 5b1b666..e028f1f 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,14 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr.
+	* archures.c (bfd_mach_mips_xlr): Define.
+	* bfd-in2.h: Regenerate.
+	* cpu-mips.c (I_xlr): Define.
+	(arch_info_struct): Add XLR entry.
+	* elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR.
+	(mips_set_isa_flags): Handle bfd_mach_mips_xlr
+	(mips_mach_extensions): Add XLR entry.
+
 2009-02-03  Eric B. Weddington  <eric.weddington@atmel.com>
 
 	* elf32-avr.c (avr_final_link_relocate): Allow avr25 to wraparound.
diff --git a/bfd/aoutx.h b/bfd/aoutx.h
index e808716..fccfdeb 100644
--- a/bfd/aoutx.h
+++ b/bfd/aoutx.h
@@ -795,6 +795,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
 	case bfd_mach_mipsisa64:
 	case bfd_mach_mipsisa64r2:
 	case bfd_mach_mips_sb1:
+	case bfd_mach_mips_xlr:
 	  /* FIXME: These should be MIPS3, MIPS4, MIPS16, MIPS32, etc.  */
 	  arch_flags = M_MIPS2;
 	  break;
diff --git a/bfd/archures.c b/bfd/archures.c
index c76e16e..f548ea2 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -175,6 +175,7 @@ DESCRIPTION
 .#define bfd_mach_mips_loongson_2f      3002
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
 .#define bfd_mach_mips_octeon		6501
+.#define bfd_mach_mips_xlr              887682   {* decimal 'XLR'  *}
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33
 .#define bfd_mach_mipsisa64             64
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index b79fa5c..994759d 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1801,6 +1801,7 @@ enum bfd_architecture
 #define bfd_mach_mips_loongson_2f      3002
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
 #define bfd_mach_mips_octeon           6501
+#define bfd_mach_mips_xlr              887682   /* decimal 'XLR'  */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33
 #define bfd_mach_mipsisa64             64
diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index 1102467..4c98821 100644
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -91,7 +91,8 @@ enum
   I_sb1,
   I_loongson_2e,
   I_loongson_2f,
-  I_mipsocteon
+  I_mipsocteon,
+  I_xlr
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -129,7 +130,8 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
   N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e",       FALSE, NN(I_loongson_2e)),
   N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",       FALSE, NN(I_loongson_2f)),
-  N (64, 64, bfd_mach_mips_octeon, "mips:octeon", FALSE, 0)
+  N (64, 64, bfd_mach_mips_octeon,"mips:octeon",  FALSE, NN(I_mipsocteon)),
+  N (64, 64, bfd_mach_mips_xlr, "mips:xlr",       FALSE, 0)
 };
 
 /* The default architecture is mips:3000, but with a machine number of
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 138d045..5a345f4 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -5879,6 +5879,9 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_OCTEON:
       return bfd_mach_mips_octeon;
 
+    case E_MIPS_MACH_XLR:
+      return bfd_mach_mips_xlr;
+
     default:
       switch (flags & EF_MIPS_ARCH)
 	{
@@ -10425,6 +10428,10 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_OCTEON;
       break;
 
+    case bfd_mach_mips_xlr:
+      val = E_MIPS_ARCH_64 | E_MIPS_MACH_XLR;
+      break;
+
     case bfd_mach_mipsisa32:
       val = E_MIPS_ARCH_32;
       break;
@@ -12120,6 +12127,7 @@ static const struct mips_mach_extension mips_mach_extensions[] = {
   /* MIPS64 extensions.  */
   { bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
   { bfd_mach_mips_sb1, bfd_mach_mipsisa64 },
+  { bfd_mach_mips_xlr, bfd_mach_mipsisa64 },
 
   /* MIPS V extensions.  */
   { bfd_mach_mipsisa64, bfd_mach_mips5 },
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 8c7f28a..0672246 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR.
+
 2009-02-03  H.J. Lu  <hongjiu.lu@intel.com>
 
 	* NEWS: Move --as-needed change to ...
diff --git a/binutils/readelf.c b/binutils/readelf.c
index d1b3e24..f1c2eb1 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2213,6 +2213,7 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
   	    case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
   	    case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
 	    case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
+	    case E_MIPS_MACH_XLR:  strcat (buf, ", xlr"); break;
 	    case 0:
 	    /* We simply ignore the field in this case to avoid confusion:
 	       MIPS ELF does not specify EF_MIPS_MACH, it is a GNU
diff --git a/gas/ChangeLog b/gas/ChangeLog
index f8f14bb..2cf0914 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T,
+	M_MSGWAIT and M_MSGWAIT_T.
+	(mips_cpu_info_table): Add XLR entry.
+	* doc/c-mips.texi (-march): Document xlr.
+
 2009-01-29  Eric B. Weddington  <eric.weddington@atmel.com>
 
 	* config/tc-avr.c (mcu_types): Add ata6289.
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 1d4193c..c139ea1 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -6042,6 +6042,43 @@ macro (struct mips_cl_insn *ip)
 	macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
       break;
 
+    case M_MSGSND:
+      {
+	unsigned long temp = (treg << 16) | (0x01);
+	macro_build (NULL, "c2", "C", temp);
+      }
+      /* AT is not used, just return */
+      return;
+
+    case M_MSGLD:
+      {
+	unsigned long temp = (0x02);
+	macro_build (NULL, "c2", "C", temp);
+      }
+      /* AT is not used, just return */
+      return;
+
+    case M_MSGLD_T:
+      {
+	unsigned long temp = (treg << 16) | (0x02);
+	macro_build (NULL, "c2", "C", temp);
+      }
+      /* AT is not used, just return */
+      return;
+
+    case M_MSGWAIT:
+      macro_build (NULL, "c2", "C", 3);
+      /* AT is not used, just return */
+      return;
+
+    case M_MSGWAIT_T:
+      {
+	unsigned long temp = (treg << 16) | 0x03;
+	macro_build (NULL, "c2", "C", temp);
+      }
+      /* AT is not used, just return */
+      return;
+
     case M_J_A:
       /* The j instruction may not be used in PIC code, since it
 	 requires an absolute address.  We convert it to a b
@@ -15196,6 +15233,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   /* Cavium Networks Octeon CPU core */
   { "octeon",	      0,      ISA_MIPS64R2,   CPU_OCTEON },
 
+  /* RMI Xlr */
+  { "xlr",	      0,      ISA_MIPS64,     CPU_XLR },
+
   /* End marker */
   { NULL, 0, 0, 0 }
 };
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 2acdbf3..91bd822 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -276,7 +276,8 @@ sb1,
 sb1a,
 loongson2e,
 loongson2f,
-octeon
+octeon,
+xlr
 @end quotation
 
 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index d24486b..a324383 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* gas/mips/mips.exp (xlr): New architecture.
+	(xlr-ext): Run test.
+	* gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New.
+
 2009-02-03  Maxim Kuvyrkov  <maxim@codesourcery.com>
 
 	* gas/m68k/tls-gd-3.d, gas/m68k/tls-gd-3.s: New test.
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 913b44d..b213aba 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -364,6 +364,8 @@ mips_arch_create sb1 	64	mips64	{ mips3d } \
 mips_arch_create octeon 64	mips64r2 {} \
 			{ -march=octeon -mtune=octeon } { -mmips:octeon } \
 			{ mips64octeon*-*-* }
+mips_arch_create xlr 	64	mips64	{} \
+			{ -march=xlr -mtune=xlr } { -mmips:xlr }
 
 #
 # And now begin the actual tests!  VxWorks uses RELA rather than REL
@@ -582,6 +584,7 @@ if { [istarget mips*-*-vxworks*] } {
 	run_dump_test "mips64-mdmx"
 	run_dump_test "sb1-ext-mdmx"
 	run_dump_test "sb1-ext-ps"
+	run_dump_test "xlr-ext"
     }
 
     run_dump_test "relax"
diff --git a/gas/testsuite/gas/mips/xlr-ext.d b/gas/testsuite/gas/mips/xlr-ext.d
new file mode 100644
index 0000000..72046f0
--- /dev/null
+++ b/gas/testsuite/gas/mips/xlr-ext.d
@@ -0,0 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:xlr
+#name: XLRs native MIPS64 extensions
+#as: -march=xlr
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 3c000000 	lui	zero,0x0
+0+0004 <[^>]*> 8c010001 	lw	at,1\(zero\)
+0+0008 <[^>]*> 8c020002 	lw	v0,2\(zero\)
+0+000c <[^>]*> 70221838 	daddwc	v1,at,v0
+0+0010 <[^>]*> 70230010 	ldaddw	v1,at
+0+0014 <[^>]*> 70230011 	ldaddwu	v1,at
+0+0018 <[^>]*> 70230012 	ldaddd	v1,at
+0+001c <[^>]*> 70230014 	swapw	v1,at
+0+0020 <[^>]*> 70230015 	swapwu	v1,at
+0+0024 <[^>]*> 4a000003 	c2	0x3
+0+0028 <[^>]*> 4a000002 	c2	0x2
+0+002c <[^>]*> 4a000001 	c2	0x1
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/xlr-ext.s b/gas/testsuite/gas/mips/xlr-ext.s
new file mode 100644
index 0000000..b92708a
--- /dev/null
+++ b/gas/testsuite/gas/mips/xlr-ext.s
@@ -0,0 +1,27 @@
+# Source file used to test XLR's assembler instructions
+
+	.set 	noreorder
+	.set 	noat
+
+	.globl	text_label	.text
+text_label:	
+
+	lui     $0, 0x00
+	lw 	    $1, 0x01
+	lw 	    $2, 0x02
+	
+	daddwc	$3, $1, $2
+	
+	ldaddw	$3, $1
+	ldaddwu	$3, $1
+	ldaddd	$3, $1
+
+	swapw	$3, $1
+	swapwu	$3, $1
+	
+	msgwait
+	msgld	$0
+	msgsnd	$0
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.space  8
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 0a4f94c..ab3bb8f 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* mips.h (E_MIPS_MACH_XLR): Define.
+
 2009-02-03  Maxim Kuvyrkov  <maxim@codesourcery.com>
 
 	* m68k.h: Map TLS relocations to numbers.
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 4ec7816..609da56 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -214,6 +214,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_4111	0x00880000
 #define E_MIPS_MACH_SB1         0x008a0000
 #define E_MIPS_MACH_OCTEON	0x008b0000
+#define E_MIPS_MACH_XLR     	0x008c0000
 #define E_MIPS_MACH_5400	0x00910000
 #define E_MIPS_MACH_5500	0x00980000
 #define E_MIPS_MACH_9000	0x00990000
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 0ebadf7..e256e6e 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,11 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* mips.h (INSN_XLR): Define.
+	(INSN_CHIP_MASK): Update.
+	(CPU_XLR): Define.
+	(OPCODE_IS_MEMBER): Update.
+	(M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
+
 2009-01-28  Doug Evans  <dje@google.com>
 
 	* opcode/i386.h: Add multiple inclusion protection.
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index e7cfdb9..a4017a1 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -543,7 +543,7 @@ static const unsigned int mips_isa_table[] =
   { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK		  0xc3ff0800
+#define INSN_CHIP_MASK		  0xc3ff0820
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON		  0x00000800
@@ -592,6 +592,8 @@ static const unsigned int mips_isa_table[] =
 #define INSN_LOONGSON_2E          0x40000000
 /* ST Microelectronics Loongson 2F.  */
 #define INSN_LOONGSON_2F          0x80000000
+/* RMI Xlr instruction */
+#define INSN_XLR              	  0x00000020
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -644,6 +646,7 @@ static const unsigned int mips_isa_table[] =
 #define CPU_LOONGSON_2E 3001
 #define CPU_LOONGSON_2F 3002
 #define CPU_OCTEON	6501
+#define CPU_XLR     	887682   	/* decimal 'XLR'   */
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
@@ -677,6 +680,7 @@ static const unsigned int mips_isa_table[] =
          && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
      || (cpu == CPU_OCTEON						\
 	 && ((insn)->membership & INSN_OCTEON) != 0)			\
+     || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0)        \
      || 0)	/* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.
@@ -809,6 +813,11 @@ enum
   M_LWR_A,
   M_LWR_AB,
   M_LWU_AB,
+  M_MSGSND,
+  M_MSGLD,
+  M_MSGLD_T,
+  M_MSGWAIT,
+  M_MSGWAIT_T,
   M_MOVE,
   M_MUL,
   M_MUL_I,
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index c0f4593..a8c53c6 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,10 @@
+2009-02-03  Sandip Matte  <sandip@rmicorp.com>
+
+	* mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define.
+	(mips_arch_choices): Add XLR entry.
+	* mips-opc.c (XLR): Define.
+	(mips_builtin_opcodes): Add XLR instructions.
+
 2009-02-03  Carlos O'Donell  <carlos@codesourcery.com>
 
 	* Makefile.am: Add install-pdf target.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 759e2aa..984d368 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -319,6 +319,56 @@ static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
   { 29, 3, "c0_datahi_d"	},
 };
 
+/* Xlr cop0 register names.  */
+static const char * const mips_cp0_names_xlr[32] = {
+  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
+  "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
+  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
+  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
+  "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
+  "c0_xcontext",  "$21",          "$22",          "c0_debug",
+  "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
+  "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
+};
+
+/* XLR's CP0 Select Registers.  */
+
+static const struct mips_cp0sel_name mips_cp0sel_names_xlr[] = {
+  {  9, 6, "c0_extintreq"       },
+  {  9, 7, "c0_extintmask"      },
+  { 15, 1, "c0_ebase"           },
+  { 16, 1, "c0_config1"         },
+  { 16, 2, "c0_config2"         },
+  { 16, 3, "c0_config3"         },
+  { 16, 7, "c0_procid2"         },
+  { 18, 1, "c0_watchlo,1"       },
+  { 18, 2, "c0_watchlo,2"       },
+  { 18, 3, "c0_watchlo,3"       },
+  { 18, 4, "c0_watchlo,4"       },
+  { 18, 5, "c0_watchlo,5"       },
+  { 18, 6, "c0_watchlo,6"       },
+  { 18, 7, "c0_watchlo,7"       },
+  { 19, 1, "c0_watchhi,1"       },
+  { 19, 2, "c0_watchhi,2"       },
+  { 19, 3, "c0_watchhi,3"       },
+  { 19, 4, "c0_watchhi,4"       },
+  { 19, 5, "c0_watchhi,5"       },
+  { 19, 6, "c0_watchhi,6"       },
+  { 19, 7, "c0_watchhi,7"       },
+  { 25, 1, "c0_perfcnt,1"       },
+  { 25, 2, "c0_perfcnt,2"       },
+  { 25, 3, "c0_perfcnt,3"       },
+  { 25, 4, "c0_perfcnt,4"       },
+  { 25, 5, "c0_perfcnt,5"       },
+  { 25, 6, "c0_perfcnt,6"       },
+  { 25, 7, "c0_perfcnt,7"       },
+  { 27, 1, "c0_cacheerr,1"      },
+  { 27, 2, "c0_cacheerr,2"      },
+  { 27, 3, "c0_cacheerr,3"      },
+  { 28, 1, "c0_datalo"          },
+  { 29, 1, "c0_datahi"          }
+};
+
 static const char * const mips_hwr_names_numeric[32] =
 {
   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
@@ -466,6 +516,12 @@ const struct mips_arch_choice mips_arch_choices[] =
     ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
     mips_hwr_names_numeric },
 
+  { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
+    ISA_MIPS64 | INSN_XLR,
+    mips_cp0_names_xlr,
+    mips_cp0sel_names_xlr, ARRAY_SIZE (mips_cp0sel_names_xlr),
+    mips_hwr_names_numeric },
+
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
   { "",		1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index b397c37..12a8cbe 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -123,6 +123,7 @@
 #define N54	INSN_5400
 #define N55	INSN_5500
 #define IOCT	INSN_OCTEON
+#define XLR     INSN_XLR
 
 #define G1      (T3             \
                  )
@@ -559,6 +560,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
 {"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
 {"daddu",   "t,r,I",	0,    (int) M_DADDU_I,	INSN_MACRO,		0,		I3	},
+{"daddwc",  "d,s,t", 	0x70000038, 0xfc0007ff, WR_d|RD_s|RD_t|WR_C0|RD_C0,	0,	XLR	},
 {"dbreak",  "",		0x7000003f, 0xffffffff,	0,			0,		N5	},
 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 	0,		I64|N55 },
@@ -747,6 +749,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ld",	    "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3	},
 {"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		0,		I1	},
 {"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1	},
+{"ldaddw",  "t,b",	0x70000010, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
+{"ldaddwu", "t,b",	0x70000011, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
+{"ldaddd",  "t,b",	0x70000012, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
 {"ldc1",    "T,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
 {"ldc1",    "E,o(b)",	0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,	0,		I2	},
 {"ldc1",    "T,A(b)",	0,    (int) M_LDC1_AB,	INSN_MACRO,		INSN2_M_FP_D,	I2	},
@@ -881,6 +886,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mflo",    "d",	0x00000012, 0xffff07ff,	WR_d|RD_LO,		0,		I1	},
 {"mflo",    "d,9",	0x00000012, 0xff9f07ff, WR_d|RD_LO,		0,		D32	},
 {"mflhxu",  "d",	0x00000052, 0xffff07ff,	WR_d|MOD_HILO,		0,		SMT	},
+{"mfcr",    "t,s",	0x70000018, 0xfc00ffff, WR_t,			0,		XLR 	},
 {"min.ob",  "X,Y,Q",	0x78000006, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"min.ob",  "D,S,T",	0x4ac00006, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"min.ob",  "D,S,T[e]",	0x48000006, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -923,6 +929,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msachiu", "d,s,t",	0x000003d9, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
 /* move is at the top of the table.  */
 {"msgn.qh", "X,Y,Q",	0x78200000, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
+{"msgsnd",  "t",	0,    (int) M_MSGSND,	INSN_MACRO,		0,             XLR	},
+{"msgld",   "", 	0,    (int) M_MSGLD,	INSN_MACRO,		0,             XLR	},
+{"msgld",   "t",	0,    (int) M_MSGLD_T,	INSN_MACRO,		0,             XLR	},
+{"msgwait", "", 	0,    (int) M_MSGWAIT,	INSN_MACRO,		0,             XLR	},
+{"msgwait", "t",	0,    (int) M_MSGWAIT_T,INSN_MACRO,		0,             XLR	},
 {"msub.d",  "D,R,S,T",	0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,		I4_33	},
 {"msub.d",	"D,S,T",	0x46200019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
 {"msub.d",	"D,S,T",	0x72200019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
@@ -956,6 +967,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtlo",    "s",	0x00000013, 0xfc1fffff,	RD_s|WR_LO,		0,		I1	},
 {"mtlo",    "s,7",	0x00000013, 0xfc1fe7ff, RD_s|WR_LO,		0,		D32	},
 {"mtlhx",   "s",	0x00000053, 0xfc1fffff,	RD_s|MOD_HILO,		0,		SMT	},
+{"mtcr",    "t,s",      0x70000019, 0xfc00ffff, RD_t,			0,		XLR	},
 {"mtm0",    "s",	0x70000008, 0xfc1fffff, RD_s,			0,		IOCT	},
 {"mtm1",    "s",	0x7000000c, 0xfc1fffff, RD_s,			0,		IOCT	},
 {"mtm2",    "s",	0x7000000d, 0xfc1fffff, RD_s,			0,		IOCT	},
@@ -1298,6 +1310,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,	0,		I5_33|N55},
 {"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
 {"sw",      "t,A(b)",	0,    (int) M_SW_AB,	INSN_MACRO,		0,		I1	},
+{"swapw",   "t,b",	0x70000014, 0xfc00ffff, SM|RD_t|WR_t|RD_b,	0,		XLR	},
+{"swapwu",  "t,b",	0x70000015, 0xfc00ffff, SM|RD_t|WR_t|RD_b,	0,		XLR	},
+{"swapd",   "t,b",	0x70000016, 0xfc00ffff, SM|RD_t|WR_t|RD_b,	0,		XLR	},
 {"swc0",    "E,o(b)",	0xe0000000, 0xfc000000,	SM|RD_C0|RD_b,		0,		I1	},
 {"swc0",    "E,A(b)",	0,    (int) M_SWC0_AB,	INSN_MACRO,		0,		I1	},
 {"swc1",    "T,o(b)",	0xe4000000, 0xfc000000,	SM|RD_T|RD_b|FP_S,	0,		I1	},