From 25236d63fdb138e24cb34aa6c513ae8de2dac7b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Thu, 21 Jul 2022 00:26:29 +0200 Subject: RISC-V: Add support for literal instruction arguments MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces support for arbitrary literal instruction arguments, that are not encoded in the opcode. A typical use case for this feature would be an instruction that applies an implicit shift by a constant value on an immediate (that is a real operand). With this patch it is possible to make this shift visible in the dissasembly and support such artificial parameter as part of the asssembly code. Co-developed-by: Lifang Xia Signed-off-by: Christoph Müllner --- gas/config/tc-riscv.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'gas/config') diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 00e4635..d9f63b1 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1279,6 +1279,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) switch (*++oparg) { + case 'l': /* Literal. */ + oparg += strcspn(oparg, ",") - 1; + break; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ goto use_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ @@ -3310,6 +3313,13 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, switch (*++oparg) { + case 'l': /* Literal. */ + n = strcspn (++oparg, ","); + if (strncmp (oparg, asarg, n)) + as_bad (_("unexpected literal (%s)"), asarg); + oparg += n - 1; + asarg += n; + continue; case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ sign = true; goto parse_imm; -- cgit v1.1