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2025-08-31Daily bump.GCC Administrator1-0/+13
2025-08-29Revert "Fix _Decimal128 arithmetic error under FE_UPWARD."liuhongt5-568/+215
This reverts commit 50064b2898edfb83bc37f2597a35cbd3c1c853e3.
2025-08-30Daily bump.GCC Administrator1-0/+10
2025-08-28Fix _Decimal128 arithmetic error under FE_UPWARD.liuhongt5-215/+568
libgcc/config/libbid/ChangeLog: PR target/120691 * bid128_div.c: Fix _Decimal128 arithmetic error under FE_UPWARD. * bid128_rem.c: Ditto. * bid128_sqrt.c: Ditto. * bid64_div.c (bid64_div): Ditto. * bid64_sqrt.c (bid64_sqrt): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr120691.c: New test.
2025-08-21pru: libgcc: Add software implementation for multiplicationDimitar Dimitrov5-0/+124
For cores without a hardware multiplier, set respective optabs with library functions which use software implementation of multiplication. The implementation was copied from the RL78 backend. gcc/ChangeLog: * config/pru/pru.cc (pru_init_libfuncs): Set softmpy libgcc functions for optab multiplication entries if TARGET_OPT_MUL option is not set. libgcc/ChangeLog: * config/pru/libgcc-eabi.ver: Add __pruabi_softmpyi and __pruabi_softmpyll symbols. * config/pru/t-pru: Add softmpy source files. * config/pru/pru-softmpy.h: New file. * config/pru/softmpyi.c: New file. * config/pru/softmpyll.c: New file. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2025-08-13LoongArch: Add support for _BitInt [PR117599]Yang Yujie3-0/+31
This patch adds support for C23's _BitInt for LoongArch. From the LoongArch psABI[1]: > _BitInt(N) objects are stored in little-endian order in memory > and are signed by default. > > For N ≤ 64, a _BitInt(N) object have the same size and alignment > of the smallest fundamental integral type that can contain it. > The unused high-order bits within this containing type are filled > with sign or zero extension of the N-bit value, depending on whether > the _BitInt(N) object is signed or unsigned. The _BitInt(N) object > propagates its signedness to the containing type and is laid out > in a register or memory as an object of this type. > > For N > 64, _BitInt(N) objects are implemented as structs of 64-bit > integer chunks. The number of chunks is the smallest even integer M > so that M * 64 ≥ N. These objects are of the same size of the struct > containing the chunks, but always have 16-byte alignment. If there > are unused bits in the highest-ordered chunk that contains used > bits, they are defined as the sign- or zero- extension of the used > bits depending on whether the _BitInt(N) object is signed or > unsigned. If an entire chunk is unused, its bits are undefined. [1] https://github.com/loongson/la-abi-specs PR target/117599 gcc/ChangeLog: * config/loongarch/loongarch.h: Define a PROMOTE_MODE case for small _BitInts. * config/loongarch/loongarch.cc (loongarch_promote_function_mode): Same. (loongarch_bitint_type_info): New function. (TARGET_C_BITINT_TYPE_INFO): Declare. libgcc/ChangeLog: * config/loongarch/t-softfp-tf: Enable _BitInt helper functions. * config/loongarch/t-loongarch: Same. * config/loongarch/libgcc-loongarch.ver: New file. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bitint-alignments.c: New test. * gcc.target/loongarch/bitint-args.c: New test. * gcc.target/loongarch/bitint-sizes.c: New test.
2025-08-08aarch64: libgcc: Honor disable-werror [PR117600]Christophe Lyon1-1/+1
In commit r15-4417-g71c7b446b98aa5, I made -werror mandatory when building libgcc for aarch64. While it achieved its goal (make us fix problems unnoticed so far), there has a been a lot of debate because it couldn't be disabled easily. This patch adds support for --enable-werror/--disable-werror in libgcc, defaulting to --enable-werror for aarch64. Tested on non-bootstrap builds on aarch64-linux-gnu (with -Wno-prio-ctor-dtor removed in order to get an error). libgcc/ChangeLog: PR libgcc/117600 * Makefile.in (WERROR): New. * config/aarch64/t-aarch64: Handle WERROR. * configure: Regenerate. * configure.ac: Add support for --enable-werror.
2025-08-07s390: Add _BitInt supportStefan Schulze Frielinghaus2-0/+15
gcc/ChangeLog: * config/s390/s390.cc (print_operand): Allow arbitrary wide_int constants for _BitInt. (s390_bitint_type_info): Implement target hook TARGET_C_BITINT_TYPE_INFO. libgcc/ChangeLog: * config/s390/libgcc-glibc.ver: Export _BitInt support functions. * config/s390/t-softfp (softfp_extras): Add fixtfbitint floatbitinttf. gcc/testsuite/ChangeLog: * gcc.target/s390/bitint-1.c: New test. * gcc.target/s390/bitint-2.c: New test. * gcc.target/s390/bitint-3.c: New test. * gcc.target/s390/bitint-4.c: New test.
2025-08-07s390: libgcc: Enable soft-fpStefan Schulze Frielinghaus3-0/+151
Enable soft-fp for -m64 only. libgcc/ChangeLog: * config.host: Include makefiles t-softfp for -m64. * config/s390/sfp-exceptions.c: New file. * config/s390/sfp-machine.h: New file. * config/s390/t-softfp: New file.
2025-07-31libgcc: Update FMV features to latest ACLE spec 2024Q4Wilco Dijkstra1-28/+6
Update FMV features to latest ACLE spec of 2024Q4 - several features have been removed or merged. Add FMV support for CSSC and MOPS. Preserve the ordering in enum CPUFeatures. gcc: * common/config/aarch64/cpuinfo.h: Remove unused features, add FEAT_CSSC and FEAT_MOPS. * config/aarch64/aarch64-option-extensions.def: Remove FMV support for RPRES, use PULL rather than AES, add FMV support for CSSC and MOPS. libgcc: * config/aarch64/cpuinfo.c (__init_cpu_features_constructor): Remove unused features, add support for CSSC and MOPS.
2025-07-31libgcc: Cleanup HWCAP defines in cpuinfo.cWilco Dijkstra1-197/+49
Cleanup HWCAP defines - rather than including hwcap.h and then repeating it using ifndef, just define the HWCAPs we need exactly as in hwcap.h. libgcc: * config/aarch64/cpuinfo.c: Cleanup HWCAP defines.
2025-07-31aarch64: Stop using sys/ifunc.h header in libatomic and libgccYury Khrustalev1-9/+37
This optional header is used to bring in the definition of the struct __ifunc_arg_t type. Since it has been added to glibc only recently, the previous implementation had to check whether this header is present and, if not, it provide its own definition. This creates dead code because either one of these two parts would not be tested. The ABI specification for ifunc resolvers allows to create own ABI-compatible definition for this type, which is the right way of doing it. In addition to improving consistency, the new approach also helps with addition of new fields to struct __ifunc_arg_t type without the need to work-around situations when the definition imported from the header lacks these new fields. ABI allows to define as many hwcap fields in this struct as needed, provided that at runtime we only access the fields that are permitted by the _size value. gcc/ * config/aarch64/aarch64.cc (build_ifunc_arg_type): Add new fields _hwcap3 and _hwcap4. libatomic/ * config/linux/aarch64/host-config.h (__ifunc_arg_t): Remove sys/ifunc.h and add new fields _hwcap3 and _hwcap4. libgcc/ * config/aarch64/cpuinfo.c (__ifunc_arg_t): Likewise. (__init_cpu_features): obtain and assign values for the fields _hwcap3 and _hwcap4. (__init_cpu_features_constructor): check _size in the arg argument.
2025-07-17aarch64: Adapt unwinder to linux's SME signal behaviourRichard Sandiford1-1/+107
SME uses a lazy save system to manage ZA. The idea is that, if a function with ZA state wants to call a "normal" function, it can leave its state in ZA and instead set up a lazy save buffer. If, unexpectedly, that normal function contains a nested use of ZA, that nested use of ZA must commit the lazy save first. This lazy save system uses a special system register called TPIDR2_EL0. See: https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#66the-za-lazy-saving-scheme for details. The ABI specifies that, on entry to an exception handler, the following things must be true: * PSTATE.SM must be 0 (the processor must be in non-streaming mode) * PSTATE.ZA must be 0 (ZA must be off) * TPIDR2_EL0 must be 0 (there must be no uncommitted lazy save) This is normally done by making _Unwind_RaiseException & friends commit any lazy save before they unwind. This also has the side effect of ensuring that TPIDR2_EL0 is never left pointing to a lazy save buffer that has been unwound. However, things get more complicated with signals. If: (a) a signal is raised while ZA is dormant (that is, while there is an uncommitted lazy save); (b) the signal handler throws an exception; and (c) that exception is caught outside the signal handler something must ensure that the lazy save from (a) is committed. This would be simple if the signal handler was entered with ZA and TPIDR2_EL0 intact. However, for various good reasons that are out of scope here, this is not done. Instead, Linux now clears both TPIDR2_EL0 and PSTATE.ZA before entering a signal handler, see: https://lore.kernel.org/all/20250417190113.3778111-1-mark.rutland@arm.com/ for details. Therefore, it is the unwinder that must simulate a commit of the lazy save from (a). It can do this by reading the previous values of TPIDR2_EL0 and ZA from the sigcontext. The SME-related sigcontext structures were only added to linux's asm/sigcontext.h relatively recently and we can't rely on GCC being built against such recent kernel header files. The patch therefore uses defines relevant macros if they are not defined and provide types that comply with ABI layout of the corresponding linux types. The patch includes some ugly casting in an attempt to support big-endian ILP32, even though SME on big-endian ILP32 linux should never be a thing. We can remove it if we also remove ILP32 support from GCC. Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com> Reviewed-by: Tamar Christina <tamar.christina@arm.com> gcc/ * doc/sourcebuild.texi (aarch64_sme_hw): Document. gcc/testsuite/ * lib/target-supports.exp (add_options_for_aarch64_sme) (check_effective_target_aarch64_sme_hw): New procedures. * g++.target/aarch64/sme/sme_throw_1.C: New test. * g++.target/aarch64/sme/sme_throw_2.C: Likewise. libgcc/ * config/aarch64/linux-unwind.h (aarch64_fallback_frame_state): If a signal was raised while there was an uncommitted lazy save, commit the save as part of the unwind process.
2025-07-16Daily bump.GCC Administrator1-0/+5
2025-07-15libgcc: Fix aarch64 buildAndrew Pinski1-0/+1
For aarch64, libgcc is built with -Werror, after the latest -Wunused-but-set* commit (r16-2258-g0eac9cfee8cb0b21d), a new warning showed up: ``` ../../../gcc/libgcc/config/libbid/bid_binarydecimal.c: In function ‘__binary32_to_bid128’: ../../../gcc/libgcc/config/libbid/bid_binarydecimal.c:130:31: error: variable ‘c3’ set but not used [-Werror=unused-but-set-variable=] 130 | { unsigned long long c0,c1,c2,c3; \ | ^~ ../../../gcc/libgcc/config/libbid/bid_binarydecimal.c:146842:5: note: in expansion of macro ‘__mul_10x256_to_256’ 146842 | __mul_10x256_to_256 (z.w[5], z.w[4], z.w[3], z.w[2], z.w[5], z.w[4], | ^~~~~~~~~~~~~~~~~~~ ``` This fixes it by casting c3 to void after the last __mul_10x64 in __mul_10x256_to_256 macro to mark it as being "used". libgcc/config/libbid/ChangeLog: * bid_binarydecimal.c (__mul_10x256_to_256): Mark c3 as being used. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-05-28Daily bump.GCC Administrator1-0/+15
2025-05-27libgcc: Add DPD support + fix big-endian support of _BitInt <-> dfp conversionsJakub Jelinek1-2/+0
The following patch fixes FAIL: gcc.dg/dfp/bitint-1.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-2.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-3.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-4.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-5.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-6.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-8.c (test for excess errors) FAIL: gcc.dg/dfp/int128-1.c (test for excess errors) FAIL: gcc.dg/dfp/int128-2.c (test for excess errors) FAIL: gcc.dg/dfp/int128-4.c (test for excess errors) on s390x-linux (with the 3 not yet posted patches). The patch does multiple things: 1) the routines were written for the DFP BID (binary integer decimal) format which is used on all arches but powerpc*/s390* (those use DPD - densely packed decimal format); as most of the code is actually the same for both BID and DPD formats, I haven't copied the sources + slightly modified them, but added the DPD support directly, + renaming of the exported symbols from __bid_* prefixed to __dpd_* prefixed that GCC expects on the DPD targets 2) while testing that I've found some big-endian issues in the existing support 3) testing also revealed that in some cases __builtin_clzll (~msb) was called with msb set to all ones, so invoking UB; apparently on aarch64 and x86 we were lucky and got some value that happened to work well, but that wasn't the case on s390x For 1), the patch uses two ~ 2KB tables to speed up the decoding/encoding. I haven't found such tables in what is added into libgcc.a, though they are in libdecnumber/bid/bid2dpd_dpd2bid.h, but there they are just huge and next to other huge tables - there is d2b which is like __dpd_d2bbitint in the patch but it uses 64-bit entries rather than 16-bit, then there is d2b2 with 64-bit entries like in d2b all multiplied by 1000, then d2b3 similarly multiplied by 1000000, then d2b4 similarly multiplied by 1000000000, then d2b5 similarly multiplied by 1000000000000ULL and d2b6 similarly multipled by 1000000000000000ULL. Arguably it can save some of the multiplications, but on the other side accesses memory which is unlikely in the caches, and the 2048 bytes in the patch vs. 24 times more for d2b is IMHO significant. For b2d, libdecnumber/bid/bid2dpd_dpd2bid.h has again b2d table like __dpd_b2dbitint in the patch, except that it has 64-bit entries rather than 16-bit (this time 1000 entries), but then has b2d2 which has the same entries shifted left by 10, then b2d3 shifted left by 20, b2d4 shifted left by 30 and b2d5 shifted left by 40. I can understand for d2b paying memory cost to speed up multiplications, but don't understand paying extra 4 * 8 * 1000 bytes (+ 6 * 1000 bytes for b2d not using ushort) just to avoid shifts. 2025-05-27 Jakub Jelinek <jakub@redhat.com> * config/t-softfp (softfp_bid_list): Don't guard with $(enable_decimal_float) == bid. * soft-fp/bitint.h (__bid_pow10bitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_pow10bitint. (__dpd_d2bbitint, __dpd_b2dbitint): Declare. * soft-fp/bitintpow10.c (__dpd_d2bbitint, __dpd_b2dbitint): New variables. * soft-fp/fixsdbitint.c (__bid_fixsdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdbitint. Add DPD support. Fix big-endian support. * soft-fp/fixddbitint.c (__bid_fixddbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddbitint. Add DPD support. Fix big-endian support. * soft-fp/fixtdbitint.c (__bid_fixtdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdbitint. Add DPD support. Fix big-endian support. * soft-fp/fixsdti.c (__bid_fixsdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdbitint. (__bid_fixsdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdti. * soft-fp/fixddti.c (__bid_fixddbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddbitint. (__bid_fixddti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddti. * soft-fp/fixtdti.c (__bid_fixtdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdbitint. (__bid_fixtdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdti. * soft-fp/fixunssdti.c (__bid_fixsdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdbitint. (__bid_fixunssdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixunssdti. * soft-fp/fixunsddti.c (__bid_fixddbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddbitint. (__bid_fixunsddti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixunsddti. * soft-fp/fixunstdti.c (__bid_fixtdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdbitint. (__bid_fixunstdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixunstdti. * soft-fp/floatbitintsd.c (__bid_floatbitintsd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintsd. Add DPD support. Avoid calling __builtin_clzll with 0 argument. Fix big-endian support. * soft-fp/floatbitintdd.c (__bid_floatbitintdd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintdd. Add DPD support. Avoid calling __builtin_clzll with 0 argument. Fix big-endian support. * soft-fp/floatbitinttd.c (__bid_floatbitinttd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitinttd. Add DPD support. Avoid calling __builtin_clzll with 0 argument. Fix big-endian support. * soft-fp/floattisd.c (__bid_floatbitintsd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintsd. (__bid_floattisd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floattisd. * soft-fp/floattidd.c (__bid_floatbitintdd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintdd. (__bid_floattidd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floattidd. * soft-fp/floattitd.c (__bid_floatbitinttd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitinttd. (__bid_floattitd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floattitd. * soft-fp/floatuntisd.c (__bid_floatbitintsd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintsd. (__bid_floatuntisd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatuntisd. * soft-fp/floatuntidd.c (__bid_floatbitintdd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintdd. (__bid_floatuntidd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatuntidd. * soft-fp/floatuntitd.c (__bid_floatbitinttd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitinttd. (__bid_floatuntitd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatuntitd.
2025-05-27AVR: target/120442 - Support f7_fdim / fdiml in LibF7.Georg-Johann Lay6-10/+39
Add Support for fdiml. PR target/120442 libgcc/config/avr/libf7/ * libf7-common.mk (LIBF_C_PARTS, m_ddd): Add fdim. * libf7.h (f7_fdim): New proto. * libf7.c (f7_fdim): New function. * f7renames.sh (f7_fdim): Add rename. * f7-wraps.h: Rebuild * f7-renames.h: Rebuild
2025-05-27AVR: target/120441 - Fix f7_exp for |x| ≥ 512.Georg-Johann Lay1-2/+2
f7_exp limited exponents to 512, but 1023 * ln2 ≈ 709, hence 1024 is a correct limit. libgcc/config/avr/libf7/ PR target/120441 * libf7.c (f7_exp): Limit aa->expo to 10 (not to 9).
2025-05-25Enable mcf thread model for aarch64-*-mingw*.LIU Hao1-0/+0
This is similar to d6d7afcdbc04adb0ec42a44b2d7e05600945af42 about the posix and win32 thread model. Signed-off-by: LIU Hao <lh_mouse@126.com> Signed-off-by: Jonathan Yong <10walls@gmail.com> libgcc/ChangeLog: * config.host: Enable mcf thread model for aarch64-*-mingw*. * config/i386/t-mingw-mcfgthread: Move to... * config/mingw/t-mingw-mcfgthread: ...here.
2025-05-21vxworks: libgcc: include string.h for memsetAlexandre Oliva1-0/+1
gthr-vxworks-thread.c calls memset in __ghtread_cond_signal, but it fails ot include <string.h>, where this function is declared, and GCC 14 rejects calls of undeclared functions. Include the required header. for libgcc/ChangeLog * config/gthr-vxworks-thread.c: Include string.h for memset.
2025-05-20libgcc: Move bitint support exports to x86/aarch64 specific map filesJakub Jelinek4-0/+24
When adding _BitInt support I was hoping all or most of arches would implement it already for GCC 14. That didn't happen and with new hosts adding support for _BitInt for GCC 16 (s390x-linux and as was posted today loongarch-linux too), we need the _BitInt support functions exported on those arches at GCC_16.0.0 rather than GCC_14.0.0 which shouldn't be changed anymore. The following patch does that. Both arches were already exporting some of the _BitInt related symbols in their specific map files, this just moves the remaining ones there as well. 2025-05-20 Jakub Jelinek <jakub@redhat.com> * libgcc-std.ver.in (GCC_14.0.0): Remove bitint related exports from here. * config/i386/libgcc-glibc.ver (GCC_14.0.0): Add them here. * config/i386/libgcc-darwin.ver (GCC_14.0.0): Likewise. * config/i386/libgcc-sol2.ver (GCC_14.0.0): Likewise. * config/aarch64/libgcc-softfp.ver (GCC_14.0.0): Likewise.
2025-05-17[PATCH] libgcc SH: fix alignment for relaxationOleg Endo1-1/+2
From 6462f1e6a2565c5d4756036d9bc2f39dce9bd768 Mon Sep 17 00:00:00 2001 From: QBos07 <qubos@outlook.de> Date: Sat, 10 May 2025 16:56:28 +0000 Subject: [PATCH] libgcc SH: fix alignment for relaxation when relaxation is enabled we can not infer the alignment from the position as that may change. This should not change non-relaxed builds as its allready aligned there. This was the missing piece to building an entire toolchain with -mrelax Credit goes to Oleg Endo: https://sourceware.org/bugzilla/show_bug.cgi?id=3298#c4 libgcc/ * config/sh/lib1funcs.S (ashiftrt_r4_32): Increase alignment. (movemem): Force alignment of the mova intruction.
2025-05-16Daily bump.GCC Administrator1-0/+6
2025-05-14Update libbid according to the latest Intel Decimal Floating-Point Math Library.liuhongt1-53/+68
The Intel Decimal Floating-Point Math Library is available as open-source on Netlib[1]. [1] https://www.netlib.org/misc/intel/ libgcc/config/libbid/ChangeLog: * bid128_string.c (MIN_DIGITS): New macro. (bid128_from_string): Bug fix. Conversion from very long input string to decimal.
2025-04-25GCN, nvptx offloading: Host/device compatibility: Itanium C++ ABI, DSO ↵Thomas Schwinge2-0/+48
Object Destruction API [PR119853, PR119854] '__dso_handle' for '__cxa_atexit', '__cxa_finalize'. See <https://itanium-cxx-abi.github.io/cxx-abi/abi.html#dso-dtor>. PR target/119853 PR target/119854 libgcc/ * config/gcn/crt0.c (_fini_array): Call '__GCC_offload___cxa_finalize'. * config/nvptx/gbl-ctors.c (__static_do_global_dtors): Likewise. libgomp/ * target-cxa-dso-dtor.c: New. * config/accel/target-cxa-dso-dtor.c: Likewise. * Makefile.am (libgomp_la_SOURCES): Add it. * Makefile.in: Regenerate. * testsuite/libgomp.c++/target-cdtor-1.C: New. * testsuite/libgomp.c++/target-cdtor-2.C: Likewise.
2025-04-19[PATCH v2] sh: libgcc: Implement fenv rouding and exceptions for soft-fp ↵Jiaxun Yang1-0/+46
[PR118257] Implement fenv rouding and exceptions for soft-fp, as per SuperH arch specification. No new tests required, as it's already covered by many torture tests with fenv_exceptions. PR target/118257 libgcc/ChangeLog: * config/sh/sfp-machine.h (_FPU_GETCW): Implement with builtin. (_FPU_SETCW): Likewise. (FP_EX_ENABLE_SHIFT): Derive from arch spec. (FP_EX_CAUSE_SHIFT): Likewise. (FP_RND_MASK): Likewise. (FP_EX_INVALID): Likewise. (FP_EX_DIVZERO): Likewise. (FP_EX_ALL): Likewise. (FP_EX_OVERFLOW): Likewise. (FP_EX_UNDERFLOW): Likewise. (FP_EX_INEXACT): Likewise. (_FP_DECL_EX): Declear default FCSR value. (FP_RND_NEAREST): Derive from arch spec. (FP_RND_ZERO): Likewise. (FP_INIT_ROUNDMODE): Likewise. (FP_ROUNDMODE): Likewise. (FP_TRAPPING_EXCEPTIONS): Likewise. (FP_HANDLE_EXCEPTIONS): Implement with _FPU_SETCW.
2025-04-19[PATCH v2] sh: Correct NaN signalling bit and propagation rules [PR111814]Jiaxun Yang1-13/+23
As per architecture, SuperH has a reversed NaN signalling bit vs IEEE754-2008, it also has a NaN propgation rule similar to MIPS style. Use mips style float format and mode for all float types, and correct sfp-machine header accordingly. PR target/111814 gcc/ChangeLog: * config/sh/sh-modes.def (RESET_FLOAT_FORMAT): Use mips format. (FLOAT_MODE): Use mips mode. libgcc/ChangeLog: * config/sh/sfp-machine.h (_FP_NANFRAC_B): Reverse signaling bit. (_FP_NANFRAC_H): Likewise. (_FP_NANFRAC_S): Likewise. (_FP_NANFRAC_D): Likewise. (_FP_NANFRAC_Q): Likewise. (_FP_KEEPNANFRACP): Enable for target. (_FP_QNANNEGATEDP): Enable for target. (_FP_CHOOSENAN): Port from MIPS. gcc/testsuite/ChangeLog: * gcc.target/sh/pr111814.c: New test.
2025-04-14GCN, nvptx: Support '-mfake-exceptions', and use it for offloading ↵Thomas Schwinge2-0/+12
compilation [PR118794] With '-mfake-exceptions' enabled, the user-visible behavior in presence of exception handling constructs changes such that the compile-time 'sorry, unimplemented: exception handling not supported' is skipped, code generation proceeds, and instead, exception handling constructs 'abort' at run time. (..., or don't, if they're in dead code.) PR target/118794 gcc/ * config/gcn/gcn.opt (-mfake-exceptions): Support. * config/nvptx/nvptx.opt (-mfake-exceptions): Likewise. * config/gcn/gcn.md (define_expand "exception_receiver"): Use it. * config/nvptx/nvptx.md (define_expand "exception_receiver"): Likewise. * config/gcn/mkoffload.cc (main): Set it. * config/nvptx/mkoffload.cc (main): Likewise. * config/nvptx/nvptx.cc (nvptx_assemble_integer) <in_section == exception_section>: Special handling for 'SYMBOL_REF's. * except.cc (expand_dw2_landing_pad_for_region): Don't generate bogus code for (default) '#define EH_RETURN_DATA_REGNO(N) INVALID_REGNUM'. libgcc/ * config/gcn/unwind-gcn.c (_Unwind_Resume): New. * config/nvptx/unwind-nvptx.c (_Unwind_Resume): Likewise. gcc/testsuite/ * g++.target/gcn/exceptions-bad_cast-2.C: Set '-mno-fake-exceptions'. * g++.target/gcn/exceptions-pr118794-1.C: Likewise. * g++.target/gcn/exceptions-throw-2.C: Likewise. * g++.target/nvptx/exceptions-bad_cast-2.C: Likewise. * g++.target/nvptx/exceptions-pr118794-1.C: Likewise. * g++.target/nvptx/exceptions-throw-2.C: Likewise. * g++.target/gcn/exceptions-bad_cast-2_-mfake-exceptions.C: New. * g++.target/gcn/exceptions-pr118794-1_-mfake-exceptions.C: Likewise. * g++.target/gcn/exceptions-throw-2_-mfake-exceptions.C: Likewise. * g++.target/nvptx/exceptions-bad_cast-2_-mfake-exceptions.C: Likewise. * g++.target/nvptx/exceptions-pr118794-1_-mfake-exceptions.C: Likewise. * g++.target/nvptx/exceptions-throw-2_-mfake-exceptions.C: Likewise. libgomp/ * testsuite/libgomp.c++/target-exceptions-bad_cast-2-offload-sorry-GCN.C: Set '-foffload-options=-mno-fake-exceptions'. * testsuite/libgomp.c++/target-exceptions-bad_cast-2-offload-sorry-nvptx.C: Likewise. * testsuite/libgomp.c++/target-exceptions-pr118794-1-offload-sorry-GCN.C: Likewise. * testsuite/libgomp.c++/target-exceptions-pr118794-1-offload-sorry-nvptx.C: Likewise. * testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-GCN.C: Likewise. * testsuite/libgomp.c++/target-exceptions-throw-2-offload-sorry-nvptx.C: Likewise. * testsuite/libgomp.oacc-c++/exceptions-bad_cast-2-offload-sorry-GCN.C: Likewise. * testsuite/libgomp.oacc-c++/exceptions-bad_cast-2-offload-sorry-nvptx.C: Likewise. * testsuite/libgomp.oacc-c++/exceptions-throw-2-offload-sorry-GCN.C: Likewise. * testsuite/libgomp.oacc-c++/exceptions-throw-2-offload-sorry-nvptx.C: Likewise. * testsuite/libgomp.c++/target-exceptions-bad_cast-2.C: Adjust. * testsuite/libgomp.c++/target-exceptions-pr118794-1.C: Likewise. * testsuite/libgomp.c++/target-exceptions-throw-2.C: Likewise. * testsuite/libgomp.oacc-c++/exceptions-bad_cast-2.C: Likewise. * testsuite/libgomp.oacc-c++/exceptions-throw-2.C: Likewise. * testsuite/libgomp.c++/target-exceptions-throw-2-O0.C: New.
2025-04-14Fix implementation of Win32 thread model for C++ modulesEric Botcazou1-35/+46
This applies the same magic to config/i386/gthr-win32.h that was applied to gthr-posix.h (https://gcc.gnu.org/cgit/gcc/commit/?id=6a4d1c374eed17) for the sake of C++ modules. libgcc/ PR target/119673 * config/i386/gthr-win32.h (__GTHREAD_ALWAYS_INLINE): New macro. (__GTHREAD_INLINE): Likewise. (__GTHR_W32_InterlockedCompareExchange): Delete. (__gthread_active_p): Mark as __GTHREAD_INLINE instead of static inline. (__gthread_create): Likewise. (__gthread_join): Likewise. (__gthread_self): Likewise. (__gthread_detach): Likewise. (__gthread_equal): Likewise. (__gthread_yield): Likewise. (__gthread_once): Likewise. (__gthread_key_create): Likewise. (__gthread_key_delete): Likewise. (__gthread_getspecific): Likewise. (__gthread_setspecific): Likewise. (__gthread_mutex_init_function): Likewise. (__gthread_mutex_destroy): Likewise. (__gthread_mutex_lock): Likewise. (__gthread_mutex_trylock): Likewise. (__gthread_mutex_timedlock): Likewise. (__gthread_mutex_unlock): Likewise. (__gthread_recursive_mutex_trylock): Likewise. (__gthread_cond_init_function): Likewise. (__gthread_cond_broadcast): Likewise. (__gthread_cond_signal): Likewise. (__gthread_cond_wait): Likewise. (__gthread_cond_timedwait): Likewise. (__GTHREAD_WIN32_INLINE): Likewise. (__GTHREAD_WIN32_COND_INLINE): Likewise. (__gthread_recursive_mutex_init_function): Likewise. (__gthread_recursive_mutex_destroy): Likewise. (__gthread_recursive_mutex_lock): Likewise. (__gthread_recursive_mutex_unlock): Likewise. (__gthread_cond_destroy): Likewise. (__gthread_cond_wait_recursive): Likewise.
2025-04-08GCN, nvptx: Define '_Unwind_RaiseException', '_Unwind_Resume_or_Rethrow'Thomas Schwinge2-0/+28
This resolves GCN: ld: error: undefined symbol: _Unwind_RaiseException >>> referenced by eh_throw.cc:93 ([...]/source-gcc/libstdc++-v3/libsupc++/eh_throw.cc:93) >>> eh_throw.o:(__cxa_throw) in archive /srv/data/tschwinge/amd-instinct2/gcc/build/submit-light-target_gcn/build-gcc/amdgcn-amdhsa/gfx908/libstdc++-v3/src/.libs/libstdc++.a [...] collect2: error: ld returned 1 exit status ..., and/or: ld: error: undefined symbol: _Unwind_Resume_or_Rethrow >>> referenced by eh_throw.cc:129 ([...]/source-gcc/libstdc++-v3/libsupc++/eh_throw.cc:129) >>> eh_throw.o:(__cxa_rethrow) in archive /srv/data/tschwinge/amd-instinct2/gcc/build/submit-light-target_gcn/build-gcc/amdgcn-amdhsa/gfx908/libstdc++-v3/src/.libs/libstdc++.a [...] collect2: error: ld returned 1 exit status ..., and nvptx: unresolved symbol _Unwind_RaiseException collect2: error: ld returned 1 exit status ..., or: unresolved symbol _Unwind_Resume_or_Rethrow collect2: error: ld returned 1 exit status For both GCN, nvptx, this each progresses ~25 'check-gcc-c++', and ~10 'check-target-libstdc++-v3' test cases: [-FAIL:-]{+PASS:+} [...] (test for excess errors) ..., with (if applicable, for most of them): [-UNRESOLVED:-]{+PASS:+} [...] [-compilation failed to produce executable-]{+execution test+} ..., or some 'FAIL: [...] execution test' where these test cases now FAIL when attempting to use these interfaces, or, if applicable, FAIL due to run-time 'GCC/nvptx: sorry, unimplemented: dynamic stack allocation not supported'. libgcc/ * config/gcn/unwind-gcn.c (_Unwind_RaiseException) (_Unwind_Resume_or_Rethrow): New. * config/nvptx/unwind-nvptx.c (_Unwind_RaiseException) (_Unwind_Resume_or_Rethrow): Likewise.
2025-04-08GCN, nvptx: Define '_Unwind_DeleteException'Thomas Schwinge2-0/+14
This resolves GCN: ld: error: undefined symbol: _Unwind_DeleteException >>> referenced by eh_catch.cc:109 ([...]/source-gcc/libstdc++-v3/libsupc++/eh_catch.cc:109) >>> eh_catch.o:(__cxa_end_catch) in archive [...]/build-gcc/amdgcn-amdhsa/libstdc++-v3/src/.libs/libstdc++.a [...] collect2: error: ld returned 1 exit status ..., and nvptx: unresolved symbol _Unwind_DeleteException collect2: error: ld returned 1 exit status For both GCN, nvptx, this each progresses ~100 'check-gcc-c++', and ~500 'check-target-libstdc++-v3' test cases: [-FAIL:-]{+PASS:+} [...] (test for excess errors) ..., with (if applicable, for most of them): [-UNRESOLVED:-]{+PASS:+} [...] [-compilation failed to produce executable-]{+execution test+} ..., or just a few 'FAIL: [...] execution test' where these test cases now FAIL for unrelated reasons, or, if applicable, FAIL due to run-time 'GCC/nvptx: sorry, unimplemented: dynamic stack allocation not supported'. libgcc/ * config/gcn/unwind-gcn.c (_Unwind_DeleteException): New. * config/nvptx/unwind-nvptx.c (_Unwind_DeleteException): Likewise.
2025-04-07nvptx: Support '-mfake-ptx-alloca': defer failure to run-time 'alloca' usageThomas Schwinge2-1/+40
Follow-up to commit 1146410c0feb0e82c689b1333fdf530a2b34dc2b "nvptx: Support '-mfake-ptx-alloca'". '-mfake-ptx-alloca' is applicable only for configurations where PTX 'alloca' is not supported, where target libraries are built with it enabled (that is, libstdc++, libgfortran). This change progresses: [-FAIL:-]{+PASS:+} g++.dg/tree-ssa/pr20458.C -std=gnu++17 (test for excess errors) [-UNRESOLVED:-]{+PASS:+} g++.dg/tree-ssa/pr20458.C -std=gnu++17 [-compilation failed to produce executable-]{+execution test+} [-FAIL:-]{+PASS:+} g++.dg/tree-ssa/pr20458.C -std=gnu++26 (test for excess errors) [-UNRESOLVED:-]{+PASS:+} g++.dg/tree-ssa/pr20458.C -std=gnu++26 [-compilation failed to produce executable-]{+execution test+} UNSUPPORTED: g++.dg/tree-ssa/pr20458.C -std=gnu++98: exception handling not supported ..., and "enables" a few test cases: FAIL: g++.old-deja/g++.other/sibcall1.C -std=gnu++17 (test for excess errors) [Etc.] FAIL: g++.old-deja/g++.other/unchanging1.C -std=gnu++17 (test for excess errors) [Etc.] ..., which now (unrelatedly to 'alloca', and in the same way as configurations where PTX 'alloca' is supported) FAIL due to: unresolved symbol _Unwind_DeleteException collect2: error: ld returned 1 exit status Most importantly, it progresses ~830 libstdc++ test cases: [-FAIL:-]{+PASS:+} [...] (test for excess errors) ..., with (if applicable, for most of them): [-UNRESOLVED:-]{+PASS:+} [...] [-compilation failed to produce executable-]{+execution test+} ..., or just a few 'FAIL: [...] execution test' where these test cases also FAIL in configurations where PTX 'alloca' is supported, or ~120 instances of 'FAIL: [...] execution test' due to run-time 'GCC/nvptx: sorry, unimplemented: dynamic stack allocation not supported'. This change also resolves the cases noted in commit bac2d8a246892334e24dfa7d62be0cd0648c5606 "nvptx: Build libgfortran with '-mfake-ptx-alloca' [PR107635]": | With '-mfake-ptx-alloca', libgfortran again succeeds to build, and compared | to before, we've got only a small number of regressions due to nvptx 'ld' | complaining about 'unresolved symbol __GCC_nvptx__PTX_alloca_not_supported': | | [-PASS:-]{+FAIL:+} gfortran.dg/coarray/codimension_2.f90 -fcoarray=lib -O2 -lcaf_single (test for excess errors) [-FAIL:-]{+PASS:+} gfortran.dg/coarray/codimension_2.f90 -fcoarray=lib -O2 -lcaf_single (test for excess errors) | [-PASS:-]{+FAIL:+} gfortran.dg/coarray/event_4.f08 -fcoarray=lib -O2 -lcaf_single (test for excess errors) | [-PASS:-]{+UNRESOLVED:+} gfortran.dg/coarray/event_4.f08 -fcoarray=lib -O2 -lcaf_single [-execution test-]{+compilation failed to produce executable+} [-FAIL:-]{+PASS:+} gfortran.dg/coarray/event_4.f08 -fcoarray=lib -O2 -lcaf_single (test for excess errors) [-UNRESOLVED:-]{+PASS:+} gfortran.dg/coarray/event_4.f08 -fcoarray=lib -O2 -lcaf_single [-compilation failed to produce executable-]{+execution test+} | [-PASS:-]{+FAIL:+} gfortran.dg/coarray/fail_image_2.f08 -fcoarray=lib -O2 -lcaf_single (test for excess errors) | [-PASS:-]{+UNRESOLVED:+} gfortran.dg/coarray/fail_image_2.f08 -fcoarray=lib -O2 -lcaf_single [-execution test-]{+compilation failed to produce executable+} [-FAIL:-]{+PASS:+} gfortran.dg/coarray/fail_image_2.f08 -fcoarray=lib -O2 -lcaf_single (test for excess errors) [-UNRESOLVED:-]{+PASS:+} gfortran.dg/coarray/fail_image_2.f08 -fcoarray=lib -O2 -lcaf_single [-compilation failed to produce executable-]{+execution test+} | [-PASS:-]{+FAIL:+} gfortran.dg/coarray/proc_pointer_assign_1.f90 -fcoarray=lib -O2 -lcaf_single (test for excess errors) | [-PASS:-]{+UNRESOLVED:+} gfortran.dg/coarray/proc_pointer_assign_1.f90 -fcoarray=lib -O2 -lcaf_single [-execution test-]{+compilation failed to produce executable+} [-FAIL:-]{+PASS:+} gfortran.dg/coarray/proc_pointer_assign_1.f90 -fcoarray=lib -O2 -lcaf_single (test for excess errors) [-UNRESOLVED:-]{+PASS:+} gfortran.dg/coarray/proc_pointer_assign_1.f90 -fcoarray=lib -O2 -lcaf_single [-compilation failed to produce executable-]{+execution test+} | [-PASS:-]{+FAIL:+} gfortran.dg/coarray_43.f90 -O (test for excess errors) [-FAIL:-]{+PASS:+} gfortran.dg/coarray_43.f90 -O (test for excess errors) ..., and further progresses: [-FAIL:-]{+PASS:+} gfortran.dg/coarray_lib_comm_1.f90 -O0 (test for excess errors) [-UNRESOLVED:-]{+FAIL:+} gfortran.dg/coarray_lib_comm_1.f90 -O0 [-compilation failed to produce executable-]{+execution test+} [Etc.] ..., which now (unrelatedly to 'alloca', and in the same way as configurations where PTX 'alloca' is supported) FAILs due to: error : Prototype doesn't match for '_gfortran_caf_transfer_between_remotes' in 'input file 9 at offset 159897', first defined in 'input file 9 at offset 159897' error : Prototype doesn't match for '_gfortran_caf_stop_numeric' in 'input file 9 at offset 159897', first defined in 'input file 9 at offset 159897' nvptx-run: cuLinkAddData failed: device kernel image is invalid (CUDA_ERROR_INVALID_SOURCE, 300) gcc/ * config/nvptx/nvptx.opt (-mfake-ptx-alloca): Update. gcc/testsuite/ * gcc.target/nvptx/alloca-2-O0_-mfake-ptx-alloca.c: Adjust. libgcc/ * config/nvptx/alloca.c: New. * config/nvptx/t-nvptx (LIB2ADD): Add it.
2025-04-07AVRrc: Tweak __[u]mulhisi3.Georg-Johann Lay1-49/+22
When MUL is not available, then the __umulhisi3 and __mulhisi3 functions can use __mulhisi3_helper. This improves code size, stack footprint and runtime on AVRrc. libgcc/ * config/avr/lib1funcs.S (__mulhisi3, __umulhisi3): Use __mulhisi3_helper for better performance on AVRrc.
2025-04-06AVRrc: Support 8-bit and 16-bit fixed-point arith in libgcc.Georg-Johann Lay3-33/+106
With some minor changes, 8-bit and 16-bit fixed-point operations can be supported on the reduced core. libgcc/ * config/avr/t-avr (LIB1ASMFUNCS): Add (and remove from FUNCS_notiny): _mulhisi3, _umulhisi3, _mulqq3, _mulhq3, _muluhq3, _mulha3, _muluha3 _muluha3_round, _usmuluha3, _ssmulha3, _divqq3, _udivuqq3, _divqq_helper, _divhq3, _udivuhq3. _divha3 _udivuha3, _ssneg_2, _ssabs_1, _ssabs_2, _mask1, _ret, _roundqq3 _rounduqq3, _round_s2, _round_u2, _round_2_const, _addmask_2. * config/avr/lib1funcs.S (__umulhisi3, __mulhisi3): Make work on AVRrc. * config/avr/lib1funcs-fixed.S: Build 8-bit and 16-bit functions on AVRrc, too.
2025-04-05AVR: Speed up __umulhisi3 for small devices with MUL.Georg-Johann Lay1-8/+1
__umulhisi3 had an "rcall 1f" to save 6 bytes, which is an unreasonable size gain vs. cycle cost. Just use the same code on all devices with MUL, irrespective of program memory size. libgcc/ * config/avr/lib1funcs.S (__umulhisi3) [Have MUL]: Reduce call depth by 1.
2025-03-23Daily bump.GCC Administrator1-0/+5
2025-03-22AVR: libgcc: Properly exclude object files for AVRrc.Georg-Johann Lay2-10/+17
There are many objects / functions that are not available on AVRrc, the reduced core. The old way to exclude some objects for AVRrc did not work properly since it tested for MULTIFLAGS. This does not work for, say MULTIFLAGS = "-mmcu=avrtiny -mdouble=64". This patch uses $(findstring avrtiny,$(MULTIDIR)) in the condition. libgcc/ * config/avr/t-avr (LIB1ASMFUNCS, LIB2FUNCS_EXCLUDE): Properly handle avrtiny. libgcc/config/avr/libf7/ * t-libf7 (libgcc-objects): Only add objects when building for non-AVRrc.
2025-03-14Revert "GCN, nvptx: Basic '__cxa_guard_{acquire,abort,release}' for C++ ↵Thomas Schwinge2-6/+0
static local variables support" GCN, nvptx now has libstdc++-v3/libsupc++ proper. This reverts commit c0bf7ea189ecf252152fe15134f70f576bcd20b2.
2025-03-13libgcc: Remove PREDRES and LS64 from AArch64 cpuinfoWilco Dijkstra1-19/+0
Change AArch64 cpuinfo to follow the latest updates to the FMV spec [1]: Remove FEAT_PREDRES and FEAT_LS64*. Preserve the ordering in enum CPUFeatures. [1] https://github.com/ARM-software/acle/pull/382 gcc: * common/config/aarch64/cpuinfo.h: Remove FEAT_PREDRES and FEAT_LS64*. * config/aarch64/aarch64-option-extensions.def: Remove FMV support for PREDRES. libgcc: * config/aarch64/cpuinfo.c (__init_cpu_features_constructor): Remove FEAT_PREDRES and FEAT_LS64* support.
2025-03-01[PATCH] H8/300, libgcc: PR target/114222 For HImode call internal ffs() ↵Jan Dubiec2-0/+43
implementation instead of an external one When INT_TYPE_SIZE < BITS_PER_WORD gcc emits a call to an external ffs() implementation instead of a call to "__builtin_ffs()" – see function init_optabs() in <SRCROOT>/gcc/optabs-libfuncs.cc. External ffs() (which is usually the one from newlib) in turn calls __builtin_ffs() what causes infinite recursion and stack overflow. This patch overrides default gcc bahaviour for H8/300H (and newer) and provides a generic ffs() implementation for HImode. PR target/114222 gcc/ChangeLog: * config/h8300/h8300.cc (h8300_init_libfuncs): For HImode override calls to external ffs() (from newlib) with calls to __ffshi2() from libgcc. The implementation of ffs() in newlib calls __builtin_ffs() what causes infinite recursion and finally a stack overflow. libgcc/ChangeLog: * config/h8300/t-h8300: Add __ffshi2(). * config/h8300/ffshi2.c: New file.
2025-02-18libgcc: i386/linux-unwind.h: always rely on sys/ucontext.hRoman Kagan1-7/+0
When gcc is built for x86_64-linux-musl target, stack unwinding from within signal handler stops at the innermost signal frame. The reason for this behaviro is that the signal trampoline is not accompanied with appropiate CFI directives, and the fallback path in libgcc to recognize it by the code sequence is only enabled for glibc except 2.0. The latter is motivated by the lack of sys/ucontext.h in that glibc version. Given that all relevant libc-s ship sys/ucontext.h for over a decade, and that other arches aren't shy of unconditionally using it, follow suit and remove the preprocessor condition, too. libgcc/ChangeLog: * config/i386/linux-unwind.h: Remove preprocessor condition to enable fallback path for all libc-s. Signed-off-by: Roman Kagan <rkagan@amazon.de>
2025-02-17LoongArch: Fix the issue of function jump out of range caused by crtbeginS.o ↵Lulu Cheng1-0/+6
[PR118844]. Due to the presence of R_LARCH_B26 in /usr/lib/gcc/loongarch64-linux-gnu/14/crtbeginS.o, its addressing range is [PC-128MiB, PC+128MiB-4]. This means that when the code segment size exceeds 128MB, linking with lld will definitely fail (ld will not fail because the order of the two is different). The linking order: lld: crtbeginS.o + .text + .plt ld : .plt + crtbeginS.o + .text To solve this issue, add '-mcmodel=extreme' when compiling crtbeginS.o. PR target/118844 libgcc/ChangeLog: * config/loongarch/t-crtstuff: Add '-mcmodel=extreme' to CRTSTUFF_T_CFLAGS_S.
2025-02-11RISC-V: Drop __riscv_vendor_feature_bitsYangyu Chen1-10/+0
As discussed from RISC-V C-API PR #101 [1], As discussed in #96, current interface is insufficient to support some cases, like a vendor buying a CPU IP from the upstream vendor but using their own mvendorid and custom features from the upstream vendor. In this case, we might need to add these extensions for each downstream vendor many times. Thus, making __riscv_vendor_feature_bits guarded by mvendorid is not a good idea. So, drop __riscv_vendor_feature_bits for now, and we should have time to discuss a better solution. [1] https://github.com/riscv-non-isa/riscv-c-api-doc/pull/101 Signed-off-by: Yangyu Chen <cyy@cyyself.name> gcc/ChangeLog: * config/riscv/riscv-feature-bits.h (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop. (struct riscv_vendor_feature_bits): Drop. libgcc/ChangeLog: * config/riscv/feature_bits.c (RISCV_VENDOR_FEATURE_BITS_LENGTH): Drop. (__init_riscv_features_bits_linux): Drop.
2025-02-07rs6000: Add cast to avoid pointer to integer comparison warning [PR117674]Peter Bergner1-1/+1
2025-02-07 Peter Bergner <bergner@linux.ibm.com> libgcc/ PR target/117674 * config/rs6000/linux-unwind.h (ppc_backchain_fallback): Add cast to avoid comparison between pointer and integer warning.
2025-01-30AVR: Provide built-ins for strlen where the string lives in some AS.Georg-Johann Lay2-1/+20
This patch adds built-in functions __builtin_avr_strlen_flash, __builtin_avr_strlen_flashx and __builtin_avr_strlen_memx. Purpose is that higher-level functions can use __builtin_constant_p on strlen without raising a diagnostic due to -Waddr-space-convert. gcc/ * config/avr/builtins.def (STRLEN_FLASH, STRLEN_FLASHX) (STRLEN_MEMX): New DEF_BUILTIN's. * config/avr/avr.cc (avr_ftype_strlen): New static function. (avr_builtin_supported_p): New built-ins are not for AVR_TINY. (avr_init_builtins) <strlen_flash_node, strlen_flashx_node, strlen_memx_node>: Provide new fntypes. (avr_fold_builtin) [AVR_BUILTIN_STRLEN_FLASH] [AVR_BUILTIN_STRLEN_FLASHX, AVR_BUILTIN_STRLEN_MEMX]: Fold if possible. * doc/extend.texi (AVR Built-in Functions): Document __builtin_avr_strlen_flash, __builtin_avr_strlen_flashx, __builtin_avr_strlen_memx. libgcc/ * config/avr/t-avr (LIB1ASMFUNCS): Add _strlen_memx. * config/avr/lib1funcs.S <L_strlen_memx, __strlen_memx>: Implement.
2025-01-28arm: libgcc: make -spec=sync-*.specs compatible with LTO [PR118642]Richard Earnshaw3-3/+3
The arm-none-eabi port provides some alternative implementations of __sync_synchronize for different implementations of the architecture. These can be selected using one of -specs=sync-{none,dmb,cp15dmb}.specs. These specs fragments fail, however, when LTO is used because they unconditionally add a --defsym=__sync_synchronize=<implementation> to the linker arguments and that fails if libgcc is not added to the list of libraries. Fix this by only adding the defsym if libgcc will be passed to the linker. libgcc/ PR target/118642 * config/arm/sync-none.specs (link): Only add the defsym if libgcc will be used. * config/arm/sync-dmb.specs: Likewise. * config/arm/sync-cp15dmb.specs: Likewise.
2025-01-17RISC-V: Add .note.gnu.property for ZICFILP and ZICFISS ISA extensionMonk Chiang4-1/+77
gcc/ChangeLog: * config/riscv/riscv.cc (riscv_file_end): Add .note.gnu.property. libgcc/ChangeLog: * config/riscv/crti.S: Add lpad instructions. * config/riscv/crtn.S: Likewise. * config/riscv/save-restore.S: Likewise. * config/riscv/riscv-asm.h: Add GNU_PROPERTY for ZICFILP, ZICFISS. Co-Developed-by: Jesse Huang <jesse.huang@sifive.com>
2025-01-17RISC-V: Add Zicfiss ISA extension.Monk Chiang2-0/+79
This patch is implemented according to the RISC-V CFI specification. It supports the generation of shadow stack instructions in the prologue, epilogue, non-local gotos, and unwinding. RISC-V CFI SPEC: https://github.com/riscv/riscv-cfi gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add ZICFISS ISA string. * config/riscv/predicates.md: New predicate x1x5_operand. * config/riscv/riscv.cc (riscv_expand_prologue): Insert shadow stack instructions. (riscv_expand_epilogue): Likewise. (riscv_for_each_saved_reg): Assign t0 or ra register for sspopchk instruction. (need_shadow_stack_push_pop_p): New function. Omit shadow stack operation on leaf function. * config/riscv/riscv.h (need_shadow_stack_push_pop_p): Define. * config/riscv/riscv.md: Add shadow stack patterns. (save_stack_nonlocal): Add shadow stack instructions for setjump. (restore_stack_nonlocal): Add shadow stack instructions for longjump. * config/riscv/riscv.opt (TARGET_ZICFISS): Define. libgcc/ChangeLog: * config/riscv/linux-unwind.h: Include shadow-stack-unwind.h. * config/riscv/shadow-stack-unwind.h (_Unwind_Frames_Extra): Define. (_Unwind_Frames_Increment): Define. gcc/testsuite/ChangeLog: * gcc.target/riscv/ssp-1.c: New test. * gcc.target/riscv/ssp-2.c: New test. Co-Developed-by: Greg McGary <gkm@rivosinc.com>, Kito Cheng <kito.cheng@gmail.com>
2025-01-07[PATCH] libgcc/m68k: More fixes for soft floatKeith Packard2-48/+47
Fix __extenddfxf2: * Remove bogus denorm handling block which would never execute -- the converted exp value is always positive as EXCESSX > EXCESSD. * Compute the whole significand in dl instead of doing part of it in ldl. * Mask off exponent from dl.l.upper so the denorm shift test works. * Insert the hidden one bit into dl.l.upper as needed. Fix __truncxfdf2 denorm handling. All that is required is to shift the significand right by the correct amount; it already has all of the necessary bits set including the explicit one. Compute the shift amount, then perform the wide shift across both elements of the significand. Fix __fixxfsi: * The value was off by a factor of two as the significand contains 32 bits, not 31 so we need to shift by one more than the equivalent code in __fixdfsi. * Simplify the code having realized that the lower 32 bits of the significand can never appear in the results. Return positive qNaN instead of negative. For floats, qNaN is 0x7fff_ffff. For doubles, qNaN is 0x7fff_ffff_ffff_ffff. Return correctly signed zero on float and double divide underflow. This means that Ld$underflow now expects d7 to contain the sign bit, just like the other return paths. libgcc/ * config/m68k/fpgnulib.c (extenddfxf2): Simplify code by removing code that should never execute. Fix denorm shift test and insert hidden bit as needed. (__truncxfdf2): Properly compue and shift the significant right. * config/m68k/lb1sf68.S (__fixxfsi): Correct shift counts and simplify. (QUIET_NAN): Make it a positive quiet NaN and fix return values to inject sign properly.
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