aboutsummaryrefslogtreecommitdiff
path: root/libgcc
AgeCommit message (Collapse)AuthorFilesLines
14 hoursDaily bump.GCC Administrator1-0/+5
25 hoursRISC-V: Only Save/Restore required registers for ILP32E/LP64EJim Lin1-8/+42
Previously the spec https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/70 has changed the save/restore routines to save/restore the registers which are really used for ILP32E/LP64 rather than always save/restore all of ra/s0/s1. I also found here that lacks the implementation for lp64e. If it's necessary I will file anothor patch for that. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_compute_frame_info): Remove the dedicated calculation for RVE. libgcc/ChangeLog: * config/riscv/save-restore.S: Only save/restore the registers which are really used for ILP32E/LP64. gcc/testsuite/ChangeLog: * gcc.target/riscv/save-restore-cfi-3.c: New test.
2025-08-31Daily bump.GCC Administrator1-0/+13
2025-08-29Revert "Fix _Decimal128 arithmetic error under FE_UPWARD."liuhongt5-568/+215
This reverts commit 50064b2898edfb83bc37f2597a35cbd3c1c853e3.
2025-08-30Daily bump.GCC Administrator1-0/+10
2025-08-28Fix _Decimal128 arithmetic error under FE_UPWARD.liuhongt5-215/+568
libgcc/config/libbid/ChangeLog: PR target/120691 * bid128_div.c: Fix _Decimal128 arithmetic error under FE_UPWARD. * bid128_rem.c: Ditto. * bid128_sqrt.c: Ditto. * bid64_div.c (bid64_div): Ditto. * bid64_sqrt.c (bid64_sqrt): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/pr120691.c: New test.
2025-08-22Daily bump.GCC Administrator1-0/+9
2025-08-21pru: libgcc: Add software implementation for multiplicationDimitar Dimitrov5-0/+124
For cores without a hardware multiplier, set respective optabs with library functions which use software implementation of multiplication. The implementation was copied from the RL78 backend. gcc/ChangeLog: * config/pru/pru.cc (pru_init_libfuncs): Set softmpy libgcc functions for optab multiplication entries if TARGET_OPT_MUL option is not set. libgcc/ChangeLog: * config/pru/libgcc-eabi.ver: Add __pruabi_softmpyi and __pruabi_softmpyll symbols. * config/pru/t-pru: Add softmpy source files. * config/pru/pru-softmpy.h: New file. * config/pru/softmpyi.c: New file. * config/pru/softmpyll.c: New file. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
2025-08-14Daily bump.GCC Administrator1-0/+12
2025-08-13LoongArch: Add support for _BitInt [PR117599]Yang Yujie3-0/+31
This patch adds support for C23's _BitInt for LoongArch. From the LoongArch psABI[1]: > _BitInt(N) objects are stored in little-endian order in memory > and are signed by default. > > For N ≤ 64, a _BitInt(N) object have the same size and alignment > of the smallest fundamental integral type that can contain it. > The unused high-order bits within this containing type are filled > with sign or zero extension of the N-bit value, depending on whether > the _BitInt(N) object is signed or unsigned. The _BitInt(N) object > propagates its signedness to the containing type and is laid out > in a register or memory as an object of this type. > > For N > 64, _BitInt(N) objects are implemented as structs of 64-bit > integer chunks. The number of chunks is the smallest even integer M > so that M * 64 ≥ N. These objects are of the same size of the struct > containing the chunks, but always have 16-byte alignment. If there > are unused bits in the highest-ordered chunk that contains used > bits, they are defined as the sign- or zero- extension of the used > bits depending on whether the _BitInt(N) object is signed or > unsigned. If an entire chunk is unused, its bits are undefined. [1] https://github.com/loongson/la-abi-specs PR target/117599 gcc/ChangeLog: * config/loongarch/loongarch.h: Define a PROMOTE_MODE case for small _BitInts. * config/loongarch/loongarch.cc (loongarch_promote_function_mode): Same. (loongarch_bitint_type_info): New function. (TARGET_C_BITINT_TYPE_INFO): Declare. libgcc/ChangeLog: * config/loongarch/t-softfp-tf: Enable _BitInt helper functions. * config/loongarch/t-loongarch: Same. * config/loongarch/libgcc-loongarch.ver: New file. gcc/testsuite/ChangeLog: * gcc.target/loongarch/bitint-alignments.c: New test. * gcc.target/loongarch/bitint-args.c: New test. * gcc.target/loongarch/bitint-sizes.c: New test.
2025-08-13LoongArch: Prioritize target-specific makefile fragmentsYang Yujie1-19/+12
libgcc/ChangeLog: * config.host: Remove unused code. Include LoongArch-specific tmake_files after the OS-specific ones.
2025-08-09Daily bump.GCC Administrator1-0/+8
2025-08-08aarch64: libgcc: Honor disable-werror [PR117600]Christophe Lyon4-1/+35
In commit r15-4417-g71c7b446b98aa5, I made -werror mandatory when building libgcc for aarch64. While it achieved its goal (make us fix problems unnoticed so far), there has a been a lot of debate because it couldn't be disabled easily. This patch adds support for --enable-werror/--disable-werror in libgcc, defaulting to --enable-werror for aarch64. Tested on non-bootstrap builds on aarch64-linux-gnu (with -Wno-prio-ctor-dtor removed in order to get an error). libgcc/ChangeLog: PR libgcc/117600 * Makefile.in (WERROR): New. * config/aarch64/t-aarch64: Handle WERROR. * configure: Regenerate. * configure.ac: Add support for --enable-werror.
2025-08-08Daily bump.GCC Administrator1-0/+14
2025-08-07s390: Add _BitInt supportStefan Schulze Frielinghaus2-0/+15
gcc/ChangeLog: * config/s390/s390.cc (print_operand): Allow arbitrary wide_int constants for _BitInt. (s390_bitint_type_info): Implement target hook TARGET_C_BITINT_TYPE_INFO. libgcc/ChangeLog: * config/s390/libgcc-glibc.ver: Export _BitInt support functions. * config/s390/t-softfp (softfp_extras): Add fixtfbitint floatbitinttf. gcc/testsuite/ChangeLog: * gcc.target/s390/bitint-1.c: New test. * gcc.target/s390/bitint-2.c: New test. * gcc.target/s390/bitint-3.c: New test. * gcc.target/s390/bitint-4.c: New test.
2025-08-07s390: libgcc: Enable soft-fpStefan Schulze Frielinghaus4-0/+153
Enable soft-fp for -m64 only. libgcc/ChangeLog: * config.host: Include makefiles t-softfp for -m64. * config/s390/sfp-exceptions.c: New file. * config/s390/sfp-machine.h: New file. * config/s390/t-softfp: New file.
2025-08-07Daily bump.GCC Administrator1-0/+6
2025-08-06libgcc: Remove useless forward declaration [PR121397]Jakub Jelinek1-1/+0
aarch64 for some strange reason unconditionally enables -Werror for libgcc building and this particular file for some strange reason contains a useless static forward declaration of a function only defined in the #if defined __sun__ && defined __svr4__ block and not otherwise (with __attribute__((constructor))). And we warn (with -Werror error) in the non-__sun__/__svr4__ case because it declares a static function that is never defined. The forward declaration makes no sense to me, for static functions forward declarations shouldn't be needed even for -Wstrict-prototypes, and AFAIK we don't warn on static __attribute__((constructor)) void foo (void) {} being unused. And the function isn't used before being defined. So, the following patch just removes the forward declaration. 2025-08-06 Jakub Jelinek <jakub@redhat.com> PR libgcc/121397 * enable-execute-stack-mprotect.c (check_enabling): Remove useless forward declaration.
2025-08-01Daily bump.GCC Administrator1-0/+17
2025-07-31libgcc: Update FMV features to latest ACLE spec 2024Q4Wilco Dijkstra1-28/+6
Update FMV features to latest ACLE spec of 2024Q4 - several features have been removed or merged. Add FMV support for CSSC and MOPS. Preserve the ordering in enum CPUFeatures. gcc: * common/config/aarch64/cpuinfo.h: Remove unused features, add FEAT_CSSC and FEAT_MOPS. * config/aarch64/aarch64-option-extensions.def: Remove FMV support for RPRES, use PULL rather than AES, add FMV support for CSSC and MOPS. libgcc: * config/aarch64/cpuinfo.c (__init_cpu_features_constructor): Remove unused features, add support for CSSC and MOPS.
2025-07-31libgcc: Cleanup HWCAP defines in cpuinfo.cWilco Dijkstra1-197/+49
Cleanup HWCAP defines - rather than including hwcap.h and then repeating it using ifndef, just define the HWCAPs we need exactly as in hwcap.h. libgcc: * config/aarch64/cpuinfo.c: Cleanup HWCAP defines.
2025-07-31aarch64: Stop using sys/ifunc.h header in libatomic and libgccYury Khrustalev1-9/+37
This optional header is used to bring in the definition of the struct __ifunc_arg_t type. Since it has been added to glibc only recently, the previous implementation had to check whether this header is present and, if not, it provide its own definition. This creates dead code because either one of these two parts would not be tested. The ABI specification for ifunc resolvers allows to create own ABI-compatible definition for this type, which is the right way of doing it. In addition to improving consistency, the new approach also helps with addition of new fields to struct __ifunc_arg_t type without the need to work-around situations when the definition imported from the header lacks these new fields. ABI allows to define as many hwcap fields in this struct as needed, provided that at runtime we only access the fields that are permitted by the _size value. gcc/ * config/aarch64/aarch64.cc (build_ifunc_arg_type): Add new fields _hwcap3 and _hwcap4. libatomic/ * config/linux/aarch64/host-config.h (__ifunc_arg_t): Remove sys/ifunc.h and add new fields _hwcap3 and _hwcap4. libgcc/ * config/aarch64/cpuinfo.c (__ifunc_arg_t): Likewise. (__init_cpu_features): obtain and assign values for the fields _hwcap3 and _hwcap4. (__init_cpu_features_constructor): check _size in the arg argument.
2025-07-18Daily bump.GCC Administrator1-0/+7
2025-07-17aarch64: Adapt unwinder to linux's SME signal behaviourRichard Sandiford1-1/+107
SME uses a lazy save system to manage ZA. The idea is that, if a function with ZA state wants to call a "normal" function, it can leave its state in ZA and instead set up a lazy save buffer. If, unexpectedly, that normal function contains a nested use of ZA, that nested use of ZA must commit the lazy save first. This lazy save system uses a special system register called TPIDR2_EL0. See: https://github.com/ARM-software/abi-aa/blob/main/aapcs64/aapcs64.rst#66the-za-lazy-saving-scheme for details. The ABI specifies that, on entry to an exception handler, the following things must be true: * PSTATE.SM must be 0 (the processor must be in non-streaming mode) * PSTATE.ZA must be 0 (ZA must be off) * TPIDR2_EL0 must be 0 (there must be no uncommitted lazy save) This is normally done by making _Unwind_RaiseException & friends commit any lazy save before they unwind. This also has the side effect of ensuring that TPIDR2_EL0 is never left pointing to a lazy save buffer that has been unwound. However, things get more complicated with signals. If: (a) a signal is raised while ZA is dormant (that is, while there is an uncommitted lazy save); (b) the signal handler throws an exception; and (c) that exception is caught outside the signal handler something must ensure that the lazy save from (a) is committed. This would be simple if the signal handler was entered with ZA and TPIDR2_EL0 intact. However, for various good reasons that are out of scope here, this is not done. Instead, Linux now clears both TPIDR2_EL0 and PSTATE.ZA before entering a signal handler, see: https://lore.kernel.org/all/20250417190113.3778111-1-mark.rutland@arm.com/ for details. Therefore, it is the unwinder that must simulate a commit of the lazy save from (a). It can do this by reading the previous values of TPIDR2_EL0 and ZA from the sigcontext. The SME-related sigcontext structures were only added to linux's asm/sigcontext.h relatively recently and we can't rely on GCC being built against such recent kernel header files. The patch therefore uses defines relevant macros if they are not defined and provide types that comply with ABI layout of the corresponding linux types. The patch includes some ugly casting in an attempt to support big-endian ILP32, even though SME on big-endian ILP32 linux should never be a thing. We can remove it if we also remove ILP32 support from GCC. Co-authored-by: Yury Khrustalev <yury.khrustalev@arm.com> Reviewed-by: Tamar Christina <tamar.christina@arm.com> gcc/ * doc/sourcebuild.texi (aarch64_sme_hw): Document. gcc/testsuite/ * lib/target-supports.exp (add_options_for_aarch64_sme) (check_effective_target_aarch64_sme_hw): New procedures. * g++.target/aarch64/sme/sme_throw_1.C: New test. * g++.target/aarch64/sme/sme_throw_2.C: Likewise. libgcc/ * config/aarch64/linux-unwind.h (aarch64_fallback_frame_state): If a signal was raised while there was an uncommitted lazy save, commit the save as part of the unwind process.
2025-07-17Daily bump.GCC Administrator1-0/+4
2025-07-16libgcc/Makefile.in: Delete dead `MACHMODE_H` variableJohn Ericson1-2/+0
This dates back to the creation of top-level `libgcc` in fa9585134f6f58fa0d3da3ca4ad5493855aea2dc. I strongly suspect that this does nothing. Andrew Pinksi adds: > So looking into this further, MACHMODE_H used part of LIBGCC_DEPS > because of TM_H and r0-78222-gfa9585134f6f58 moved away from including > tm.h from libgcc. It was copied over unused. It is indeed used then. (For background context, my overall goal here is hoping libgcc can depend on fewer/no stuff that is generated by `gcc/Makefile`. This is me trying to pluck some low-hanging fruit -- this is the only direct mention of `insn-modes.h` in libgcc.) libgcc/ChangeLog: * Makefile.in: Delete dead `MACHMODE_H` variable
2025-07-16Daily bump.GCC Administrator1-0/+5
2025-07-15libgcc: Fix aarch64 buildAndrew Pinski1-0/+1
For aarch64, libgcc is built with -Werror, after the latest -Wunused-but-set* commit (r16-2258-g0eac9cfee8cb0b21d), a new warning showed up: ``` ../../../gcc/libgcc/config/libbid/bid_binarydecimal.c: In function ‘__binary32_to_bid128’: ../../../gcc/libgcc/config/libbid/bid_binarydecimal.c:130:31: error: variable ‘c3’ set but not used [-Werror=unused-but-set-variable=] 130 | { unsigned long long c0,c1,c2,c3; \ | ^~ ../../../gcc/libgcc/config/libbid/bid_binarydecimal.c:146842:5: note: in expansion of macro ‘__mul_10x256_to_256’ 146842 | __mul_10x256_to_256 (z.w[5], z.w[4], z.w[3], z.w[2], z.w[5], z.w[4], | ^~~~~~~~~~~~~~~~~~~ ``` This fixes it by casting c3 to void after the last __mul_10x64 in __mul_10x256_to_256 macro to mark it as being "used". libgcc/config/libbid/ChangeLog: * bid_binarydecimal.c (__mul_10x256_to_256): Mark c3 as being used. Signed-off-by: Andrew Pinski <quic_apinski@quicinc.com>
2025-07-11Daily bump.GCC Administrator1-0/+6
2025-07-10[PATCH] libgcc: PR target/116363 Fix SFtype to UDWtype conversionJan Dubiec1-28/+13
This patch fixes SFtype to UDWtype (aka float to unsigned long long) conversion on targets without DFmode like e.g. H8/300H. It solely relies on SFtype->UWtype and UWtype->UDWtype conversions/casts. The existing code in line 2218 (counter = a) assigns/casts a float which is *always* not lesser than Wtype_MAXp1_F to an UWtype int which of course does not have enough capacity. PR target/116363 libgcc/ChangeLog: * libgcc2.c (__fixunssfDI): Fix SFtype to UDWtype conversion for targets without LIBGCC2_HAS_DF_MODE defined
2025-05-28Daily bump.GCC Administrator2-0/+94
2025-05-27libgcc: Add DPD support + fix big-endian support of _BitInt <-> dfp conversionsJakub Jelinek21-30/+654
The following patch fixes FAIL: gcc.dg/dfp/bitint-1.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-2.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-3.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-4.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-5.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-6.c (test for excess errors) FAIL: gcc.dg/dfp/bitint-8.c (test for excess errors) FAIL: gcc.dg/dfp/int128-1.c (test for excess errors) FAIL: gcc.dg/dfp/int128-2.c (test for excess errors) FAIL: gcc.dg/dfp/int128-4.c (test for excess errors) on s390x-linux (with the 3 not yet posted patches). The patch does multiple things: 1) the routines were written for the DFP BID (binary integer decimal) format which is used on all arches but powerpc*/s390* (those use DPD - densely packed decimal format); as most of the code is actually the same for both BID and DPD formats, I haven't copied the sources + slightly modified them, but added the DPD support directly, + renaming of the exported symbols from __bid_* prefixed to __dpd_* prefixed that GCC expects on the DPD targets 2) while testing that I've found some big-endian issues in the existing support 3) testing also revealed that in some cases __builtin_clzll (~msb) was called with msb set to all ones, so invoking UB; apparently on aarch64 and x86 we were lucky and got some value that happened to work well, but that wasn't the case on s390x For 1), the patch uses two ~ 2KB tables to speed up the decoding/encoding. I haven't found such tables in what is added into libgcc.a, though they are in libdecnumber/bid/bid2dpd_dpd2bid.h, but there they are just huge and next to other huge tables - there is d2b which is like __dpd_d2bbitint in the patch but it uses 64-bit entries rather than 16-bit, then there is d2b2 with 64-bit entries like in d2b all multiplied by 1000, then d2b3 similarly multiplied by 1000000, then d2b4 similarly multiplied by 1000000000, then d2b5 similarly multiplied by 1000000000000ULL and d2b6 similarly multipled by 1000000000000000ULL. Arguably it can save some of the multiplications, but on the other side accesses memory which is unlikely in the caches, and the 2048 bytes in the patch vs. 24 times more for d2b is IMHO significant. For b2d, libdecnumber/bid/bid2dpd_dpd2bid.h has again b2d table like __dpd_b2dbitint in the patch, except that it has 64-bit entries rather than 16-bit (this time 1000 entries), but then has b2d2 which has the same entries shifted left by 10, then b2d3 shifted left by 20, b2d4 shifted left by 30 and b2d5 shifted left by 40. I can understand for d2b paying memory cost to speed up multiplications, but don't understand paying extra 4 * 8 * 1000 bytes (+ 6 * 1000 bytes for b2d not using ushort) just to avoid shifts. 2025-05-27 Jakub Jelinek <jakub@redhat.com> * config/t-softfp (softfp_bid_list): Don't guard with $(enable_decimal_float) == bid. * soft-fp/bitint.h (__bid_pow10bitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_pow10bitint. (__dpd_d2bbitint, __dpd_b2dbitint): Declare. * soft-fp/bitintpow10.c (__dpd_d2bbitint, __dpd_b2dbitint): New variables. * soft-fp/fixsdbitint.c (__bid_fixsdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdbitint. Add DPD support. Fix big-endian support. * soft-fp/fixddbitint.c (__bid_fixddbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddbitint. Add DPD support. Fix big-endian support. * soft-fp/fixtdbitint.c (__bid_fixtdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdbitint. Add DPD support. Fix big-endian support. * soft-fp/fixsdti.c (__bid_fixsdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdbitint. (__bid_fixsdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdti. * soft-fp/fixddti.c (__bid_fixddbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddbitint. (__bid_fixddti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddti. * soft-fp/fixtdti.c (__bid_fixtdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdbitint. (__bid_fixtdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdti. * soft-fp/fixunssdti.c (__bid_fixsdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixsdbitint. (__bid_fixunssdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixunssdti. * soft-fp/fixunsddti.c (__bid_fixddbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixddbitint. (__bid_fixunsddti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixunsddti. * soft-fp/fixunstdti.c (__bid_fixtdbitint): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixtdbitint. (__bid_fixunstdti): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_fixunstdti. * soft-fp/floatbitintsd.c (__bid_floatbitintsd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintsd. Add DPD support. Avoid calling __builtin_clzll with 0 argument. Fix big-endian support. * soft-fp/floatbitintdd.c (__bid_floatbitintdd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintdd. Add DPD support. Avoid calling __builtin_clzll with 0 argument. Fix big-endian support. * soft-fp/floatbitinttd.c (__bid_floatbitinttd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitinttd. Add DPD support. Avoid calling __builtin_clzll with 0 argument. Fix big-endian support. * soft-fp/floattisd.c (__bid_floatbitintsd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintsd. (__bid_floattisd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floattisd. * soft-fp/floattidd.c (__bid_floatbitintdd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintdd. (__bid_floattidd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floattidd. * soft-fp/floattitd.c (__bid_floatbitinttd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitinttd. (__bid_floattitd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floattitd. * soft-fp/floatuntisd.c (__bid_floatbitintsd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintsd. (__bid_floatuntisd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatuntisd. * soft-fp/floatuntidd.c (__bid_floatbitintdd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitintdd. (__bid_floatuntidd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatuntidd. * soft-fp/floatuntitd.c (__bid_floatbitinttd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatbitinttd. (__bid_floatuntitd): For !defined(ENABLE_DECIMAL_BID_FORMAT) redefine to __dpd_floatuntitd.
2025-05-27AVR: target/120442 - Support f7_fdim / fdiml in LibF7.Georg-Johann Lay6-10/+39
Add Support for fdiml. PR target/120442 libgcc/config/avr/libf7/ * libf7-common.mk (LIBF_C_PARTS, m_ddd): Add fdim. * libf7.h (f7_fdim): New proto. * libf7.c (f7_fdim): New function. * f7renames.sh (f7_fdim): Add rename. * f7-wraps.h: Rebuild * f7-renames.h: Rebuild
2025-05-27AVR: target/120441 - Fix f7_exp for |x| ≥ 512.Georg-Johann Lay1-2/+2
f7_exp limited exponents to 512, but 1023 * ln2 ≈ 709, hence 1024 is a correct limit. libgcc/config/avr/libf7/ PR target/120441 * libf7.c (f7_exp): Limit aa->expo to 10 (not to 9).
2025-05-26Daily bump.GCC Administrator1-0/+6
2025-05-25Enable mcf thread model for aarch64-*-mingw*.LIU Hao2-2/+5
This is similar to d6d7afcdbc04adb0ec42a44b2d7e05600945af42 about the posix and win32 thread model. Signed-off-by: LIU Hao <lh_mouse@126.com> Signed-off-by: Jonathan Yong <10walls@gmail.com> libgcc/ChangeLog: * config.host: Enable mcf thread model for aarch64-*-mingw*. * config/i386/t-mingw-mcfgthread: Move to... * config/mingw/t-mingw-mcfgthread: ...here.
2025-05-22Daily bump.GCC Administrator1-0/+4
2025-05-21vxworks: libgcc: include string.h for memsetAlexandre Oliva1-0/+1
gthr-vxworks-thread.c calls memset in __ghtread_cond_signal, but it fails ot include <string.h>, where this function is declared, and GCC 14 rejects calls of undeclared functions. Include the required header. for libgcc/ChangeLog * config/gthr-vxworks-thread.c: Include string.h for memset.
2025-05-21Daily bump.GCC Administrator1-0/+16
2025-05-20libgcc: Move bitint support exports to x86/aarch64 specific map filesJakub Jelinek5-6/+24
When adding _BitInt support I was hoping all or most of arches would implement it already for GCC 14. That didn't happen and with new hosts adding support for _BitInt for GCC 16 (s390x-linux and as was posted today loongarch-linux too), we need the _BitInt support functions exported on those arches at GCC_16.0.0 rather than GCC_14.0.0 which shouldn't be changed anymore. The following patch does that. Both arches were already exporting some of the _BitInt related symbols in their specific map files, this just moves the remaining ones there as well. 2025-05-20 Jakub Jelinek <jakub@redhat.com> * libgcc-std.ver.in (GCC_14.0.0): Remove bitint related exports from here. * config/i386/libgcc-glibc.ver (GCC_14.0.0): Add them here. * config/i386/libgcc-darwin.ver (GCC_14.0.0): Likewise. * config/i386/libgcc-sol2.ver (GCC_14.0.0): Likewise. * config/aarch64/libgcc-softfp.ver (GCC_14.0.0): Likewise.
2025-05-20libgcc: Small bitint_reduce_prec big-endian fixesJakub Jelinek2-10/+10
The big-endian _BitInt support in libgcc was written without any testing and so I haven't discovered I've made one mistake in it (in multiple places). The bitint_reduce_prec function attempts to optimize inputs which have some larger precision but at runtime they are found to need smaller number of limbs. For little-endian that is handled just by returning smaller precision (or negative precision for signed), but for big-endian we need to adjust the passed in limb pointer so that when it returns smaller precision the argument still contains the least significant limbs for the returned precision. 2025-05-20 Jakub Jelinek <jakub@redhat.com> * libgcc2.c (bitint_reduce_prec): For big endian __LIBGCC_BITINT_ORDER__ use ++*p and --*p instead of ++p and --p. * soft-fp/bitint.h (bitint_reduce_prec): Likewise.
2025-05-18Daily bump.GCC Administrator1-0/+5
2025-05-17[PATCH] libgcc SH: fix alignment for relaxationOleg Endo1-1/+2
From 6462f1e6a2565c5d4756036d9bc2f39dce9bd768 Mon Sep 17 00:00:00 2001 From: QBos07 <qubos@outlook.de> Date: Sat, 10 May 2025 16:56:28 +0000 Subject: [PATCH] libgcc SH: fix alignment for relaxation when relaxation is enabled we can not infer the alignment from the position as that may change. This should not change non-relaxed builds as its allready aligned there. This was the missing piece to building an entire toolchain with -mrelax Credit goes to Oleg Endo: https://sourceware.org/bugzilla/show_bug.cgi?id=3298#c4 libgcc/ * config/sh/lib1funcs.S (ashiftrt_r4_32): Increase alignment. (movemem): Force alignment of the mova intruction.
2025-05-16Daily bump.GCC Administrator1-0/+6
2025-05-14Update libbid according to the latest Intel Decimal Floating-Point Math Library.liuhongt1-53/+68
The Intel Decimal Floating-Point Math Library is available as open-source on Netlib[1]. [1] https://www.netlib.org/misc/intel/ libgcc/config/libbid/ChangeLog: * bid128_string.c (MIN_DIGITS): New macro. (bid128_from_string): Bug fix. Conversion from very long input string to decimal.
2025-04-26Daily bump.GCC Administrator1-0/+8
2025-04-25GCN, nvptx offloading: Host/device compatibility: Itanium C++ ABI, DSO ↵Thomas Schwinge2-0/+48
Object Destruction API [PR119853, PR119854] '__dso_handle' for '__cxa_atexit', '__cxa_finalize'. See <https://itanium-cxx-abi.github.io/cxx-abi/abi.html#dso-dtor>. PR target/119853 PR target/119854 libgcc/ * config/gcn/crt0.c (_fini_array): Call '__GCC_offload___cxa_finalize'. * config/nvptx/gbl-ctors.c (__static_do_global_dtors): Likewise. libgomp/ * target-cxa-dso-dtor.c: New. * config/accel/target-cxa-dso-dtor.c: Likewise. * Makefile.am (libgomp_la_SOURCES): Add it. * Makefile.in: Regenerate. * testsuite/libgomp.c++/target-cdtor-1.C: New. * testsuite/libgomp.c++/target-cdtor-2.C: Likewise.
2025-04-20Daily bump.GCC Administrator1-0/+34
2025-04-19[PATCH v2] sh: libgcc: Implement fenv rouding and exceptions for soft-fp ↵Jiaxun Yang1-0/+46
[PR118257] Implement fenv rouding and exceptions for soft-fp, as per SuperH arch specification. No new tests required, as it's already covered by many torture tests with fenv_exceptions. PR target/118257 libgcc/ChangeLog: * config/sh/sfp-machine.h (_FPU_GETCW): Implement with builtin. (_FPU_SETCW): Likewise. (FP_EX_ENABLE_SHIFT): Derive from arch spec. (FP_EX_CAUSE_SHIFT): Likewise. (FP_RND_MASK): Likewise. (FP_EX_INVALID): Likewise. (FP_EX_DIVZERO): Likewise. (FP_EX_ALL): Likewise. (FP_EX_OVERFLOW): Likewise. (FP_EX_UNDERFLOW): Likewise. (FP_EX_INEXACT): Likewise. (_FP_DECL_EX): Declear default FCSR value. (FP_RND_NEAREST): Derive from arch spec. (FP_RND_ZERO): Likewise. (FP_INIT_ROUNDMODE): Likewise. (FP_ROUNDMODE): Likewise. (FP_TRAPPING_EXCEPTIONS): Likewise. (FP_HANDLE_EXCEPTIONS): Implement with _FPU_SETCW.
2025-04-19[PATCH v2] sh: Correct NaN signalling bit and propagation rules [PR111814]Jiaxun Yang1-13/+23
As per architecture, SuperH has a reversed NaN signalling bit vs IEEE754-2008, it also has a NaN propgation rule similar to MIPS style. Use mips style float format and mode for all float types, and correct sfp-machine header accordingly. PR target/111814 gcc/ChangeLog: * config/sh/sh-modes.def (RESET_FLOAT_FORMAT): Use mips format. (FLOAT_MODE): Use mips mode. libgcc/ChangeLog: * config/sh/sfp-machine.h (_FP_NANFRAC_B): Reverse signaling bit. (_FP_NANFRAC_H): Likewise. (_FP_NANFRAC_S): Likewise. (_FP_NANFRAC_D): Likewise. (_FP_NANFRAC_Q): Likewise. (_FP_KEEPNANFRACP): Enable for target. (_FP_QNANNEGATEDP): Enable for target. (_FP_CHOOSENAN): Port from MIPS. gcc/testsuite/ChangeLog: * gcc.target/sh/pr111814.c: New test.
generated by cgit v1.1 at 2025-09-20 14:25:03 +0000