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2023-05-12i386: Cleanup ix86_expand_vecop_qihi{,2}Uros Bizjak1-27/+37
Some cleanups while looking at these two functions. gcc/ChangeLog: * config/i386/i386-expand.cc (ix86_expand_vecop_qihi2): Also reject ymm instructions for TARGET_PREFER_AVX128. Use generic gen_extend_insn to generate zero/sign extension instructions. Fix comments. (ix86_expand_vecop_qihi): Initialize interleave functions for MULT code only. Fix comments.
2023-05-12PR modula2/109830 m2iso library SeqFile.mod appending to a file overwrites ↵Gaius Mulley2-21/+101
content This patch is for the m2iso library SeqFile.mod to fix a bug when a file is opened using OpenAppend. The patch checks to see if the file exists and it uses FIO.OpenForRandom to ensure the file is not overwritten. gcc/m2/ChangeLog: PR modula2/109830 * gm2-libs-iso/SeqFile.mod (newCid): New parameter toAppend used to select FIO.OpenForRandom. (OpenRead): Pass extra parameter to newCid. (OpenWrite): Pass extra parameter to newCid. (OpenAppend): Pass extra parameter to newCid. gcc/testsuite/ChangeLog: PR modula2/109830 * gm2/isolib/run/pass/seqappend.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-05-12i386: Remove mulv2si emulated sequence for TARGET_SSE2 [PR109797]Uros Bizjak1-33/+1
Remove mulv2si emulated sequence for TARGET_SSE2 and enable only native PMULLD instruction for TARGET_SSE4_1. Ideally, the vectorization for TARGET_SSE2 should depend on more precise cost estimation (the PR contains patch for ix86_multiplication_cost), but even with patched cost function the runtime regression was not fixed. PR target/109797 gcc/ChangeLog: * config/i386/mmx.md (mulv2si3): Remove expander. (mulv2si3): Rename insn pattern from *mulv2si.
2023-05-12LTO: Fix writing of toplevel asm with offloading [PR109816]Tobias Burnus1-1/+1
When offloading was enabled, top-level 'asm' were added to the offloading section, confusing assemblers which did not support the syntax. Additionally, with offloading and -flto, the top-level assembler code did not end up in the host files. As r14-321-g9a41d2cdbcd added top-level 'asm' to one libstdc++ header file, the issue became more apparent, causing fails with nvptx for some C++ testcases. PR libstdc++/109816 gcc/ChangeLog: * lto-cgraph.cc (output_symtab): Guard lto_output_toplevel_asms by '!lto_stream_offload_p'. libgomp/ChangeLog: * testsuite/libgomp.c++/target-map-class-1.C: New test. * testsuite/libgomp.c++/target-map-class-2.C: New test.
2023-05-12RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743]Kito Cheng5-45/+277
Rebase to trunk and send V3 patch for: https://gcc.gnu.org/pipermail/gcc-patches/2023-May/617821.html This patch is fixing: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109743. This issue happens is because we are currently very conservative in optimization of user vsetvli. Consider this following case: bb 1: vsetvli a5,a4... (demand AVL = a4). bb 2: RVV insn use a5 (demand AVL = a5). LCM will hoist vsetvl of bb 2 into bb 1. We don't do AVL propagation for this situation since it's complicated that we should analyze the code sequence between vsetvli in bb 1 and RVV insn in bb 2. They are not necessary the consecutive blocks. This patch is doing the optimizations after LCM, we will check and eliminate the vsetvli in LCM inserted edge if such vsetvli is redundant. Such approach is much simplier and safe. code: void foo2 (int32_t *a, int32_t *b, int n) { if (n <= 0) return; int i = n; size_t vl = __riscv_vsetvl_e32m1 (i); for (; i >= 0; i--) { vint32m1_t v = __riscv_vle32_v_i32m1 (a, vl); __riscv_vse32_v_i32m1 (b, v, vl); if (i >= vl) continue; if (i == 0) return; vl = __riscv_vsetvl_e32m1 (i); } } Before this patch: foo2: .LFB2: .cfi_startproc ble a2,zero,.L1 mv a4,a2 li a3,-1 vsetvli a5,a2,e32,m1,ta,mu vsetvli zero,a5,e32,m1,ta,ma <- can be eliminated. .L5: vle32.v v1,0(a0) vse32.v v1,0(a1) bgeu a4,a5,.L3 .L10: beq a2,zero,.L1 vsetvli a5,a4,e32,m1,ta,mu addi a4,a4,-1 vsetvli zero,a5,e32,m1,ta,ma <- can be eliminated. vle32.v v1,0(a0) vse32.v v1,0(a1) addiw a2,a2,-1 bltu a4,a5,.L10 .L3: addiw a2,a2,-1 addi a4,a4,-1 bne a2,a3,.L5 .L1: ret After this patch: f: ble a2,zero,.L1 mv a4,a2 li a3,-1 vsetvli a5,a2,e32,m1,ta,ma .L5: vle32.v v1,0(a0) vse32.v v1,0(a1) bgeu a4,a5,.L3 .L10: beq a2,zero,.L1 vsetvli a5,a4,e32,m1,ta,ma addi a4,a4,-1 vle32.v v1,0(a0) vse32.v v1,0(a1) addiw a2,a2,-1 bltu a4,a5,.L10 .L3: addiw a2,a2,-1 addi a4,a4,-1 bne a2,a3,.L5 .L1: ret PR target/109743 gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (pass_vsetvl::get_vsetvl_at_end): New. (local_avl_compatible_p): New. (pass_vsetvl::local_eliminate_vsetvl_insn): Enhance local optimizations for LCM, rewrite as a backward algorithm. (pass_vsetvl::cleanup_insns): Use new local_eliminate_vsetvl_insn interface, handle a BB at once. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/pr109743-1.c: New test. * gcc.target/riscv/rvv/vsetvl/pr109743-2.c: New test. * gcc.target/riscv/rvv/vsetvl/pr109743-3.c: New test. * gcc.target/riscv/rvv/vsetvl/pr109743-4.c: New test. Co-authored-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
2023-05-12tree-optimization/64731 - extend store-from CTOR lowering to TARGET_MEM_REFRichard Biener2-17/+38
The following also covers TARGET_MEM_REF when decomposing stores from CTORs to supported elementwise operations. This avoids spilling and cleans up after vector lowering which doesn't touch loads or stores. It also mimics what we already do for loads. PR tree-optimization/64731 * tree-ssa-forwprop.cc (pass_forwprop::execute): Also handle TARGET_MEM_REF destinations of stores from vector CTORs. * gcc.target/i386/pr64731.c: New testcase.
2023-05-12c++: remove redundant testcase [PR83258]Patrick Palka2-9/+1
I noticed only after the fact that the new testcase template/function2.C (from r14-708-gc3afdb8ba8f183) is just a subset of ext/visibility/anon8.C, so let's get rid of it. PR c++/83258 gcc/testsuite/ChangeLog: * g++.dg/ext/visibility/anon8.C: Mention PR83258. * g++.dg/template/function2.C: Removed.
2023-05-12c++: robustify testcase [PR109752]Patrick Palka2-26/+13
This rewrites the testcase for PR109752 to make it simpler and more robust (i.e. no longer dependent on r13-4035-gc41bbfcaf9d6ef). PR c++/109752 gcc/testsuite/ChangeLog: * g++.dg/cpp2a/concepts-pr109752.C: Rename to ... * g++.dg/cpp2a/concepts-complete4.C: ... this. Rewrite.
2023-05-12tree-optimization/109791 - simplify (unsigned)&foo - (unsigned)(&foo + o)Richard Biener1-0/+12
The following adds another variant of address difference simplification. The utility ptr_difference_const only handles constant differences (we also cannot code generate anything else), so exposing a possible POINTER_PLUS_EXPR in the match and computing the difference on the base only makes it possible to handle one case of a variable offset. This simplifies (unsigned long) &MEM <char[3]> [(void *)&str + 2B] - (unsigned long) (&str + (_69 + 1)) down to (1 - (unsigned long) _69) during niter analysis, allowing ranger to eliminate a condition later and avoiding a bogus -Wstringop-overflow diagnostic for the testcase in the PR. PR tree-optimization/109791 * match.pd (minus (convert ADDR_EXPR@0) (convert (pointer_plus @1 @2))): New pattern. (minus (convert (pointer_plus @1 @2)) (convert ADDR_EXPR@0)): Likewise.
2023-05-12arm: [MVE intrinsics] rework vsriqChristophe Lyon5-213/+5
Implement vsriq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vsriq): New. * config/arm/arm-mve-builtins-base.def (vsriq): New. * config/arm/arm-mve-builtins-base.h (vsriq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vsriq. * config/arm/arm_mve.h (vsriq): Remove. (vsriq_m): Remove. (vsriq_n_u8): Remove. (vsriq_n_s8): Remove. (vsriq_n_u16): Remove. (vsriq_n_s16): Remove. (vsriq_n_u32): Remove. (vsriq_n_s32): Remove. (vsriq_m_n_s8): Remove. (vsriq_m_n_u8): Remove. (vsriq_m_n_s16): Remove. (vsriq_m_n_u16): Remove. (vsriq_m_n_s32): Remove. (vsriq_m_n_u32): Remove. (__arm_vsriq_n_u8): Remove. (__arm_vsriq_n_s8): Remove. (__arm_vsriq_n_u16): Remove. (__arm_vsriq_n_s16): Remove. (__arm_vsriq_n_u32): Remove. (__arm_vsriq_n_s32): Remove. (__arm_vsriq_m_n_s8): Remove. (__arm_vsriq_m_n_u8): Remove. (__arm_vsriq_m_n_s16): Remove. (__arm_vsriq_m_n_u16): Remove. (__arm_vsriq_m_n_s32): Remove. (__arm_vsriq_m_n_u32): Remove. (__arm_vsriq): Remove. (__arm_vsriq_m): Remove.
2023-05-12arm: [MVE intrinsics] factorize vsriqChristophe Lyon2-4/+6
Factorize vsriq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vsri. * config/arm/mve.md (mve_vsriq_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_n_<supf><mode>): .,. this. (mve_vsriq_m_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12arm: [MVE intrinsics] add ternary_rshift shapeChristophe Lyon2-0/+39
This patch adds the ternary_rshift shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (ternary_rshift): New. * config/arm/arm-mve-builtins-shapes.h (ternary_rshift): New.
2023-05-12arm: [MVE intrinsics] rework vsliqChristophe Lyon5-213/+5
Implement vsliq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vsliq): New. * config/arm/arm-mve-builtins-base.def (vsliq): New. * config/arm/arm-mve-builtins-base.h (vsliq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vsliq. * config/arm/arm_mve.h (vsliq): Remove. (vsliq_m): Remove. (vsliq_n_u8): Remove. (vsliq_n_s8): Remove. (vsliq_n_u16): Remove. (vsliq_n_s16): Remove. (vsliq_n_u32): Remove. (vsliq_n_s32): Remove. (vsliq_m_n_s8): Remove. (vsliq_m_n_s32): Remove. (vsliq_m_n_s16): Remove. (vsliq_m_n_u8): Remove. (vsliq_m_n_u32): Remove. (vsliq_m_n_u16): Remove. (__arm_vsliq_n_u8): Remove. (__arm_vsliq_n_s8): Remove. (__arm_vsliq_n_u16): Remove. (__arm_vsliq_n_s16): Remove. (__arm_vsliq_n_u32): Remove. (__arm_vsliq_n_s32): Remove. (__arm_vsliq_m_n_s8): Remove. (__arm_vsliq_m_n_s32): Remove. (__arm_vsliq_m_n_s16): Remove. (__arm_vsliq_m_n_u8): Remove. (__arm_vsliq_m_n_u32): Remove. (__arm_vsliq_m_n_u16): Remove. (__arm_vsliq): Remove. (__arm_vsliq_m): Remove.
2023-05-12arm: [MVE intrinsics] factorize vsliqChristophe Lyon2-4/+6
Factorize vsliq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn>): Add vsli. * config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vsliq_m_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12arm: [MVE intrinsics] add ternary_lshift shapeChristophe Lyon2-0/+39
This patch adds the ternary_lshift shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (ternary_lshift): New. * config/arm/arm-mve-builtins-shapes.h (ternary_lshift): New.
2023-05-12arm: [MVE intrinsics] rework vpselqChristophe Lyon4-177/+4
Implement vpselq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vpselq): New. * config/arm/arm-mve-builtins-base.def (vpselq): New. * config/arm/arm-mve-builtins-base.h (vpselq): New. * config/arm/arm_mve.h (vpselq): Remove. (vpselq_u8): Remove. (vpselq_s8): Remove. (vpselq_u16): Remove. (vpselq_s16): Remove. (vpselq_u32): Remove. (vpselq_s32): Remove. (vpselq_u64): Remove. (vpselq_s64): Remove. (vpselq_f16): Remove. (vpselq_f32): Remove. (__arm_vpselq_u8): Remove. (__arm_vpselq_s8): Remove. (__arm_vpselq_u16): Remove. (__arm_vpselq_s16): Remove. (__arm_vpselq_u32): Remove. (__arm_vpselq_s32): Remove. (__arm_vpselq_u64): Remove. (__arm_vpselq_s64): Remove. (__arm_vpselq_f16): Remove. (__arm_vpselq_f32): Remove. (__arm_vpselq): Remove.
2023-05-12arm: [MVE intrinsics] add vpsel shapeChristophe Lyon2-0/+40
This patch adds the vpsel shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (vpsel): New. * config/arm/arm-mve-builtins-shapes.h (vpsel): New.
2023-05-12arm: [MVE intrinsics] factorize vpselqChristophe Lyon3-13/+18
Factorize vpselq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm.cc (arm_expand_vcond): Use gen_mve_q instead of gen_mve_vpselq. * config/arm/iterators.md (MVE_VPSELQ_F): New. (mve_insn): Add vpsel. * config/arm/mve.md (@mve_vpselq_<supf><mode>): Rename into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (@mve_vpselq_f<mode>): Rename into ... (@mve_<mve_insn>q_f<mode>): ... this.
2023-05-12arm: [MVE intrinsics] rework vfmaq vfmasq vfmsqChristophe Lyon5-292/+12
Implement vfmaq, vfmasq, vfmsq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vfmaq, vfmasq, vfmsq): New. * config/arm/arm-mve-builtins-base.def (vfmaq, vfmasq, vfmsq): New. * config/arm/arm-mve-builtins-base.h (vfmaq, vfmasq, vfmsq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vfmaq, vfmasq, vfmsq. * config/arm/arm_mve.h (vfmaq): Remove. (vfmasq): Remove. (vfmsq): Remove. (vfmaq_m): Remove. (vfmasq_m): Remove. (vfmsq_m): Remove. (vfmaq_f16): Remove. (vfmaq_n_f16): Remove. (vfmasq_n_f16): Remove. (vfmsq_f16): Remove. (vfmaq_f32): Remove. (vfmaq_n_f32): Remove. (vfmasq_n_f32): Remove. (vfmsq_f32): Remove. (vfmaq_m_f32): Remove. (vfmaq_m_f16): Remove. (vfmaq_m_n_f32): Remove. (vfmaq_m_n_f16): Remove. (vfmasq_m_n_f32): Remove. (vfmasq_m_n_f16): Remove. (vfmsq_m_f32): Remove. (vfmsq_m_f16): Remove. (__arm_vfmaq_f16): Remove. (__arm_vfmaq_n_f16): Remove. (__arm_vfmasq_n_f16): Remove. (__arm_vfmsq_f16): Remove. (__arm_vfmaq_f32): Remove. (__arm_vfmaq_n_f32): Remove. (__arm_vfmasq_n_f32): Remove. (__arm_vfmsq_f32): Remove. (__arm_vfmaq_m_f32): Remove. (__arm_vfmaq_m_f16): Remove. (__arm_vfmaq_m_n_f32): Remove. (__arm_vfmaq_m_n_f16): Remove. (__arm_vfmasq_m_n_f32): Remove. (__arm_vfmasq_m_n_f16): Remove. (__arm_vfmsq_m_f32): Remove. (__arm_vfmsq_m_f16): Remove. (__arm_vfmaq): Remove. (__arm_vfmasq): Remove. (__arm_vfmsq): Remove. (__arm_vfmaq_m): Remove. (__arm_vfmasq_m): Remove. (__arm_vfmsq_m): Remove.
2023-05-12arm: [MVE intrinsics] factorize vfmaq vfmsq vfmasqChristophe Lyon2-108/+35
Factorize vmvnq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_FP_M_BINARY): Add VFMAQ_M_F, VFMSQ_M_F. (MVE_FP_M_N_BINARY): Add VFMAQ_M_N_F, VFMASQ_M_N_F. (MVE_VFMxQ_F, MVE_VFMAxQ_N_F): New. (mve_insn): Add vfma, vfmas, vfms. * config/arm/mve.md (mve_vfmaq_f<mode>, mve_vfmsq_f<mode>): Merge into ... (@mve_<mve_insn>q_f<mode>): ... this. (mve_vfmaq_n_f<mode>, mve_vfmasq_n_f<mode>): Merge into ... (@mve_<mve_insn>q_n_f<mode>): ... this. (mve_vfmaq_m_f<mode>, mve_vfmsq_m_f<mode>): Merge into @mve_<mve_insn>q_m_f<mode>. (mve_vfmaq_m_n_f<mode>, mve_vfmasq_m_n_f<mode>): Merge into @mve_<mve_insn>q_m_n_f<mode>.
2023-05-12arm: [MVE intrinsics] add ternary_opt_n shapeChristophe Lyon2-0/+31
This patch adds the ternary_opt_n shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (ternary_opt_n): New. * config/arm/arm-mve-builtins-shapes.h (ternary_opt_n): New.
2023-05-12arm: [MVE intrinsics] rework vmvnqChristophe Lyon4-438/+12
Implement vmvnq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (FUNCTION_WITH_RTX_M_N_NO_F): New. (vmvnq): New. * config/arm/arm-mve-builtins-base.def (vmvnq): New. * config/arm/arm-mve-builtins-base.h (vmvnq): New. * config/arm/arm_mve.h (vmvnq): Remove. (vmvnq_m): Remove. (vmvnq_x): Remove. (vmvnq_s8): Remove. (vmvnq_s16): Remove. (vmvnq_s32): Remove. (vmvnq_n_s16): Remove. (vmvnq_n_s32): Remove. (vmvnq_u8): Remove. (vmvnq_u16): Remove. (vmvnq_u32): Remove. (vmvnq_n_u16): Remove. (vmvnq_n_u32): Remove. (vmvnq_m_u8): Remove. (vmvnq_m_s8): Remove. (vmvnq_m_u16): Remove. (vmvnq_m_s16): Remove. (vmvnq_m_u32): Remove. (vmvnq_m_s32): Remove. (vmvnq_m_n_s16): Remove. (vmvnq_m_n_u16): Remove. (vmvnq_m_n_s32): Remove. (vmvnq_m_n_u32): Remove. (vmvnq_x_s8): Remove. (vmvnq_x_s16): Remove. (vmvnq_x_s32): Remove. (vmvnq_x_u8): Remove. (vmvnq_x_u16): Remove. (vmvnq_x_u32): Remove. (vmvnq_x_n_s16): Remove. (vmvnq_x_n_s32): Remove. (vmvnq_x_n_u16): Remove. (vmvnq_x_n_u32): Remove. (__arm_vmvnq_s8): Remove. (__arm_vmvnq_s16): Remove. (__arm_vmvnq_s32): Remove. (__arm_vmvnq_n_s16): Remove. (__arm_vmvnq_n_s32): Remove. (__arm_vmvnq_u8): Remove. (__arm_vmvnq_u16): Remove. (__arm_vmvnq_u32): Remove. (__arm_vmvnq_n_u16): Remove. (__arm_vmvnq_n_u32): Remove. (__arm_vmvnq_m_u8): Remove. (__arm_vmvnq_m_s8): Remove. (__arm_vmvnq_m_u16): Remove. (__arm_vmvnq_m_s16): Remove. (__arm_vmvnq_m_u32): Remove. (__arm_vmvnq_m_s32): Remove. (__arm_vmvnq_m_n_s16): Remove. (__arm_vmvnq_m_n_u16): Remove. (__arm_vmvnq_m_n_s32): Remove. (__arm_vmvnq_m_n_u32): Remove. (__arm_vmvnq_x_s8): Remove. (__arm_vmvnq_x_s16): Remove. (__arm_vmvnq_x_s32): Remove. (__arm_vmvnq_x_u8): Remove. (__arm_vmvnq_x_u16): Remove. (__arm_vmvnq_x_u32): Remove. (__arm_vmvnq_x_n_s16): Remove. (__arm_vmvnq_x_n_s32): Remove. (__arm_vmvnq_x_n_u16): Remove. (__arm_vmvnq_x_n_u32): Remove. (__arm_vmvnq): Remove. (__arm_vmvnq_m): Remove. (__arm_vmvnq_x): Remove.
2023-05-12arm: [MVE intrinsics] factorize vmvnqChristophe Lyon2-6/+9
Factorize vmvnq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vmvn. * config/arm/mve.md (mve_vmvnq_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vmvnq_m_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this. (mve_vmvnq_m_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12arm: [MVE intrinsics] add mvn shapeChristophe Lyon2-0/+50
This patch adds the mvn shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (mvn): New. * config/arm/arm-mve-builtins-shapes.h (mvn): New.
2023-05-12arm: [MVE intrinsics] rework vbrsrqChristophe Lyon4-426/+4
Implement vbrsrq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vbrsrq): New. * config/arm/arm-mve-builtins-base.def (vbrsrq): New. * config/arm/arm-mve-builtins-base.h (vbrsrq): New. * config/arm/arm_mve.h (vbrsrq): Remove. (vbrsrq_m): Remove. (vbrsrq_x): Remove. (vbrsrq_n_f16): Remove. (vbrsrq_n_f32): Remove. (vbrsrq_n_u8): Remove. (vbrsrq_n_s8): Remove. (vbrsrq_n_u16): Remove. (vbrsrq_n_s16): Remove. (vbrsrq_n_u32): Remove. (vbrsrq_n_s32): Remove. (vbrsrq_m_n_s8): Remove. (vbrsrq_m_n_s32): Remove. (vbrsrq_m_n_s16): Remove. (vbrsrq_m_n_u8): Remove. (vbrsrq_m_n_u32): Remove. (vbrsrq_m_n_u16): Remove. (vbrsrq_m_n_f32): Remove. (vbrsrq_m_n_f16): Remove. (vbrsrq_x_n_s8): Remove. (vbrsrq_x_n_s16): Remove. (vbrsrq_x_n_s32): Remove. (vbrsrq_x_n_u8): Remove. (vbrsrq_x_n_u16): Remove. (vbrsrq_x_n_u32): Remove. (vbrsrq_x_n_f16): Remove. (vbrsrq_x_n_f32): Remove. (__arm_vbrsrq_n_u8): Remove. (__arm_vbrsrq_n_s8): Remove. (__arm_vbrsrq_n_u16): Remove. (__arm_vbrsrq_n_s16): Remove. (__arm_vbrsrq_n_u32): Remove. (__arm_vbrsrq_n_s32): Remove. (__arm_vbrsrq_m_n_s8): Remove. (__arm_vbrsrq_m_n_s32): Remove. (__arm_vbrsrq_m_n_s16): Remove. (__arm_vbrsrq_m_n_u8): Remove. (__arm_vbrsrq_m_n_u32): Remove. (__arm_vbrsrq_m_n_u16): Remove. (__arm_vbrsrq_x_n_s8): Remove. (__arm_vbrsrq_x_n_s16): Remove. (__arm_vbrsrq_x_n_s32): Remove. (__arm_vbrsrq_x_n_u8): Remove. (__arm_vbrsrq_x_n_u16): Remove. (__arm_vbrsrq_x_n_u32): Remove. (__arm_vbrsrq_n_f16): Remove. (__arm_vbrsrq_n_f32): Remove. (__arm_vbrsrq_m_n_f32): Remove. (__arm_vbrsrq_m_n_f16): Remove. (__arm_vbrsrq_x_n_f16): Remove. (__arm_vbrsrq_x_n_f32): Remove. (__arm_vbrsrq): Remove. (__arm_vbrsrq_m): Remove. (__arm_vbrsrq_x): Remove.
2023-05-12arm: [MVE intrinsics] factorize vrbsrqChristophe Lyon2-10/+20
Factorize vrbsrq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VBRSR_M_N_FP, MVE_VBRSR_N_FP): New. (mve_insn): Add vbrsr. * config/arm/mve.md (mve_vbrsrq_n_f<mode>): Rename into ... (@mve_<mve_insn>q_n_f<mode>): ... this. (mve_vbrsrq_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vbrsrq_m_n_<supf><mode>): Rename into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this. (mve_vbrsrq_m_n_f<mode>): Rename into ... (@mve_<mve_insn>q_m_n_f<mode>): ... this.
2023-05-12arm: [MVE intrinsics] add binary_imm32 shapeChristophe Lyon2-0/+28
This patch adds the binary_imm32 shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_imm32): New. * config/arm/arm-mve-builtins-shapes.h (binary_imm32): New.
2023-05-12arm: [MVE intrinsics] rework vqshluqChristophe Lyon4-111/+3
Implement vqshluq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vqshluq): New. * config/arm/arm-mve-builtins-base.def (vqshluq): New. * config/arm/arm-mve-builtins-base.h (vqshluq): New. * config/arm/arm_mve.h (vqshluq): Remove. (vqshluq_m): Remove. (vqshluq_n_s8): Remove. (vqshluq_n_s16): Remove. (vqshluq_n_s32): Remove. (vqshluq_m_n_s8): Remove. (vqshluq_m_n_s16): Remove. (vqshluq_m_n_s32): Remove. (__arm_vqshluq_n_s8): Remove. (__arm_vqshluq_n_s16): Remove. (__arm_vqshluq_n_s32): Remove. (__arm_vqshluq_m_n_s8): Remove. (__arm_vqshluq_m_n_s16): Remove. (__arm_vqshluq_m_n_s32): Remove. (__arm_vqshluq): Remove. (__arm_vqshluq_m): Remove.
2023-05-12arm: [MVE intrinsics] factorize vqshluqChristophe Lyon2-6/+12
Factorize vqshluq builtins so that they use parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (mve_insn): Add vqshlu. (supf): Add VQSHLUQ_M_N_S, VQSHLUQ_N_S. (VQSHLUQ_M_N, VQSHLUQ_N): New. * config/arm/mve.md (mve_vqshluq_n_s<mode>): Change name into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vqshluq_m_n_s<mode>): Change name into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
2023-05-12arm: [MVE intrinsics] add binary_lshift_unsigned shapeChristophe Lyon2-0/+59
This patch adds the binary_lshift_unsigned shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_lshift_unsigned): New. * config/arm/arm-mve-builtins-shapes.h (binary_lshift_unsigned): New.
2023-05-12arm: [MVE intrinsics] rework vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq ↵Christophe Lyon5-184/+16
vrmlsldavhaxq Implement vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vrmlaldavhaq) (vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New. * config/arm/arm-mve-builtins-base.def (vrmlaldavhaq) (vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New. * config/arm/arm-mve-builtins-base.h (vrmlaldavhaq) (vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq): New. * config/arm/arm-mve-builtins-functions.h: Handle vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq. * config/arm/arm_mve.h (vrmlaldavhaq): Remove. (vrmlaldavhaxq): Remove. (vrmlsldavhaq): Remove. (vrmlsldavhaxq): Remove. (vrmlaldavhaq_p): Remove. (vrmlaldavhaxq_p): Remove. (vrmlsldavhaq_p): Remove. (vrmlsldavhaxq_p): Remove. (vrmlaldavhaq_s32): Remove. (vrmlaldavhaq_u32): Remove. (vrmlaldavhaxq_s32): Remove. (vrmlsldavhaq_s32): Remove. (vrmlsldavhaxq_s32): Remove. (vrmlaldavhaq_p_s32): Remove. (vrmlaldavhaq_p_u32): Remove. (vrmlaldavhaxq_p_s32): Remove. (vrmlsldavhaq_p_s32): Remove. (vrmlsldavhaxq_p_s32): Remove. (__arm_vrmlaldavhaq_s32): Remove. (__arm_vrmlaldavhaq_u32): Remove. (__arm_vrmlaldavhaxq_s32): Remove. (__arm_vrmlsldavhaq_s32): Remove. (__arm_vrmlsldavhaxq_s32): Remove. (__arm_vrmlaldavhaq_p_s32): Remove. (__arm_vrmlaldavhaq_p_u32): Remove. (__arm_vrmlaldavhaxq_p_s32): Remove. (__arm_vrmlsldavhaq_p_s32): Remove. (__arm_vrmlsldavhaxq_p_s32): Remove. (__arm_vrmlaldavhaq): Remove. (__arm_vrmlaldavhaxq): Remove. (__arm_vrmlsldavhaq): Remove. (__arm_vrmlsldavhaxq): Remove. (__arm_vrmlaldavhaq_p): Remove. (__arm_vrmlaldavhaxq_p): Remove. (__arm_vrmlsldavhaq_p): Remove. (__arm_vrmlsldavhaxq_p): Remove.
2023-05-12arm: [MVE intrinsics] factorize vrmlaldavhaq vrmlaldavhaxq vrmlsldavhaq ↵Christophe Lyon2-125/+44
vrmlsldavhaxq Factorize vrmlaldavhaq, vrmlaldavhaxq, vrmlsldavhaq, vrmlsldavhaxq builtins so that they use the same parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VRMLxLDAVHAxQ) (MVE_VRMLxLDAVHAxQ_P): New. (mve_insn): Add vrmlaldavha, vrmlaldavhax, vrmlsldavha, vrmlsldavhax. (supf): Add VRMLALDAVHAXQ_P_S, VRMLALDAVHAXQ_S, VRMLSLDAVHAQ_P_S, VRMLSLDAVHAQ_S, VRMLSLDAVHAXQ_P_S, VRMLSLDAVHAXQ_S, VRMLALDAVHAQ_P_S. * config/arm/mve.md (mve_vrmlaldavhaq_<supf>v4si) (mve_vrmlaldavhaxq_sv4si, mve_vrmlsldavhaxq_sv4si) (mve_vrmlsldavhaq_sv4si): Merge into ... (@mve_<mve_insn>q_<supf>v4si): ... this. (mve_vrmlaldavhaq_p_sv4si, mve_vrmlaldavhaq_p_uv4si) (mve_vrmlaldavhaxq_p_sv4si, mve_vrmlsldavhaq_p_sv4si) (mve_vrmlsldavhaxq_p_sv4si): Merge into ... (@mve_<mve_insn>q_p_<supf>v4si): ... this.
2023-05-12arm: [MVE intrinsics] rework vqdmullbq vqdmulltqChristophe Lyon4-294/+6
Implement vqdmullbq, vqdmulltq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vqdmullbq, vqdmulltq): New. * config/arm/arm-mve-builtins-base.def (vqdmullbq, vqdmulltq): New. * config/arm/arm-mve-builtins-base.h (vqdmullbq, vqdmulltq): New. * config/arm/arm_mve.h (vqdmulltq): Remove. (vqdmullbq): Remove. (vqdmullbq_m): Remove. (vqdmulltq_m): Remove. (vqdmulltq_s16): Remove. (vqdmulltq_n_s16): Remove. (vqdmullbq_s16): Remove. (vqdmullbq_n_s16): Remove. (vqdmulltq_s32): Remove. (vqdmulltq_n_s32): Remove. (vqdmullbq_s32): Remove. (vqdmullbq_n_s32): Remove. (vqdmullbq_m_n_s32): Remove. (vqdmullbq_m_n_s16): Remove. (vqdmullbq_m_s32): Remove. (vqdmullbq_m_s16): Remove. (vqdmulltq_m_n_s32): Remove. (vqdmulltq_m_n_s16): Remove. (vqdmulltq_m_s32): Remove. (vqdmulltq_m_s16): Remove. (__arm_vqdmulltq_s16): Remove. (__arm_vqdmulltq_n_s16): Remove. (__arm_vqdmullbq_s16): Remove. (__arm_vqdmullbq_n_s16): Remove. (__arm_vqdmulltq_s32): Remove. (__arm_vqdmulltq_n_s32): Remove. (__arm_vqdmullbq_s32): Remove. (__arm_vqdmullbq_n_s32): Remove. (__arm_vqdmullbq_m_n_s32): Remove. (__arm_vqdmullbq_m_n_s16): Remove. (__arm_vqdmullbq_m_s32): Remove. (__arm_vqdmullbq_m_s16): Remove. (__arm_vqdmulltq_m_n_s32): Remove. (__arm_vqdmulltq_m_n_s16): Remove. (__arm_vqdmulltq_m_s32): Remove. (__arm_vqdmulltq_m_s16): Remove. (__arm_vqdmulltq): Remove. (__arm_vqdmullbq): Remove. (__arm_vqdmullbq_m): Remove. (__arm_vqdmulltq_m): Remove.
2023-05-12arm: [MVE intrinsics] factorize vqdmullbq vqdmulltqChristophe Lyon2-80/+56
Factorize vqdmullbq, vqdmulltq builtins so that they use the same parameterized names. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/iterators.md (MVE_VQDMULLxQ, MVE_VQDMULLxQ_M) (MVE_VQDMULLxQ_M_N, MVE_VQDMULLxQ_N): New. (mve_insn): Add vqdmullb, vqdmullt. (supf): Add VQDMULLBQ_S, VQDMULLBQ_M_S, VQDMULLBQ_M_N_S, VQDMULLBQ_N_S, VQDMULLTQ_S, VQDMULLTQ_M_S, VQDMULLTQ_M_N_S, VQDMULLTQ_N_S. * config/arm/mve.md (mve_vqdmullbq_n_s<mode>) (mve_vqdmulltq_n_s<mode>): Merge into ... (@mve_<mve_insn>q_n_<supf><mode>): ... this. (mve_vqdmullbq_s<mode>, mve_vqdmulltq_s<mode>): Merge into ... (@mve_<mve_insn>q_<supf><mode>): ... this. (mve_vqdmullbq_m_n_s<mode>, mve_vqdmulltq_m_n_s<mode>): Merge into ... (@mve_<mve_insn>q_m_n_<supf><mode>): ... this. (mve_vqdmullbq_m_s<mode>, mve_vqdmulltq_m_s<mode>): Merge into ... (@mve_<mve_insn>q_m_<supf><mode>): ... this.
2023-05-12arm: [MVE intrinsics] add binary_widen_opt_n shapeChristophe Lyon2-0/+50
This patch adds the binary_widen_opt_n shape description. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-shapes.cc (binary_widen_opt_n): New. * config/arm/arm-mve-builtins-shapes.h (binary_widen_opt_n): New.
2023-05-12RISC-V: Suppress unused parameter warning in riscv-common.ccKito Cheng1-9/+3
gcc/ChangeLog: * common/config/riscv/riscv-common.cc (riscv_select_multilib_by_abi): Drop unused parameter. (riscv_select_multilib): Ditto. (riscv_compute_multilib): Update call site of riscv_select_multilib_by_abi and riscv_select_multilib_by_abi.
2023-05-12RISC-V: Fix fail of vmv-imm-rv64.c in rv32Juzhe Zhong1-1/+1
After update local codebase to the trunk. I realize there is one more fail in RV32. After this patch, all fails of RVV are cleaned up. Thanks. FAIL: gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c -O3 -ftree-vectorize (test for excess errors) Excess errors: cc1: error: ABI requires '-march=rv32' gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: Add ABI Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
2023-05-12RISC-V: Add basic vec_init for VLS RVV auto-vectorizationJuzhe Zhong22-0/+1547
typedef int8_t vnx16qi __attribute__((vector_size (16))); typedef int8_t vnx16qi __attribute__ ((vector_size (16))); typedef int8_t vnx32qi __attribute__ ((vector_size (32))); typedef int8_t vnx64qi __attribute__ ((vector_size (64))); typedef int8_t vnx128qi __attribute__ ((vector_size (128))); __attribute__ ((noipa)) void f_vnx128qi (int8_t a, int8_t b, int8_t c, int8_t d, int8_t e, int8_t f, int8_t g, int8_t h, int8_t *out) { vnx128qi v = {a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h, a, b, c, d, e, f, g, h}; *(vnx128qi *) out = v; } This patch codegen: f_vnx128qi: andi a1,a1,0xff andi a0,a0,0xff slli a1,a1,8 andi a2,a2,0xff or a1,a1,a0 slli a2,a2,16 andi a3,a3,0xff or a2,a2,a1 slli a3,a3,24 andi a4,a4,0xff or a3,a3,a2 slli a4,a4,32 andi a5,a5,0xff or a4,a4,a3 slli a5,a5,40 andi a6,a6,0xff or a5,a5,a4 slli a6,a6,48 or a6,a6,a5 vsetvli a5,zero,e64,m8,ta,ma ld a5,0(sp) slli a7,a7,56 or a7,a7,a6 vmv.v.x v8,a7 vs8r.v v8,0(a5) ret We support more optimizations cases in the future. But they are not included in this patch. Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai> gcc/ChangeLog: * config/riscv/autovec.md (vec_init<mode><vel>): New pattern. * config/riscv/riscv-protos.h (expand_vec_init): New function. * config/riscv/riscv-v.cc (class rvv_builder): New class. (rvv_builder::can_duplicate_repeating_sequence_p): New function. (rvv_builder::get_merged_repeating_sequence): Ditto. (expand_vector_init_insert_elems): Ditto. (expand_vec_init): Ditto. * config/riscv/vector-iterators.md: New attribute. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/rvv.exp: * gcc.target/riscv/rvv/autovec/vls-vlmax/insert-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-4.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-5.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat-6.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: New test. * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: New test.
2023-05-12RISC-V: Reorganize binary autovec testcasesPan Li60-0/+2
1. This patch is moving binary autovec testcases into binop directory to make it easier to maintain. 2. Current binary autovec only tested in LMUL = 1, enable testing in LMUL = 2/4/8. Tested on both rv32/rv64, with no fails in RVV. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/shift-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-run.c: ...here. * gcc.target/riscv/rvv/autovec/shift-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/shift-scalar-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-scalar-template.h: ...here. * gcc.target/riscv/rvv/autovec/shift-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/shift-template.h: ...here. * gcc.target/riscv/rvv/autovec/vadd-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vadd-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: ...here. * gcc.target/riscv/rvv/autovec/vadd-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vadd-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vadd-template.h: ...here. * gcc.target/riscv/rvv/autovec/vand-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vand-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-run.c: ...here. * gcc.target/riscv/rvv/autovec/vand-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vand-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vand-template.h: ...here. * gcc.target/riscv/rvv/autovec/vdiv-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vdiv-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: ...here. * gcc.target/riscv/rvv/autovec/vdiv-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vdiv-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vdiv-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmax-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmax-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: ...here. * gcc.target/riscv/rvv/autovec/vmax-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmax-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmax-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmin-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmin-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: ...here. * gcc.target/riscv/rvv/autovec/vmin-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmin-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmin-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmul-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vmul-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: ...here. * gcc.target/riscv/rvv/autovec/vmul-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vmul-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vmul-template.h: ...here. * gcc.target/riscv/rvv/autovec/vor-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vor-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-run.c: ...here. * gcc.target/riscv/rvv/autovec/vor-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vor-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vor-template.h: ...here. * gcc.target/riscv/rvv/autovec/vrem-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vrem-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: ...here. * gcc.target/riscv/rvv/autovec/vrem-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vrem-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vrem-template.h: ...here. * gcc.target/riscv/rvv/autovec/vsub-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vsub-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: ...here. * gcc.target/riscv/rvv/autovec/vsub-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vsub-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vsub-template.h: ...here. * gcc.target/riscv/rvv/autovec/vxor-run-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-run-template.h: ...here. * gcc.target/riscv/rvv/autovec/vxor-run.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: ...here. * gcc.target/riscv/rvv/autovec/vxor-rv32gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-rv32gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-rv64gcv.c: ...here. * gcc.target/riscv/rvv/autovec/vxor-template.h: Moved to... * gcc.target/riscv/rvv/autovec/binop/vxor-template.h: ...here. * gcc.target/riscv/rvv/rvv.exp: Add autovec LMUL = 2/4/8 for binary. Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai>
2023-05-12RISC-V: Fix RVV binary auto-vectorizaiton test failsPan Li22-23/+23
In rv32: FAIL: gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmin-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vand-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vrem-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmul-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vand-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vdiv-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vor-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/shift-scalar-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vmax-run.c -O3 -ftree-vectorize (test for excess errors) FAIL: gcc.target/riscv/rvv/autovec/vor-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) In rv64: FAIL: gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c -O3 -ftree-vectorize (test for excess errors) Signed-off-by: Juzhe Zhong <juzhe.zhong@rivai.ai> gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/shift-run.c: Fix fail. * gcc.target/riscv/rvv/autovec/shift-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/shift-scalar-run.c: Ditto. * gcc.target/riscv/rvv/autovec/shift-scalar-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vadd-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vand-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vand-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vdiv-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vdiv-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmax-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmax-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmin-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmin-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vmul-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vmul-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vor-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vrem-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vrem-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vsub-rv64gcv.c: Ditto. * gcc.target/riscv/rvv/autovec/vxor-run.c: Ditto. * gcc.target/riscv/rvv/autovec/vxor-rv64gcv.c: Ditto.
2023-05-12rs6000: Change ilp32 target check for scalar-extract-sig and ↵Haochen Gui3-3/+3
scalar-insert-exp test cases gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-extract-sig-2.c: Replace ilp32 check with dg-skip-if has_arch_ppc64. * gcc.target/powerpc/bfp/scalar-insert-exp-2.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-5.c: Likewise.
2023-05-12rs6000: Change mode and insn condition for scalar insert exp instructionHaochen Gui8-14/+14
gcc/ * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_insert_exp): Replace bif-pattern from xsiexpdp to xsiexpdp_di. (__builtin_vsx_scalar_insert_exp_dp): Replace bif-pattern from xsiexpdpf to xsiexpdpf_di. * config/rs6000/vsx.md (xsiexpdp): Rename to... (xsiexpdp_<mode>): ..., set the mode of second operand to GPR and replace TARGET_64BIT with TARGET_POWERPC64. (xsiexpdpf): Rename to... (xsiexpdpf_<mode>): ..., set the mode of second operand to GPR and replace TARGET_64BIT with TARGET_POWERPC64. gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-insert-exp-0.c: Replace lp64 check with has_arch_ppc64. * gcc.target/powerpc/bfp/scalar-insert-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-12.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-13.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-3.c: Likewise. * gcc.target/powerpc/bfp/scalar-insert-exp-4.c: Likewise.
2023-05-12rs6000: Change mode and insn condition for scalar extract sig instructionHaochen Gui5-5/+5
gcc/ * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_extract_sig): Set return type to const signed long long. * config/rs6000/vsx.md (xsxsigdp): Replace TARGET_64BIT with TARGET_POWERPC64. gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-extract-sig-0.c: Replace lp64 check with has_arch_ppc64. * gcc.target/powerpc/bfp/scalar-extract-sig-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-sig-6.c: Likewise.
2023-05-12rs6000: Change mode and insn condition for scalar extract exp instructionHaochen Gui7-34/+10
gcc/ * config/rs6000/rs6000-builtins.def (__builtin_vsx_scalar_extract_exp): Set return type to const signed int and set its bif-pattern to xsxexpdp_si, move it from power9-64 to power9 catalog. * config/rs6000/vsx.md (xsxexpdp): Rename to ... (xsxexpdp_<mode>): ..., set mode of operand 0 to GPR and remove TARGET_64BIT check. * doc/extend.texi (scalar_extract_exp): Remove 64-bit environment requirement when it has a 64-bit argument. gcc/testsuite/ * gcc.target/powerpc/bfp/scalar-extract-exp-0.c: Remove lp64 check. * gcc.target/powerpc/bfp/scalar-extract-exp-1.c: Likewise. * gcc.target/powerpc/bfp/scalar-extract-exp-2.c: Delete as the case is invalid now. * gcc.target/powerpc/bfp/scalar-extract-exp-6.c: Remove lp64 check.
2023-05-12Var-Tracking: Typedef pointer_mux<tree_node, rtx_def> as decl_or_valuePan Li2-52/+37
The decl_or_value is defined as void * before this PATCH. It will take care of both the tree_node and rtx_def. Unfortunately, given a void pointer cannot tell the input is tree_node or rtx_def. Then we have some implicit structure layout requirement similar as below. Or we will touch unreasonable bits when cast void * to tree_node or rtx_def. +--------+-----------+----------+ | offset | tree_node | rtx_def | +--------+-----------+----------+ | 0 | code: 16 | code: 16 | <- require the same location and bitssize +--------+-----------+----------+ | 16 | ... | mode: 8 | +--------+-----------+----------+ | ... | +--------+-----------+----------+ | 24 | ... | ... | +--------+-----------+----------+ This behavior blocks the PATCH that extend the rtx_def mode from 8 to 16 bits for running out of machine mode. This PATCH introduced the pointer_mux to tell the input is tree_node or rtx_def, and decouple the above implicit dependency. Signed-off-by: Pan Li <pan2.li@intel.com> Co-Authored-By: Richard Sandiford <richard.sandiford@arm.com> Co-Authored-By: Richard Biener <rguenther@suse.de> Co-Authored-By: Jakub Jelinek <jakub@redhat.com> gcc/ChangeLog: * mux-utils.h: Add overload operator == and != for pointer_mux. * var-tracking.cc: Included mux-utils.h for pointer_tmux. (decl_or_value): Changed from void * to pointer_mux<tree_node, rtx_def>. (dv_is_decl_p): Reconciled to the new type, aka pointer_mux. (dv_as_decl): Ditto. (dv_as_opaque): Removed due to unnecessary. (struct variable_hasher): Take decl_or_value as compare_type. (variable_hasher::equal): Diito. (dv_from_decl): Reconciled to the new type, aka pointer_mux. (dv_from_value): Ditto. (attrs_list_member): Ditto. (vars_copy): Ditto. (var_reg_decl_set): Ditto. (var_reg_delete_and_set): Ditto. (find_loc_in_1pdv): Ditto. (canonicalize_values_star): Ditto. (variable_post_merge_new_vals): Ditto. (dump_onepart_variable_differences): Ditto. (variable_different_p): Ditto. (set_slot_part): Ditto. (clobber_slot_part): Ditto. (clobber_variable_part): Ditto.
2023-05-12Daily bump.GCC Administrator6-1/+1980
2023-05-12PR modula2/109810 ICE fix when an array is assigned by a larger stringGaius Mulley6-139/+183
This patch fixes an ICE when an array variable is assigned with a string which exceeds the array size. It improves the accuracy of the virtual token used to indicate the error message. gcc/m2/ChangeLog: PR modula2/109810 * gm2-compiler/M2ALU.mod (ConvertConstToType): Use PrepareCopyString in place of DoCopyString. * gm2-compiler/M2GenGCC.def (DoCopyString): Rename to ... (PrepareCopyString): ... this. * gm2-compiler/M2GenGCC.mod (CodeStatement): Call CodeReturnValue with a single parameter. Call CodeXIndr with a single parameter. (CodeReturnValue): Remove parameters and replace with a single quadno. Reimplement using PrepareCopyString. Issue error if the string exceeds designator space. (DoCopyString): Reimplement and rename to ... (PrepareCopyString): ... this. (CodeXIndr): Remove parameters and replace with a single quadno. Reimplement using PrepareCopyString. Issue error if the string exceeds designator space. (CodeBecomes): Remove parameters and replace with a single quadno. Reimplement using PrepareCopyString. Issue error if the string exceeds designator space. * gm2-compiler/M2Quads.def (BuildReturn): Rename parameter to tokreturn. * gm2-compiler/M2Quads.mod (BuildReturn): Rename parameter to tokreturn. Rename tokno to tokcombined. gcc/testsuite/ChangeLog: PR modula2/109810 * gm2/pim/fail/highice.mod: New test. Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
2023-05-11c++: 'mutable' subobject of constexpr variable [PR109745]Patrick Palka4-4/+96
r13-2701-g7107ea6fb933f1 made us correctly accept during constexpr evaluation 'mutable' member accesses of objects constructed during that evaluation, while continuing to reject such accesses for constexpr objects constructed outside of that evaluation, by considering the CONSTRUCTOR_MUTABLE_POISON flag during cxx_eval_component_reference. However, this flag is set only for the outermost CONSTRUCTOR of a constexpr variable initializer, so if we're accessing a 'mutable' member of a nested CONSTRUCTOR, the flag won't be set and we won't reject the access. This can lead to us accepting invalid code, as in the first testcase, or even wrong code generation due to our speculative constexpr evaluation, as in the second and third testcase. This patch fixes this by setting CONSTRUCTOR_MUTABLE_POISON recursively rather than only on the outermost CONSTRUCTOR. PR c++/109745 gcc/cp/ChangeLog: * typeck2.cc (poison_mutable_constructors): Define. (store_init_value): Use it instead of setting CONSTRUCTOR_MUTABLE_POISON directly. gcc/testsuite/ChangeLog: * g++.dg/cpp0x/constexpr-mutable4.C: New test. * g++.dg/cpp0x/constexpr-mutable5.C: New test. * g++.dg/cpp1y/constexpr-mutable2.C: New test.
2023-05-11aarch64: convert vector shift + bitwise and + multiply to vector comparemtsamis2-0/+133
When using SWAR (SIMD in a register) techniques a comparison operation within such a register can be made by using a combination of shifts, bitwise and and multiplication. If code using this scheme is vectorized then there is potential to replace all these operations with a single vector comparison, by reinterpreting the vector types to match the width of the SWAR register. For example, for the test function packed_cmp_16_32, the original generated code is: ldr q0, [x0] add w1, w1, 1 ushr v0.4s, v0.4s, 15 and v0.16b, v0.16b, v2.16b shl v1.4s, v0.4s, 16 sub v0.4s, v1.4s, v0.4s str q0, [x0], 16 cmp w2, w1 bhi .L20 with this pattern the above can be optimized to: ldr q0, [x0] add w1, w1, 1 cmlt v0.8h, v0.8h, #0 str q0, [x0], 16 cmp w2, w1 bhi .L20 The effect is similar for x86-64. Bootstrapped and reg-tested for x86 and aarch64. gcc/ChangeLog: * match.pd: simplify vector shift + bit_and + multiply. gcc/testsuite/ChangeLog: * gcc.target/aarch64/swar_to_vec_cmp.c: New test. Signed-off-by: Manolis Tsamis <manolis.tsamis@vrull.eu> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2023-05-11arm: [MVE intrinsics] rework vmlaq vmlasq vqdmlahq vqdmlashq vqrdmlahq ↵Christophe Lyon5-894/+24
vqrdmlashq Implement vmlaq, vmlasq, vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq using the new MVE builtins framework. 2022-12-12 Christophe Lyon <christophe.lyon@arm.com> gcc/ * config/arm/arm-mve-builtins-base.cc (vmlaq, vmlasq, vqdmlahq) (vqdmlashq, vqrdmlahq, vqrdmlashq): New. * config/arm/arm-mve-builtins-base.def (vmlaq, vmlasq, vqdmlahq) (vqdmlashq, vqrdmlahq, vqrdmlashq): New. * config/arm/arm-mve-builtins-base.h (vmlaq, vmlasq, vqdmlahq) (vqdmlashq, vqrdmlahq, vqrdmlashq): New. * config/arm/arm-mve-builtins.cc (function_instance::has_inactive_argument): Handle vmlaq, vmlasq, vqdmlahq, vqdmlashq, vqrdmlahq, vqrdmlashq. * config/arm/arm_mve.h (vqrdmlashq): Remove. (vqrdmlahq): Remove. (vqdmlashq): Remove. (vqdmlahq): Remove. (vmlasq): Remove. (vmlaq): Remove. (vmlaq_m): Remove. (vmlasq_m): Remove. (vqdmlashq_m): Remove. (vqdmlahq_m): Remove. (vqrdmlahq_m): Remove. (vqrdmlashq_m): Remove. (vmlasq_n_u8): Remove. (vmlaq_n_u8): Remove. (vqrdmlashq_n_s8): Remove. (vqrdmlahq_n_s8): Remove. (vqdmlahq_n_s8): Remove. (vqdmlashq_n_s8): Remove. (vmlasq_n_s8): Remove. (vmlaq_n_s8): Remove. (vmlasq_n_u16): Remove. (vmlaq_n_u16): Remove. (vqrdmlashq_n_s16): Remove. (vqrdmlahq_n_s16): Remove. (vqdmlashq_n_s16): Remove. (vqdmlahq_n_s16): Remove. (vmlasq_n_s16): Remove. (vmlaq_n_s16): Remove. (vmlasq_n_u32): Remove. (vmlaq_n_u32): Remove. (vqrdmlashq_n_s32): Remove. (vqrdmlahq_n_s32): Remove. (vqdmlashq_n_s32): Remove. (vqdmlahq_n_s32): Remove. (vmlasq_n_s32): Remove. (vmlaq_n_s32): Remove. (vmlaq_m_n_s8): Remove. (vmlaq_m_n_s32): Remove. (vmlaq_m_n_s16): Remove. (vmlaq_m_n_u8): Remove. (vmlaq_m_n_u32): Remove. (vmlaq_m_n_u16): Remove. (vmlasq_m_n_s8): Remove. (vmlasq_m_n_s32): Remove. (vmlasq_m_n_s16): Remove. (vmlasq_m_n_u8): Remove. (vmlasq_m_n_u32): Remove. (vmlasq_m_n_u16): Remove. (vqdmlashq_m_n_s8): Remove. (vqdmlashq_m_n_s32): Remove. (vqdmlashq_m_n_s16): Remove. (vqdmlahq_m_n_s8): Remove. (vqdmlahq_m_n_s32): Remove. (vqdmlahq_m_n_s16): Remove. (vqrdmlahq_m_n_s8): Remove. (vqrdmlahq_m_n_s32): Remove. (vqrdmlahq_m_n_s16): Remove. (vqrdmlashq_m_n_s8): Remove. (vqrdmlashq_m_n_s32): Remove. (vqrdmlashq_m_n_s16): Remove. (__arm_vmlasq_n_u8): Remove. (__arm_vmlaq_n_u8): Remove. (__arm_vqrdmlashq_n_s8): Remove. (__arm_vqdmlashq_n_s8): Remove. (__arm_vqrdmlahq_n_s8): Remove. (__arm_vqdmlahq_n_s8): Remove. (__arm_vmlasq_n_s8): Remove. (__arm_vmlaq_n_s8): Remove. (__arm_vmlasq_n_u16): Remove. (__arm_vmlaq_n_u16): Remove. (__arm_vqrdmlashq_n_s16): Remove. (__arm_vqdmlashq_n_s16): Remove. (__arm_vqrdmlahq_n_s16): Remove. (__arm_vqdmlahq_n_s16): Remove. (__arm_vmlasq_n_s16): Remove. (__arm_vmlaq_n_s16): Remove. (__arm_vmlasq_n_u32): Remove. (__arm_vmlaq_n_u32): Remove. (__arm_vqrdmlashq_n_s32): Remove. (__arm_vqdmlashq_n_s32): Remove. (__arm_vqrdmlahq_n_s32): Remove. (__arm_vqdmlahq_n_s32): Remove. (__arm_vmlasq_n_s32): Remove. (__arm_vmlaq_n_s32): Remove. (__arm_vmlaq_m_n_s8): Remove. (__arm_vmlaq_m_n_s32): Remove. (__arm_vmlaq_m_n_s16): Remove. (__arm_vmlaq_m_n_u8): Remove. (__arm_vmlaq_m_n_u32): Remove. (__arm_vmlaq_m_n_u16): Remove. (__arm_vmlasq_m_n_s8): Remove. (__arm_vmlasq_m_n_s32): Remove. (__arm_vmlasq_m_n_s16): Remove. (__arm_vmlasq_m_n_u8): Remove. (__arm_vmlasq_m_n_u32): Remove. (__arm_vmlasq_m_n_u16): Remove. (__arm_vqdmlahq_m_n_s8): Remove. (__arm_vqdmlahq_m_n_s32): Remove. (__arm_vqdmlahq_m_n_s16): Remove. (__arm_vqrdmlahq_m_n_s8): Remove. (__arm_vqrdmlahq_m_n_s32): Remove. (__arm_vqrdmlahq_m_n_s16): Remove. (__arm_vqrdmlashq_m_n_s8): Remove. (__arm_vqrdmlashq_m_n_s32): Remove. (__arm_vqrdmlashq_m_n_s16): Remove. (__arm_vqdmlashq_m_n_s8): Remove. (__arm_vqdmlashq_m_n_s16): Remove. (__arm_vqdmlashq_m_n_s32): Remove. (__arm_vmlasq): Remove. (__arm_vmlaq): Remove. (__arm_vqrdmlashq): Remove. (__arm_vqdmlashq): Remove. (__arm_vqrdmlahq): Remove. (__arm_vqdmlahq): Remove. (__arm_vmlaq_m): Remove. (__arm_vmlasq_m): Remove. (__arm_vqdmlahq_m): Remove. (__arm_vqrdmlahq_m): Remove. (__arm_vqrdmlashq_m): Remove. (__arm_vqdmlashq_m): Remove.
generated by cgit v1.1 at 2025-08-02 21:51:42 +0000