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| author | Christophe Lyon <christophe.lyon@arm.com> | 2023-02-27 19:16:43 +0000 |
|---|---|---|
| committer | Christophe Lyon <christophe.lyon@arm.com> | 2023-05-12 12:40:40 +0200 |
| commit | 3767c7fe356f6e320ffb1806fadf5a3b54c80151 (patch) | |
| tree | 88466ee1275c6cb9bf34b83b9946c50286503b36 /gcc | |
| parent | ae5c1d25e77f474d202d22964b5d458b205f24bf (diff) | |
| download | gcc-3767c7fe356f6e320ffb1806fadf5a3b54c80151.zip gcc-3767c7fe356f6e320ffb1806fadf5a3b54c80151.tar.gz gcc-3767c7fe356f6e320ffb1806fadf5a3b54c80151.tar.bz2 | |
arm: [MVE intrinsics] factorize vsliq
Factorize vsliq builtins so that they use parameterized names.
2022-12-12 Christophe Lyon <christophe.lyon@arm.com>
gcc/
* config/arm/iterators.md (mve_insn>): Add vsli.
* config/arm/mve.md (mve_vsliq_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vsliq_m_n_<supf><mode>): Rename into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/iterators.md | 2 | ||||
| -rw-r--r-- | gcc/config/arm/mve.md | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 3d4a9cf..7e72190 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1181,6 +1181,8 @@ (VSHRNTQ_N_S "vshrnt") (VSHRNTQ_N_U "vshrnt") (VSHRQ_M_N_S "vshr") (VSHRQ_M_N_U "vshr") (VSHRQ_N_S "vshr") (VSHRQ_N_U "vshr") + (VSLIQ_M_N_S "vsli") (VSLIQ_M_N_U "vsli") + (VSLIQ_N_S "vsli") (VSLIQ_N_U "vsli") (VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub") (VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub") (VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub") diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index c6f9c0b..a1c2cad 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -2058,7 +2058,7 @@ ;; ;; [vsliq_n_u, vsliq_n_s]) ;; -(define_insn "mve_vsliq_n_<supf><mode>" +(define_insn "@mve_<mve_insn>q_n_<supf><mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") @@ -2067,7 +2067,7 @@ VSLIQ_N)) ] "TARGET_HAVE_MVE" - "vsli.%#<V_sz_elem>\t%q0, %q2, %3" + "<mve_insn>.%#<V_sz_elem>\t%q0, %q2, %3" [(set_attr "type" "mve_move") ]) @@ -2960,7 +2960,7 @@ ;; ;; [vsliq_m_n_u, vsliq_m_n_s]) ;; -(define_insn "mve_vsliq_m_n_<supf><mode>" +(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>" [ (set (match_operand:MVE_2 0 "s_register_operand" "=w") (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0") @@ -2970,7 +2970,7 @@ VSLIQ_M_N)) ] "TARGET_HAVE_MVE" - "vpst\;vslit.%#<V_sz_elem>\t%q0, %q2, %3" + "vpst\;<mve_insn>t.%#<V_sz_elem>\t%q0, %q2, %3" [(set_attr "type" "mve_move") (set_attr "length""8")]) |