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2013-05-04combine.c (combine_simplify_rtx): If nonzero_bits on op shows all bits zero i...Jakub Jelinek2-0/+16
2013-05-04re PR c++/51927 ([C++0x] Cannot access non-static members in initializer)Paolo Carlini2-0/+19
2013-05-04re PR target/57150 (GCC when targeting power7 spills long double using VSX in...Michael Meissner5-6/+61
2013-05-04gimple-ssa-strength-reduction.c (slsr_process_phi): Disable.Bill Schmidt10-1/+31
2013-05-04coverage.c (coverage_obj_init): Move the construction of gcov constructor toGuozhi Wei2-18/+34
2013-05-04Daily bump.GCC Administrator1-1/+1
2013-05-03Remove "\\" from scan-assembler-timesDominique d'Humieres2-1/+6
2013-05-03gimple-ssa-strength-reduction.c (cand_kind): Add CAND_PHI.Bill Schmidt10-210/+1279
2013-05-03AArch64 test cases for TST instructionIan Bolton3-0/+311
2013-05-03re PR bootstrap/57154 (Bootstrap broken for powerpc64-unknown-linux-gnu)Teresa Johnson2-0/+12
2013-05-03Fix typos in ChangeLog entriesJeff Law2-2/+2
2013-05-03re PR tree-optimization/57411 (ICE: verify_ssa failed: definition in block 4 ...Jeff Law4-1/+33
2013-05-03re PR rtl-optimization/57130 (Incorrect "and --> extract" conversion in combine)Jakub Jelinek4-2/+51
2013-05-03i386.md (isa): Add x64_sse4_noavx and x64_avx members.Uros Bizjak5-65/+45
2013-05-03re PR tree-optimization/57027 (ICE in gimple_assign_rhs_code, at gimple.h:2022)Joern Rennecke2-4/+15
2013-05-03double-int.h (lshift): New overload without precision and arith argument.Richard Biener7-108/+151
2013-05-03[AArch64] Correct simd_fabd comment text.Vidya Praveen2-1/+5
2013-05-03[AArch64] Support scalar FABDVidya Praveen4-0/+58
2013-05-03re PR c++/54318 ([C++11] Bogus "template instantiation depth exceeds maximum"...Paolo Carlini2-0/+29
2013-05-03re PR c++/14283 (Diagnostic for invalid template-id could be improved)Paolo Carlini5-13/+54
2013-05-03Daily bump.GCC Administrator1-1/+1
2013-05-02lra-constraints.c (process_alt_operands): Add checking alt number to choose t...Vladimir Makarov2-1/+8
2013-05-02tree-eh.c (cleanup_empty_eh_merge_phis): Remove rename_virts bitmap and its h...Richard Biener2-28/+8
2013-05-02re PR fortran/57142 (SIZE/SHAPE overflow despite kind=8)Tobias Burnus6-23/+96
2013-05-02re PR middle-end/57140 (Segmentation fault in backtrace_dwarf_add)Richard Biener4-2/+208
2013-05-02re PR rtl-optimization/56732 (ICE in advance_target_bb)Greta Yorsh4-1/+33
2013-05-02re PR middle-end/56988 (ipa-cp incorrectly propagates a field of an aggregate)Martin Jambor6-3/+74
2013-05-02graphds.h (struct graph): Add obstack member.Richard Biener3-20/+17
2013-05-02Follow-on patch to r197595 to complete the replacement of truncating divides ...Teresa Johnson7-38/+40
2013-05-02AArch64 fix for LDR/STR from/to S and D regsIan Bolton2-2/+8
2013-05-02AArch64 Support for BICS in the backendIan Bolton5-0/+297
2013-05-02tree-scalar-evolution.c (scev_info_hasher): Remove.Richard Biener2-82/+111
2013-05-02Move libitm ChangeLog entry to the right ChangeLog file.Jakub Jelinek1-6/+0
2013-05-02re PR rtl-optimization/57131 (Wrong register assignment?)Jakub Jelinek2-0/+24
2013-05-02Daily bump.GCC Administrator1-1/+1
2013-05-01re PR c++/57132 (spurious warning: division by zero [-Wdiv-by-zero] in if (m...Paolo Carlini4-1/+37
2013-05-01re PR target/57091 (ICE: in assign_by_spills, at lra-assigns.c:1268 with -mcm...Vladimir Makarov4-26/+40
2013-05-01[AArch64] Refactor reduc_<su>plus patterns.James Greenhalgh8-254/+303
2013-05-01[AArch64] Rewrite v<max,min><nm><q><v>_<sfu><8, 16, 32, 64> intrinsics using ...James Greenhalgh5-362/+573
2013-05-01[AArch64] Fold max and min reduction builtins to tree.James Greenhalgh2-0/+20
2013-05-01[AArch64] Refactor vector max and min RTL and builtins.James Greenhalgh5-79/+144
2013-05-01[AArch64] Add testcases for FAC, FCM changes.James Greenhalgh3-0/+166
2013-05-01[AArch64] Rewrite vca<ge, gt, le, lt> Neon patterns in C.James Greenhalgh2-176/+111
2013-05-01[AArch64] Add combiner patterns for FAC instructionsJames Greenhalgh3-0/+25
2013-05-01[AArch64 Testsuite] Fix fallout from FCM changes.James Greenhalgh2-18/+112
2013-05-01[AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.James Greenhalgh2-18/+77
2013-05-01[AArch64] Remap neon vcmp functions to C/TREEJames Greenhalgh4-339/+1161
2013-05-01[AArch64] Improve description of <F>CM instructions in RTLJames Greenhalgh6-52/+236
2013-05-01thumb2.md (thumb2_smaxsi3,thumb2_sminsi3): Convert define_insn to define_insn...Greta Yorsh2-63/+339
2013-05-01re PR c++/57092 (Using decltype of function pointer type to define a data mem...Paolo Carlini4-2/+25