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author | Ian Bolton <ian.bolton@arm.com> | 2013-05-02 12:52:22 +0000 |
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committer | Ian Bolton <ibolton@gcc.gnu.org> | 2013-05-02 12:52:22 +0000 |
commit | add3c9653f4afdd353a546fa43fad17b3e2eda0a (patch) | |
tree | 6e2fdc073b06185251b5ec30312fd8598589fd6e /gcc | |
parent | fdd43ac4f7880ceb96b0bb3884ae800ad393deba (diff) | |
download | gcc-add3c9653f4afdd353a546fa43fad17b3e2eda0a.zip gcc-add3c9653f4afdd353a546fa43fad17b3e2eda0a.tar.gz gcc-add3c9653f4afdd353a546fa43fad17b3e2eda0a.tar.bz2 |
AArch64 Support for BICS in the backend
From-SVN: r198526
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/ChangeLog | 8 | ||||
-rw-r--r-- | gcc/config/aarch64/aarch64.md | 66 | ||||
-rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/bics_1.c | 107 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/aarch64/bics_2.c | 111 |
5 files changed, 297 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2acb274..f1692c6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2013-05-02 Ian Bolton <ian.bolton@arm.com> + + * config/aarch64/aarch64.md (*and_one_cmpl<mode>3_compare0): + New pattern. + (*and_one_cmplsi3_compare0_uxtw): Likewise. + (*and_one_cmpl_<SHIFT:optab><mode>3_compare0): Likewise. + (*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw): Likewise. + 2013-05-02 Richard Biener <rguenther@suse.de> * tree-scalar-evolution.c (scev_info_hasher): Remove. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 96be7a10..50acdaaf 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2746,6 +2746,35 @@ [(set_attr "v8type" "logic") (set_attr "mode" "<MODE>")]) +(define_insn "*and_one_cmpl<mode>3_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (not:GPI + (match_operand:GPI 1 "register_operand" "r")) + (match_operand:GPI 2 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (and:GPI (not:GPI (match_dup 1)) (match_dup 2)))] + "" + "bics\\t%<w>0, %<w>2, %<w>1" + [(set_attr "v8type" "logics") + (set_attr "mode" "<MODE>")]) + +;; zero_extend version of above +(define_insn "*and_one_cmplsi3_compare0_uxtw" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:SI (not:SI + (match_operand:SI 1 "register_operand" "r")) + (match_operand:SI 2 "register_operand" "r")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (and:SI (not:SI (match_dup 1)) (match_dup 2))))] + "" + "bics\\t%w0, %w2, %w1" + [(set_attr "v8type" "logics") + (set_attr "mode" "SI")]) + (define_insn "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3" [(set (match_operand:GPI 0 "register_operand" "=r") (LOGICAL:GPI (not:GPI @@ -2758,6 +2787,43 @@ [(set_attr "v8type" "logic_shift") (set_attr "mode" "<MODE>")]) +(define_insn "*and_one_cmpl_<SHIFT:optab><mode>3_compare0" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:GPI (not:GPI + (SHIFT:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n"))) + (match_operand:GPI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:GPI 0 "register_operand" "=r") + (and:GPI (not:GPI + (SHIFT:GPI + (match_dup 1) (match_dup 2))) (match_dup 3)))] + "" + "bics\\t%<w>0, %<w>3, %<w>1, <SHIFT:shift> %2" + [(set_attr "v8type" "logics_shift") + (set_attr "mode" "<MODE>")]) + +;; zero_extend version of above +(define_insn "*and_one_cmpl_<SHIFT:optab>si3_compare0_uxtw" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ + (and:SI (not:SI + (SHIFT:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_si" "n"))) + (match_operand:SI 3 "register_operand" "r")) + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI (and:SI + (not:SI + (SHIFT:SI (match_dup 1) (match_dup 2))) (match_dup 3))))] + "" + "bics\\t%w0, %w3, %w1, <SHIFT:shift> %2" + [(set_attr "v8type" "logics_shift") + (set_attr "mode" "SI")]) + (define_insn "clz<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (clz:GPI (match_operand:GPI 1 "register_operand" "r")))] diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index a083699..4c7a5b3 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2013-05-02 Ian Bolton <ian.bolton@arm.com> + + * gcc.target/aarch64/bics_1.c: New test. + * gcc.target/aarch64/bics_2.c: Likewise. + 2013-05-02 Jakub Jelinek <jakub@redhat.com> PR rtl-optimization/57131 diff --git a/gcc/testsuite/gcc.target/aarch64/bics_1.c b/gcc/testsuite/gcc.target/aarch64/bics_1.c new file mode 100644 index 0000000..d62ea9a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bics_1.c @@ -0,0 +1,107 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); + +int +bics_si_test1 (int a, int b, int c) +{ + int d = a & ~b; + + /* { dg-final { scan-assembler-times "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +bics_si_test2 (int a, int b, int c) +{ + int d = a & ~(b << 3); + + /* { dg-final { scan-assembler "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +typedef long long s64; + +s64 +bics_di_test1 (s64 a, s64 b, s64 c) +{ + s64 d = a & ~b; + + /* { dg-final { scan-assembler-times "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +s64 +bics_di_test2 (s64 a, s64 b, s64 c) +{ + s64 d = a & ~(b << 3); + + /* { dg-final { scan-assembler "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + if (d == 0) + return a + c; + else + return b + d + c; +} + +int +main () +{ + int x; + s64 y; + + x = bics_si_test1 (29, ~4, 5); + if (x != ((29 & 4) + ~4 + 5)) + abort (); + + x = bics_si_test1 (5, ~2, 20); + if (x != 25) + abort (); + + x = bics_si_test2 (35, ~4, 5); + if (x != ((35 & ~(~4 << 3)) + ~4 + 5)) + abort (); + + x = bics_si_test2 (96, ~2, 20); + if (x != 116) + abort (); + + y = bics_di_test1 (0x130000029ll, + ~0x320000004ll, + 0x505050505ll); + + if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll)) + abort (); + + y = bics_di_test1 (0x5000500050005ll, + ~0x2111211121112ll, + 0x0000000002020ll); + if (y != 0x5000500052025ll) + abort (); + + y = bics_di_test2 (0x130000029ll, + ~0x064000008ll, + 0x505050505ll); + if (y != ((0x130000029ll & ~(~0x064000008ll << 3)) + + ~0x064000008ll + 0x505050505ll)) + abort (); + + y = bics_di_test2 (0x130002900ll, + ~0x088000008ll, + 0x505050505ll); + if (y != (0x130002900ll + 0x505050505ll)) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/bics_2.c b/gcc/testsuite/gcc.target/aarch64/bics_2.c new file mode 100644 index 0000000..e33c748 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/bics_2.c @@ -0,0 +1,111 @@ +/* { dg-do run } */ +/* { dg-options "-O2 --save-temps -fno-inline" } */ + +extern void abort (void); + +int +bics_si_test1 (int a, int b, int c) +{ + int d = a & ~b; + + /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" } } */ + /* { dg-final { scan-assembler-times "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+" 2 } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int +bics_si_test2 (int a, int b, int c) +{ + int d = a & ~(b << 3); + + /* { dg-final { scan-assembler-not "bics\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + /* { dg-final { scan-assembler "bic\tw\[0-9\]+, w\[0-9\]+, w\[0-9\]+, lsl 3" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +typedef long long s64; + +s64 +bics_di_test1 (s64 a, s64 b, s64 c) +{ + s64 d = a & ~b; + + /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" } } */ + /* { dg-final { scan-assembler-times "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+" 2 } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +s64 +bics_di_test2 (s64 a, s64 b, s64 c) +{ + s64 d = a & ~(b << 3); + + /* { dg-final { scan-assembler-not "bics\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + /* { dg-final { scan-assembler "bic\tx\[0-9\]+, x\[0-9\]+, x\[0-9\]+, lsl 3" } } */ + if (d <= 0) + return a + c; + else + return b + d + c; +} + +int +main () +{ + int x; + s64 y; + + x = bics_si_test1 (29, ~4, 5); + if (x != ((29 & 4) + ~4 + 5)) + abort (); + + x = bics_si_test1 (5, ~2, 20); + if (x != 25) + abort (); + + x = bics_si_test2 (35, ~4, 5); + if (x != ((35 & ~(~4 << 3)) + ~4 + 5)) + abort (); + + x = bics_si_test2 (96, ~2, 20); + if (x != 116) + abort (); + + y = bics_di_test1 (0x130000029ll, + ~0x320000004ll, + 0x505050505ll); + + if (y != ((0x130000029ll & 0x320000004ll) + ~0x320000004ll + 0x505050505ll)) + abort (); + + y = bics_di_test1 (0x5000500050005ll, + ~0x2111211121112ll, + 0x0000000002020ll); + if (y != 0x5000500052025ll) + abort (); + + y = bics_di_test2 (0x130000029ll, + ~0x064000008ll, + 0x505050505ll); + if (y != ((0x130000029ll & ~(~0x064000008ll << 3)) + + ~0x064000008ll + 0x505050505ll)) + abort (); + + y = bics_di_test2 (0x130002900ll, + ~0x088000008ll, + 0x505050505ll); + if (y != (0x130002900ll + 0x505050505ll)) + abort (); + + return 0; +} + +/* { dg-final { cleanup-saved-temps } } */ |