riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2024-09-05	[PATCH 1/2 v2] RISC-V: Additional large constant synthesis improvements	Raphael Moreira Zinsly	4	-1/+81
2024-09-06	Match: Add int type fits check for form 2 of .SAT_SUB imm operand	Pan Li	5	-0/+104
2024-09-06	Match: Add int type fits check for form 1 of .SAT_SUB imm operand	Pan Li	5	-0/+104
2024-09-04	[PATCH] RISC-V: Make the setCC/REE tests robust to instruction selection	Palmer Dabbelt	4	-4/+4
2024-09-04	[PATCH 1/3] RISC-V: Improve codegen for negative repeating large constants	Raphael Moreira Zinsly	1	-0/+28
2024-09-04	[RISC-V] Fix scan test output after recent path-splitting changes	Jeff Law	41	-41/+41
2024-09-04	RISC-V: Allow IMM operand for unsigned scalar .SAT_ADD	Pan Li	6	-6/+6
2024-09-03	[PR target/115921] Improve reassociation for rv64	Jeff Law	1	-0/+13
2024-09-03	RISC-V: Support form 1 of integer scalar .SAT_ADD	Pan Li	11	-0/+315
2024-09-01	[PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.	Xianmiao Qu	1	-0/+13
2024-09-02	RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 3	Pan Li	6	-0/+102
2024-09-02	RISC-V: Add testcases for unsigned scalar quad and oct .SAT_TRUNC form 2	Pan Li	6	-0/+102
2024-09-02	RISC-V: Add testcases for form 4 of unsigned vector .SAT_ADD IMM	Pan Li	9	-0/+188
2024-09-02	RISC-V: Add testcases for form 3 of unsigned vector .SAT_ADD IMM	Pan Li	8	-0/+168
2024-09-02	RISC-V: Refactor gen zero_extend rtx for SAT_* when expand SImode in RV64	Pan Li	24	-0/+72
2024-08-29	RISC-V: Fix subreg of VLS modes larger than a vector [PR116086].	Robin Dapp	3	-0/+100
2024-08-28	Test: Move pr116278 run test to dg/torture [NFC]	Pan Li	2	-4/+4
2024-08-28	Vect: Reconcile the const_int operand type of unsigned .SAT_ADD	Pan Li	16	-0/+155
2024-08-28	RISC-V: Add missing mode_idx for vrol and vror	Kito Cheng	1	-0/+13
2024-08-28	RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 4	Pan Li	15	-0/+421
2024-08-28	RISC-V: Add testcases for unsigned scalar .SAT_SUB IMM form 3	Pan Li	15	-0/+432
2024-08-27	RISC-V: Support IMM for operand 1 of ussub pattern	Pan Li	15	-0/+421
2024-08-26	Match: Add int type fits check for .SAT_ADD imm operand	Pan Li	57	-8/+442
2024-08-26	RISC-V: Support IMM for operand 0 of ussub pattern	Pan Li	15	-0/+431
2024-08-26	RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 4	Pan Li	13	-0/+236
2024-08-26	RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 4	Pan Li	13	-0/+218
2024-08-25	RISC-V: Fix double mode under RV32 not utilize vf	demin.han	32	-67/+67
2024-08-25	[PATCH] Re-add calling emit_clobber in lower-subreg.cc's resolve_simple_move.	Xianmiao Qu	1	-0/+16
2024-08-25	Disable late-combine in another RISC-V test	Jeff Law	1	-1/+1
2024-08-25	[committed] Fix assembly scan for RISC-V VLS tests	Jeff Law	7	-7/+7
2024-08-25	Turn off late-combine for a few risc-v specific tests	Jeff Law	4	-4/+4
2024-08-23	optabs-query: Use opt_machine_mode for smallest_int_mode_for_size [PR115495].	Robin Dapp	1	-0/+9
2024-08-23	RISC-V: Expand vec abs without masking.	Robin Dapp	11	-23/+39
2024-08-22	RISC-V: Fix vector cfi notes for stack-clash protection	Raphael Moreira Zinsly	1	-1/+2
2024-08-22	RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 3	Pan Li	13	-0/+236
2024-08-22	RISC-V: Add testcases for unsigned vector .SAT_TRUNC form 2	Pan Li	13	-0/+236
2024-08-21	RISC-V: Fix one typo in .SAT_TRUNC test func name [NFC]	Pan Li	25	-63/+63
2024-08-18	RISC-V: Implement the quad and oct .SAT_TRUNC for scalar	Pan Li	9	-2/+155
2024-08-18	RISC-V: Make sure high bits of usadd operands is clean for non-Xmode [PR116278]	Pan Li	12	-10/+90
2024-08-18	RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3	Pan Li	7	-0/+116
2024-08-18	RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2	Pan Li	7	-0/+116
2024-08-17	RISC-V: Fix ICE for vector single-width integer multiply-add intrinsics	Jin Ma	2	-0/+52
2024-08-17	[RISC-V][PR target/116282] Stabilize pattern conditions	Jeff Law	1	-0/+16
2024-08-17	RISC-V: Bugfix for RVV rounding intrinsic ICE in function checker	Jin Ma	1	-0/+13
2024-08-17	RISC-V: Bugfix incorrect operand for vwsll auto-vect	Pan Li	2	-0/+24
2024-08-17	RISC-V: Add auto-vect pattern for vector rotate shift	Feng Wang	3	-0/+126
2024-08-17	RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]	曾治金	1	-0/+32
2024-08-15	RISC-V: use fclass insns to implement isfinite,isnormal and isinf builtins	Vineet Gupta	1	-0/+38
2024-08-14	Restrict pr116202-run-1.c test to riscv_v target	Mark Wielaard	1	-1/+1
2024-08-12	RISC-V: Fix missing abi arg in test	Edwin Lu	1	-1/+1