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2022-10-03gcc/config/t-i386: add build dependencies on i386-builtin-types.incSergei Trofimovich1-0/+5
2022-10-03vect: while_ult for integer masksAndrew Stubbs1-1/+7
2022-10-03arm: Add missing early clobber to MVE vrev64q_m patternsChristophe Lyon1-2/+2
2022-10-02Define GCC_DRIVER_HOST_INITIALIZATION for VxWorks targetsMarc Poulhiès3-0/+107
2022-10-02Refine guard for vxworks crtstuff specOlivier Hainque1-5/+4
2022-10-01or1k: Only define TARGET_HAVE_TLS when HAVE_AS_TLSStafford Horne1-0/+2
2022-10-01Improve Z flag handling on H8Jeff Law2-0/+269
2022-09-30RISC-V: Support -fexcess-precision=16Palmer Dabbelt1-0/+1
2022-09-30arm, csky: Fix C++ ICEs with _Float16 and __fp16 [PR107080]Jakub Jelinek2-5/+7
2022-09-30aarch64: Fix C++ ICEs with _Float16 and __fp16 [PR107080]Jakub Jelinek1-0/+2
2022-09-30i386, rs6000, ia64, s390: Fix C++ ICEs with _Float64x or _Float128 [PR107080]Jakub Jelinek4-11/+12
2022-09-30RISC-V: Add '-m[no]-csr-check' option in gcc.Jiawei2-0/+11
2022-09-30rs6000: Rework ELFv2 support for -fpatchable-function-entry* [PR99888]Kewen Lin4-2/+48
2022-09-29amdgcn: remove unused variableAndrew Stubbs1-2/+0
2022-09-29Comment about HAVE_INITFINI_ARRAY_SUPPORT in vxworks.hOlivier Hainque1-0/+5
2022-09-29Add an mcmodel=large multilib for aarch64-vxworksOlivier Hainque1-0/+5
2022-09-29Remove TARGET_FLOAT128_ENABLE_TYPE setting for VxWorksOlivier Hainque1-3/+4
2022-09-29Robustify DWARF2_UNWIND_INFO handling in vx-common.hOlivier Hainque1-2/+5
2022-09-29aarch64: Remove redundant TARGET_* checksRichard Sandiford4-49/+47
2022-09-29aarch64: Tweak handling of -mgeneral-regs-onlyRichard Sandiford6-22/+56
2022-09-29aarch64: Make more use of aarch64_feature_flagsRichard Sandiford6-38/+46
2022-09-29aarch64: Tweak constness of option-related dataRichard Sandiford2-15/+14
2022-09-29aarch64: Simplify feature definitionsRichard Sandiford9-443/+356
2022-09-29aarch64: Reorder an entry in aarch64-option-extensions.defRichard Sandiford1-10/+10
2022-09-29aarch64: Fix transitive closure of featuresRichard Sandiford1-7/+9
2022-09-29aarch64: Remove AARCH64_FL_RCPC8_4 [PR107025]Richard Sandiford2-4/+3
2022-09-29aarch64: Avoid redundancy in aarch64-cores.defRichard Sandiford3-67/+67
2022-09-29aarch64: Small config.gcc cleanupsRichard Sandiford1-1/+1
2022-09-29aarch64: Add "V" to aarch64-arches.def namesRichard Sandiford4-81/+82
2022-09-29aarch64: Rename AARCH64_FL_FOR_ARCH macrosRichard Sandiford4-108/+108
2022-09-29aarch64: Rename AARCH64_FL architecture-level macrosRichard Sandiford1-36/+36
2022-09-29aarch64: Rename AARCH64_ISA architecture-level macrosRichard Sandiford2-16/+16
2022-09-28i386: Mark XMM4-XMM6 as clobbered by encodekey128/encodekey256H.J. Lu2-12/+12
2022-09-29RISC-V: Add ABI-defined RVV types.Ju-Zhe Zhong8-1/+828
2022-09-28arm: Define __ARM_FEATURE_AES and __ARM_FEATURE_SHA2 when march +crypto is se...Andrea Corallo1-0/+2
2022-09-28LoongArch: Use UNSPEC for fmin/fmax RTL pattern [PR105414]Xi Ruoyao1-4/+8
2022-09-28LoongArch: Fixed a typo in the comment information of the function loongarch_...Lulu Cheng1-1/+1
2022-09-27c++: Implement P1467R9 - Extended floating-point types and standard names com...Jakub Jelinek7-19/+60
2022-09-26nvptx: Allow '--with-arch' to override the default '-misa'Thomas Schwinge2-5/+76
2022-09-26nvptx: Introduce dummy multilib option for default '-misa=sm_30'Thomas Schwinge1-1/+19
2022-09-26nvptx: Make default '-misa=sm_30' explicitThomas Schwinge3-1/+9
2022-09-26nvptx: forward '-v' command-line option to assemblerThomas Schwinge1-0/+4
2022-09-26s390: fix wrong refactoringMartin Liska1-8/+7
2022-09-26aarch64: Add -march support for Armv9.1-A, Armv9.2-A, Armv9.3-AKyrylo Tkachov2-0/+21
2022-09-26rs6000: Fix the condition with frame_pointer_needed_indeed [PR96072]Kewen Lin1-1/+1
2022-09-25rs6000: Fix condition of define_expand vec_shr_<mode> [PR100645]Kewen Lin1-1/+1
2022-09-26Support 2-instruction vector shuffle for V4SI/V4SF in ix86_expand_vec_perm_co...liuhongt1-0/+116
2022-09-23RISC-V: make USE_LOAD_ADDRESS_MACRO easier to understandVineet Gupta1-6/+7
2022-09-23RISC-V: Add RVV machine modes.zhongjuzhe1-0/+141
2022-09-23RISC-V: Support poly move manipulation and selftests.zhongjuzhe5-5/+550
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