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2024-06-20i386: Fix some ISA bit test in option_overrideHongyu Wang1-5/+9
2024-06-19[PATCH v2] RISC-V: Remove float vector eqne patterndemin.han2-92/+2
2024-06-19i386: Zhaoxin shijidadao enablementmayshao7-8/+141
2024-06-19xtensa: Eliminate double MEMW insertions for volatile memoryTakayuki 'January June' Suwa1-1/+11
2024-06-19arm: Add support for MVE Tail-Predicated Low Overhead LoopsAndre Vieira8-55/+1424
2024-06-19xtensa: constantsynth: Reforge to fix some non-fatal issuesTakayuki 'January June' Suwa3-30/+103
2024-06-18RISC-V: Move mode assertion out of conditional branch in emit_insnEdwin Lu1-6/+19
2024-06-18RISC-V: Fix vwsll combine on rv32 targetsEdwin Lu1-4/+2
2024-06-18aarch64: Add comment about thunderxt81/t83 being aliasesAndrew Pinski1-0/+1
2024-06-18aarch64: make thunderxt88p1 an alias of thunderxt88Andrew Pinski2-4/+3
2024-06-18[to-be-committed,RISC-V] Improve bset generation when bit position is limitedJeff Law1-0/+36
2024-06-18aarch64: Add some uses of force_highpart_subregRichard Sandiford1-13/+4
2024-06-18aarch64: Add some uses of force_lowpart_subregRichard Sandiford4-17/+12
2024-06-18aarch64: Use force_subreg in more placesRichard Sandiford4-12/+10
2024-06-18rs6000: Shrink rs6000_init_generated_builtins size [PR115324]Jakub Jelinek2-12/+29
2024-06-18i386: Handle target of __builtin_ia32_cmp[p|s][s|d] from avx into sse/sse2/avxHu, Lin17-78/+104
2024-06-17[to-be-committed,RISC-V] Handle zero_extract destination for single bit inser...Jeff Law1-0/+17
2024-06-17rs6000: Compute rop_hash_save_offset for non-Altivec compiles [PR115389]Peter Bergner1-5/+4
2024-06-17[to-be-committed,RISC-V] Improve variable bit set for rv64Jeff Law1-0/+12
2024-06-17i386: Refine all cvtt* instructions with UNSPEC instead of FIX/UNSIGNED_FIX.Hu, Lin12-64/+399
2024-06-17x86: Emit cvtne2ps2bf16 for odd increasing perm in __builtin_shufflevectorLevy Hsu3-2/+48
2024-06-17s390: Extend two element float vectorStefan Schulze Frielinghaus1-0/+28
2024-06-17s390: Extend two/four element integer vectorsStefan Schulze Frielinghaus2-5/+28
2024-06-16aarch64: Fix reg_is_wrapped_separately array size [PR100211]Andrew Pinski1-1/+1
2024-06-16[to-be-committed] [RISC-V] Improve (1 << N) | C for rv64Jeff Law1-0/+15
2024-06-15[committed] Fix minor SH scan-asm failure after recent IOR->ADD changesJeff Law1-0/+19
2024-06-15riscv: Allocate enough space to strcpy() stringChristoph Müllner1-3/+3
2024-06-14RISC-V: Bugfix vec_extract v mode iterator restriction mismatchPan Li1-1/+3
2024-06-14Adjust ix86_rtx_costs for pternlog_operand_p.liuhongt1-1/+38
2024-06-14Remove one_if_conv for latest Intel processors.liuhongt1-2/+2
2024-06-14i386: More use of m{32,64}bcst addressing modes with ternlog.Roger Sayle1-0/+63
2024-06-13RISC-V: Add support for subword atomic loads/storesPatrick O'Neill3-26/+26
2024-06-13[APX CCMP] Add targetm.have_ccmp hook [PR115370]Hongyu Wang1-0/+9
2024-06-13aarch64: Fix invalid nested subregs [PR115464]Richard Sandiford1-1/+1
2024-06-13RISC-V: Bugfix vec_extract vls mode iterator restriction mismatchPan Li2-1/+5
2024-06-13[APX CCMP] Use ctestcc when comparing to const 0Hongyu Wang1-4/+7
2024-06-13Fix ICE due to REGNO of a SUBREG.liuhongt1-1/+1
2024-06-13MIPS: Use FPU-enabled tune for mips32/mips64/mips64r2/mips64r3/mips64r5YunQiang Su1-5/+5
2024-06-13MIPS: Use signaling fcmp instructions for LT/LE/LTGTYunQiang Su5-11/+61
2024-06-13[APX ZU] Support APX zero-upperLingling Kong4-3/+29
2024-06-12pretty_printer: unbreak build on aarch64 [PR115465]David Malcolm1-1/+1
2024-06-12aarch64: Use bitreverse rtl code instead of unspec [PR115176]Andrew Pinski6-19/+10
2024-06-12LoongArch: Use bstrins for "value & (-1u << const)"Xi Ruoyao3-0/+26
2024-06-12LoongArch: Fix mode size comparision in loongarch_expand_conditional_moveXi Ruoyao1-1/+1
2024-06-12arm: Zero/Sign extends for CMSE security on Armv8-M.baseline [PR115253]Torbjörn SVENSSON1-8/+68
2024-06-11c: Add -std=c2y, -std=gnu2y, -Wc23-c2y-compat, C2Y _Generic with type operandJoseph Myers1-0/+1
2024-06-11RISC-V: Add Zalrsc amo-op patternsPatrick O'Neill1-5/+119
2024-06-11RISC-V: Add basic Zaamo and Zalrsc supportEdwin Lu3-16/+21
2024-06-11i386: Use CMOV in .SAT_{ADD|SUB} expansion for TARGET_CMOV [PR112600]Uros Bizjak1-9/+53
2024-06-11aarch64: Add vector floating point trunc patternPengxuan Zheng2-3/+10
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