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2024-10-03Aarch64: Define WIDEST_HARDWARE_FP_SIZEEric Botcazou1-0/+2
2024-10-03aarch64: Fix early ra for -fno-delete-dead-exceptions [PR116927]Andrew Pinski1-0/+6
2024-10-02arm: Prevent ICE when doloop dec_set is not PLUS exprAndre Vieira1-17/+32
2024-10-01AVR: avr.cc - Drop a superfluous sub-condition in avr_out_compare.Georg-Johann Lay1-1/+0
2024-10-01AVR: avr-passes.cc - Fix a build warning.Georg-Johann Lay1-1/+2
2024-10-01aarch64: Introduce new unspecs for smax/sminSaurabh Jha2-61/+45
2024-10-01aarch64: Add fp8 scalar typesClaudio Bantaloukas4-2/+79
2024-09-30c6x: Adjust dot-product backend patternsVictor Do Nascimento1-1/+1
2024-09-30rs6000: Adjust altivec dot-product backend patternsVictor Do Nascimento1-2/+2
2024-09-30mips: Adjust dot-product backend patternsVictor Do Nascimento1-1/+1
2024-09-30arc: Adjust dot-product backend patternsVictor Do Nascimento1-4/+4
2024-09-30i386: Fix dot_prod backend patterns for mmx and sse targetsVictor Do Nascimento2-34/+37
2024-09-30arm: Fix arm backend-use of (u|s|us)dot_prod patternsVictor Do Nascimento2-4/+11
2024-09-30aarch64: Fix aarch64 backend-use of (u|s|us)dot_prod patternsVictor Do Nascimento8-17/+51
2024-09-30RISC-V: Implement scalar SAT_SUB for signed integerPan Li3-0/+81
2024-09-27i386: Modernize AMD processor typesUros Bizjak1-6/+26
2024-09-26x86: Extend AVX512 Vectorization for Popcount in Various ModesLevy Hsu1-0/+24
2024-09-26Define VECTOR_STORE_FLAG_VALUEliuhongt1-1/+4
2024-09-25i386: Add GENERIC and GIMPLE folders of __builtin_ia32_{min,max}* [PR116738]Jakub Jelinek1-0/+195
2024-09-26x86: Don't use address override with segment regsiterH.J. Lu1-1/+8
2024-09-25i386: Update the comment for mapxf optionLingling Kong1-1/+1
2024-09-24i386: Fix comment typoJakub Jelinek1-1/+1
2024-09-24[PATCH] RISC-V: Fix FIXED_REGISTERS comment missing return address registerYixuan Chen1-1/+1
2024-09-24RISC-V: Add more vector-vector extract cases.Robin Dapp2-0/+212
2024-09-24build: enable C++11 narrowing warningsJason Merrill2-6/+6
2024-09-24nvptx: Partial support for aliases to aliases.Prathamesh Kulkarni1-3/+21
2024-09-23aarch64: Add codegen support for AdvSIMD faminmaxSaurabh Jha2-0/+12
2024-09-23aarch64: Add AdvSIMD faminmax intrinsicsSaurabh Jha6-0/+167
2024-09-23dwarf2: add hooks for architecture-specific CFIsMatthieu Longo2-0/+68
2024-09-23Rename REG_CFA_TOGGLE_RA_MANGLE to REG_CFA_NEGATE_RA_STATEMatthieu Longo1-2/+2
2024-09-23arc: Remove mlra option [PR113954]Claudiu Zissulescu3-15/+3
2024-09-23gcn/mkoffload.cc: Re-add fprintf for #include of stdlib.h/stdbool.hTobias Burnus1-0/+6
2024-09-22aarch64: Take into account when VF is higher than known scalar itersTamar Christina1-0/+13
2024-09-20AArch64: Define VECTOR_STORE_FLAG_VALUE.Tamar Christina1-0/+10
2024-09-20Darwin: Allow for as versions that need '-' for std in.Iain Sandoe1-0/+2
2024-09-20s390: Remove -m{,no-}lra optionStefan Schulze Frielinghaus3-16/+0
2024-09-20i386: Fix up _mm_min_ss etc. handling of zeros and NaNs [PR116738]Jakub Jelinek2-1/+43
2024-09-19SVE intrinsics: Fold svmul with all-zero operands to zero vectorJennifer Schmitz1-1/+16
2024-09-19aarch64: Define l1_cache_line_size for -mcpu=neoverse-v2Kyrylo Tkachov1-1/+14
2024-09-19i386: Add ssemov2, sseicvt2 for some load instructions that use memory on ope...Hu, Lin12-6/+11
2024-09-18hppa: Add peephole2 optimizations for REG+D loads and storesJohn David Anglin2-0/+103
2024-09-18[PATCH v3] RISC-V: Fixed incorrect semantic description in DF to DI pattern i...Jin Ma1-7/+9
2024-09-18[PATCH 1/2] RISC-V: Fix the outer_code when calculating the cost of SET expre...Xianmiao Qu1-1/+1
2024-09-18[PATCH] RISC-V: Fix th.extu operands exceeding range on rv32.Xianmiao Qu1-1/+3
2024-09-18[PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vxBohan Lei1-4/+4
2024-09-18reload1.cc: rtl-optimization/116326 - Use RELOAD_ELIMINABLE_REGS.Georg-Johann Lay1-1/+8
2024-09-18RISC-V: Implement SAT_ADD for signed integer vectorPan Li3-0/+21
2024-09-17PR 89213: Add better support for shifting vectors with 64-bit elementsMichael Meissner2-0/+114
2024-09-17SVE intrinsics: Fold svdiv with all-zero operands to zero vectorJennifer Schmitz1-9/+20
2024-09-16aarch64: Improve vector constant generation using SVE INDEX instruction [PR11...Pengxuan Zheng1-1/+12
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