aboutsummaryrefslogtreecommitdiff
path: root/gcc/config
AgeCommit message (Expand)AuthorFilesLines
2021-10-12Fix PR target/102588Eric Botcazou1-0/+3
2021-10-12Support reduc_{plus,smax,smin,umax,umin}_scal_v4qi.liuhongt2-0/+50
2021-10-11rs6000: Support more SSE4 "cmp", "mul", "pack" intrinsicsPaul A. Clarke2-0/+81
2021-10-11rs6000: Support SSE4.1 "cvt" intrinsicsPaul A. Clarke1-0/+138
2021-10-11rs6000: Simplify some SSE4.1 "test" intrinsicsPaul A. Clarke1-26/+4
2021-10-11rs6000: Support SSE4.1 "min" and "max" intrinsicsPaul A. Clarke1-0/+56
2021-10-11IBM Z: Provide rawmemchr{qi,hi,si} expanderStefan Schulze Frielinghaus5-26/+104
2021-10-09Refine movhfcc.liuhongt3-6/+48
2021-10-08Come up with OPTION_SET_P macro.Martin Liska36-130/+145
2021-10-08Simplify (_Float16) ceil ((double) x) to .CEIL (x) when available.liuhongt1-8/+12
2021-10-08Support reduc_{plus,smax,smin,umax,min}_scal_v4hi.liuhongt2-0/+41
2021-10-07amdgcn: Fix assembler version incompatibilityAndrew Stubbs1-4/+12
2021-10-07amdgcn: Implement -msram-ecc=anyAndrew Stubbs3-38/+96
2021-10-07amdgcn: Support LLVM 13 assembler syntaxAndrew Stubbs2-18/+89
2021-10-05Fix redefinition warningJan-Benedict Glaw1-0/+1
2021-10-04Remove dead code in config/rs6000/vxworks.hEric Botcazou1-4/+0
2021-10-01aarch64: enable cortex-x2 CPUPrzemyslaw Wirkus2-1/+3
2021-10-01aarch64: enable cortex-a710 CPUPrzemyslaw Wirkus2-1/+3
2021-10-01aarch64: enable cortex-a510 CPUPrzemyslaw Wirkus2-1/+6
2021-10-01Default to dwarf version 4 on hppa64-hpuxJohn David Anglin1-0/+10
2021-10-01aarch64: fix AARCH64_FL_V9 flag valuePrzemyslaw Wirkus1-2/+3
2021-10-01aarch64: add armv9-a to -marchPrzemyslaw Wirkus2-0/+6
2021-10-01Fix PR c++/64697 at -O1 or aboveEric Botcazou1-13/+8
2021-09-30arm: Enable Cortex-R52+ CPUPrzemyslaw Wirkus3-1/+14
2021-09-30i386: Eliminate sign extension after logic operation [PR89954]Uros Bizjak1-0/+34
2021-09-29aarch64: Fix type qualifiers for qtbl1 and qtbx1 Neon builtinsJonathan Wright3-21/+27
2021-09-29aarch64: Improve size heuristic for cpymem expansionKyrylo Tkachov1-11/+25
2021-09-29aarch64: Improve size optimisation heuristic for setmem expansionKyrylo Tkachov1-13/+18
2021-09-28RISC-V: Pattern name fix mul*3_highpart -> smul*3_highpart.Geng Qi1-5/+5
2021-09-28Darwin, D : Add .d suffix to the list for invoking dsymutil.Iain Sandoe1-1/+1
2021-09-28Darwin, PPC : Fix R13 for PPC64.Iain Sandoe1-1/+4
2021-09-28aarch64: Add command-line support for Armv8.7-aKyrylo Tkachov3-0/+13
2021-09-28i386: Don't emit fldpi etc. if -frounding-math [PR102498]Jakub Jelinek1-1/+2
2021-09-28AVX512FP16: Support basic 64/32bit vector type and operation.Hongyu Wang4-15/+59
2021-09-28Support 128/256/512-bit vector plus/smin/smax reduction for _Float16.liuhongt2-2/+11
2021-09-27Revert "Optimize v4sf reduction.".liuhongt1-28/+11
2021-09-25pru: Named address space for R30/R31 I/O accessDimitar Dimitrov7-10/+282
2021-09-24AVX512FP16: Support cond_op for HFmodeHongyu Wang1-56/+56
2021-09-23rs6000: Add psabi diagnostic for C++ zero-width bit field ABI changeBill Schmidt1-6/+58
2021-09-23AVX512FP16: Enable vec_cmpmn/vcondmn expanders for HF modes.Hongyu Wang2-12/+74
2021-09-23AVX512FP16: add truncmn2/extendmn2 expandersHongyu Wang1-7/+68
2021-09-23AVX512FP16: Add float(uns)?mn2 expanderHongyu Wang1-8/+38
2021-09-23AVX512FP16: Add fix(uns)?_truncmn2 for HF scalar and vector modesHongyu Wang2-0/+72
2021-09-23AVX512FP16: Add expander for smin/maxhf3.Hongyu Wang1-0/+11
2021-09-23AVX512FP16: Add expander for fmahf4liuhongt1-5/+6
2021-09-23AVX512FP16: Add expander for rint/nearbyinthf2.liuhongt1-0/+22
2021-09-22AVX512FP16: Add permutation and mask blend intrinsics.dianhong xu2-0/+93
2021-09-22AVX512FP16: Add complex conjugation intrinsic instructions.dianhong xu2-0/+80
2021-09-22AVX512FP16: Add reduce operators(add/mul/min/max).dianhong xu2-0/+203
2021-09-22AVX512FP16: Support load/store/abs intrinsics.dianhong xu2-0/+116
generated by cgit v1.1 at 2024-10-20 17:45:43 +0000