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AgeCommit message (Expand)AuthorFilesLines
2020-07-08rs6000: Add len_load/len_store optab supportKewen Lin1-0/+28
2020-07-07Aarch64: Change costs for TX2 to expose more vectorization opportunitiesAnton Youdkevitch1-9/+9
2020-07-06nvptx: Add support for vadd.add and vsub.add instructions.Roger Sayle1-0/+16
2020-07-06cris: New peephole2 movulsr + test-case.Hans-Peter Nilsson1-4/+41
2020-07-06cris: Correct gcc_assert for atomic_fetch_op patternHans-Peter Nilsson1-1/+5
2020-07-06cris: update recent patterns. Simplify cris_select_cc_mode.Hans-Peter Nilsson3-67/+71
2020-07-06cris.md: Reinstate add/sub with extendHans-Peter Nilsson1-0/+83
2020-07-03[PATCH] nvptx: Add support for popcount and widening multiply instructionsRoger Sayle1-0/+44
2020-07-03amdgcn: Add fold_left_plus vector reductionsAndrew Stubbs1-0/+20
2020-07-03nvptx: Fix ICE in nvptx_vector_alignment on gcc.dg/attr-vector_size.cRoger Sayle1-2/+15
2020-07-02RISC-V: Handle multi-letter extension for multilib-generatorKito Cheng1-8/+22
2020-07-01aarch64: Fix missing BTI instruction in trampolinesOmar Tahir1-22/+8
2020-07-01Fix bootstrap for m68k.Jeff Law1-6/+6
2020-07-01aarch64: Add 64 bit setter getter fpsr fpcrAndrea Corallo3-54/+98
2020-06-30Fix bootstrap failure on PAJeff Law1-4/+4
2020-06-30aarch64: Treat GNU and Advanced SIMD vectors as distinct [PR92789, PR95726]Richard Sandiford2-18/+31
2020-06-30arm: Warn if IRQ handler is not compiled with -mgeneral-regs-only [PR target/...Christophe Lyon1-0/+5
2020-06-29rs6000: Rename isa attribute "fut" to "p10"Segher Boessenkool1-5/+5
2020-06-29amdgcn: Support basic DWARFAndrew Stubbs3-8/+120
2020-06-29sparc: Remove register storage class in sparc.cRainer Orth1-11/+11
2020-06-26Linux/i386: Remove SUBTARGET_FRAME_POINTER_REQUIREDH.J. Lu2-6/+2
2020-06-26rs6000: Add support for __builtin_cpu_is ("power10")Peter Bergner1-0/+1
2020-06-25This patch disables the movsicc pattern in the M32R backend, which is repsons...Nick Clifton1-0/+6
2020-06-25powerpc: Restore bootstrap for Darwin.Iain Sandoe1-1/+1
2020-06-25x96: Remove PTA_CLWB from PTA_ICELAKE_CLIENTH.J. Lu1-3/+3
2020-06-24[PATCH, PR target/94954] Fix wrong codegen for vec_pack_to_short_fp32() builtinWill Schmidt5-1/+49
2020-06-24x86: Remove brand ID check for Intel processorsH.J. Lu1-1/+1
2020-06-24x86: Share _isa_names_table and use cpuinfo.hH.J. Lu2-583/+113
2020-06-24x86: Move cpuinfo.h from libgcc to common/config/i386H.J. Lu1-89/+58
2020-06-24x86: Fold arch_names_table into processor_alias_tableH.J. Lu2-293/+83
2020-06-23arm: PR target/95646: Do not clobber callee saved registers with CMSEAndre Simoes Dias Vieira1-1/+1
2020-06-23handle dumpbase in offloading, adjust testsuiteAlexandre Oliva2-7/+75
2020-06-22rs6000: Rename future to power10Segher Boessenkool20-792/+787
2020-06-22x86: Skip EXT_REX_SSE_REG_P for vzeroupper optimizationH.J. Lu1-1/+3
2020-06-22amdgcn: Pass vector parameters in memoryAndrew Stubbs1-0/+8
2020-06-22RISC-V: Normalize arch string in driver timeKito Cheng1-1/+5
2020-06-22RISC-V: Fix compilation failed for frflags builtin in C++ modeKito Cheng2-2/+5
2020-06-21aix: Add GCC64 configuration and FAT target libraries.David Edelsohn3-21/+123
2020-06-21rs6000: Add MMA built-in function definitions and test cases.Peter Bergner8-24/+1225
2020-06-21rs6000: Add base support and types for defining MMA built-ins.Peter Bergner10-30/+398
2020-06-19amdgcn: Silence compile warningsTobias Burnus1-3/+3
2020-06-18i386: Fix mode of ZERO_EXTRACT RTXes, remove ext_register_operand predicate.Uros Bizjak3-221/+263
2020-06-18rs6000: Fix creation of VEC_COND_EXPRMartin Liska1-6/+9
2020-06-17IBM Z: Prevent mach optimization on doloop patternsAndreas Krebbel1-2/+7
2020-06-17amdgcn: Switch to HSACO v3 binary formatAndrew Stubbs6-288/+116
2020-06-17Optimize V16QI/V32QI/V64QI shift by constant.liuhongt3-1/+102
2020-06-16S/390: Emit vector alignment hints for z13 if AS accepts themStefan Schulze Frielinghaus2-3/+8
2020-06-16[PATCH][GCC] arm: Fix the MVE ACLE vaddq_m polymorphic variants.Srinath Parvathaneni1-24/+24
2020-06-16[PATCH][GCC] arm: Fix MVE scalar shift intrinsics code-gen.Srinath Parvathaneni2-36/+48
2020-06-16RISC-V: Fix ICE on riscv_gpr_save_operation_p [PR95683]Kito Cheng1-1/+4
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