riscv-gnu-toolchain/gcc.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-06-24	RISC-V: Refactor the integer ternary autovec pattern	Juzhe-Zhong	1	-26/+28
2023-06-24	RISC-V: Support RVV floating-point auto-vectorization	Juzhe-Zhong	4	-14/+224
2023-06-23	Fix power10 fusion bug with prefixed loads, PR target/105325	Michael Meissner	4	-36/+46
2023-06-22	Change fma_reassoc_width tuning for ampere1	Di Zhao OS	1	-1/+1
2023-06-22	i386: Convert ptestz of pandn into ptestc.	Roger Sayle	3	-8/+91
2023-06-21	c-family: implement -ffp-contract=on	Alexander Monakov	1	-1/+1
2023-06-21	aarch64: Avoid same input and output Z register for gather loads	Kyrylo Tkachov	2	-71/+135
2023-06-21	aarch64: Convert SVE gather patterns to compact syntax	Kyrylo Tkachov	2	-191/+211
2023-06-21	Revert "aarch64: Convert SVE gather patterns to compact syntax"	Kyrylo Tkachov	2	-275/+191
2023-06-21	aarch64: Convert SVE gather patterns to compact syntax	Kyrylo Tkachov	2	-191/+275
2023-06-21	[i386] Reject too large vectors for partial vector vectorization	Richard Biener	1	-0/+26
2023-06-21	x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F	Jan Beulich	2	-11/+27
2023-06-20	aarch64: Robustify stack tie handling	Richard Sandiford	2	-7/+18
2023-06-20	rs6000: Add builtins for IEEE 128-bit floating point values	Carl Love	5	-21/+62
2023-06-20	RISC-V: Set the natural size of constant vector mask modes to one RVV data ve...	Li Xu	1	-0/+5
2023-06-20	RISC-V: Optimize codegen of VLA SLP	Juzhe-Zhong	1	-45/+36
2023-06-20	RISC-V: Fix compiler warning of riscv_arg_has_vector	Lehua Ding	1	-2/+4
2023-06-20	aarch64: Optimise ADDP with same source operands	Kyrylo Tkachov	1	-0/+30
2023-06-20	AArch64: remove test comment from *mov<mode>_aarch64	Tamar Christina	1	-1/+1
2023-06-20	x86: correct and improve "*vec_dupv2di"	Jan Beulich	1	-6/+22
2023-06-20	RISC-V: Add tuple vector mode psABI checking and simplify code	Lehua Ding	1	-36/+17
2023-06-19	RISC-V: Save and restore FCSR in interrupt functions to avoid program errors.	Jin Ma	2	-3/+58
2023-06-19	AArch64: convert some patterns to compact MD syntax	Tamar Christina	1	-83/+78
2023-06-19	RISC-V: Fix VWEXTF iterator requirement	Li Xu	1	-6/+6
2023-06-19	RISC-V: Bugfix for RVV widenning reduction in ZVE32/64	Pan Li	3	-199/+163
2023-06-19	RISC-V: Bugfix for RVV float reduction in ZVE32/64	Pan Li	3	-216/+280
2023-06-19	amdgcn: implement vector div and mod libfuncs	Andrew Stubbs	1	-0/+244
2023-06-19	amdgcn: minimal V64TImode vector support	Andrew Stubbs	3	-130/+299
2023-06-19	Fix build of aarc64	Richard Biener	1	-1/+2
2023-06-19	avr: Fix wrong array bounds warning on SFR access	Senthil Kumar Selvaraj	1	-0/+17
2023-06-19	RISC-V: Add autovec FP unary operations.	Robin Dapp	1	-1/+35
2023-06-19	RISC-V: Add autovec FP binary operations.	Robin Dapp	5	-14/+137
2023-06-19	RISC-V: Add sign-extending variants for vmv.x.s.	Robin Dapp	2	-0/+34
2023-06-19	RISC-V: Implement vec_set and vec_extract.	Robin Dapp	3	-2/+132
2023-06-19	avr: Fix ICE on optimize attribute.	Senthil Kumar Selvaraj	1	-2/+2
2023-06-18	xtensa: constantsynth: Add new 2-insns synthesis pattern	Takayuki 'January June' Suwa	1	-2/+10
2023-06-18	xtensa: Remove TARGET_MEMORY_MOVE_COST hook	Takayuki 'January June' Suwa	1	-13/+0
2023-06-19	rs6000: Enable const_anchor for 'addi'	Jiufu Guo	1	-0/+4
2023-06-19	Refined 256/512-bit vpacksswb/vpackssdw patterns.	liuhongt	1	-18/+147
2023-06-19	Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_...	liuhongt	4	-30/+59
2023-06-19	RISC-V: Fix one typo for reduc expand GET_MODE_CLASS	Pan Li	1	-1/+1
2023-06-18	Fix arc assumption that insns are not re-recognized	Jeff Law	1	-1/+7
2023-06-18	i386: Refactor new ix86_expand_carry to set the carry flag.	Roger Sayle	3	-14/+19
2023-06-18	i386: Standardize shift amount constants as QImode in i386.md.	Roger Sayle	1	-6/+6
2023-06-18	RISC-V:Add float16 tuple type support	yulong	7	-3/+144
2023-06-17	i386: Two minor tweaks to ix86_expand_move.	Roger Sayle	1	-4/+6
2023-06-17	RISC-V: Bugfix for RVV integer reduction in ZVE32/64.	Pan Li	3	-60/+222
2023-06-17	RISC-V: Fix VL operand bug in VSETVL PASS[PR110264]	Juzhe-Zhong	1	-1/+4
2023-06-16	PR target/31985: Improve memory operand use with doubleword add.	Roger Sayle	1	-0/+30
2023-06-16	aarch64: Handle ASHIFTRT in patterns for shrn2	Kyrylo Tkachov	3	-29/+31