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2023-12-09RISC-V: Fix VLS mode movmiaslign bugJuzhe-Zhong1-21/+2
2023-12-08RISC-V: Add vectorized strcmp and strncmp.Robin Dapp3-5/+163
2023-12-08RISC-V: Add vectorized strlen.Robin Dapp3-12/+34
2023-12-08aarch64: Some tweaks to the early-ra passRichard Sandiford1-20/+69
2023-12-08Revert "arm: vld1q_types_x2 ACLE intrinsics"Richard Earnshaw3-139/+0
2023-12-08Revert "arm: vld1q_types_x3 ACLE intrinsics"Richard Earnshaw3-156/+0
2023-12-08Revert "arm: vld1q_types_x4 ACLE intrinsics"Richard Earnshaw3-159/+0
2023-12-08Revert "arm: vst1_types_x2 ACLE intrinsics"Richard Earnshaw3-125/+0
2023-12-08Revert "arm: vst1_types_x3 ACLE intrinsics"Richard Earnshaw3-125/+0
2023-12-08Revert "arm: vst1_types_x4 ACLE intrinsics"Richard Earnshaw3-125/+0
2023-12-08Revert "arm: vst1q_types_x2 ACLE intrinsics"Richard Earnshaw4-124/+3
2023-12-08Revert "arm: vst1q_types_x3 ACLE intrinsics"Richard Earnshaw3-139/+0
2023-12-08Revert "arm: vst1q_types_x4 ACLE intrinsics"Richard Earnshaw3-141/+0
2023-12-08Revert "arm: vld1_types_x2 ACLE intrinsics"Richard Earnshaw3-149/+20
2023-12-08Revert "arm: vld1_types_x3 ACLE intrinsics"Richard Earnshaw3-154/+15
2023-12-08Revert "arm: vld1_types_x4 ACLE intrinsics"Richard Earnshaw3-154/+15
2023-12-08LoongArch: Fix ICE and use simplify_gen_subreg instead of gen_rtx_SUBREG dire...Jiahao Xu1-33/+46
2023-12-08LoongArch: Vectorized loop unrolling is disable for divf/sqrtf/rsqrtf when -m...Jiahao Xu1-2/+34
2023-12-08LoongArch: New options -mrecip and -mrecip= with ffast-math.Jiahao Xu9-10/+379
2023-12-08LoongArch: Redefine pattern for xvfrecip/vfrecip instructions.Jiahao Xu4-8/+32
2023-12-08LoongArch: Use standard pattern name for xvfrsqrt/vfrsqrt instructions.Jiahao Xu5-23/+44
2023-12-08LoongArch: Add support for LoongArch V1.1 approximate instructions.Jiahao Xu14-3/+242
2023-12-08RISC-V: Fix ICE for incorrect mode attr in V_F2DI_CONVERT_BRIDGEPan Li1-1/+1
2023-12-08LoongArch: Add support for xorsign.Jiahao Xu4-8/+59
2023-12-08LoongArch: Remove the definition of ISA_BASE_LA64V110 from the code.Lulu Cheng9-45/+19
2023-12-08LoongArch: Switch loongarch-def from C to C++ to make it possible.Xi Ruoyao8-258/+390
2023-12-08i386: Mark Xeon Phi ISAs as deprecatedHaochen Jiang3-7/+37
2023-12-08RISC-V: Remove redundant check of better_main_loop_than_p in COST modelJuzhe-Zhong1-3/+0
2023-12-08RISC-V: Support interleave vector with different step sequenceJuzhe-Zhong2-12/+138
2023-12-07aarch64: Add an early RA for strided registersRichard Sandiford14-54/+3736
2023-12-07arm: vld1_types_x4 ACLE intrinsicsEzra Sitorus3-15/+154
2023-12-07arm: vld1_types_x3 ACLE intrinsicsEzra Sitorus3-15/+154
2023-12-07arm: vld1_types_x2 ACLE intrinsicsEzra Sitorus3-20/+149
2023-12-07arm: vst1q_types_x4 ACLE intrinsicsEzra Sitorus3-0/+141
2023-12-07arm: vst1q_types_x3 ACLE intrinsicsEzra Sitorus3-0/+139
2023-12-07arm: vst1q_types_x2 ACLE intrinsicsEzra Sitorus4-3/+124
2023-12-07arm: vst1_types_x4 ACLE intrinsicsEzra Sitorus3-0/+125
2023-12-07arm: vst1_types_x3 ACLE intrinsicsEzra Sitorus3-0/+125
2023-12-07arm: vst1_types_x2 ACLE intrinsicsEzra Sitorus3-0/+125
2023-12-07arm: vld1q_types_x4 ACLE intrinsicsEzra Sitorus3-0/+159
2023-12-07arm: vld1q_types_x3 ACLE intrinsicsEzra Sitorus3-0/+156
2023-12-07arm: vld1q_types_x2 ACLE intrinsicsEzra Sitorus3-0/+139
2023-12-07s390: Fix expansion of vec_stepStefan Schulze Frielinghaus1-2/+2
2023-12-07strub: enable conditional supportAlexandre Oliva1-0/+3
2023-12-07RISC-V: Fix AVL propagation ICE for vleff/vlsegffJuzhe-Zhong2-7/+31
2023-12-07RISC-V: xtheadfmemidx: Disable if xtheadmemidx is not availableChristoph Müllner2-10/+12
2023-12-07aarch64: rcpc3: add Neon ACLE wrapper functions to `arm_neon.h'Victor Do Nascimento1-0/+129
2023-12-07aarch64: rcpc3: Add Neon ACLE intrinsicsVictor Do Nascimento3-0/+74
2023-12-07aarch64: rcpc3: Add relevant iterators to handle Neon intrinsicsVictor Do Nascimento1-8/+17
2023-12-07aarch64: rcpc3: Add +rcpc3 extensionVictor Do Nascimento2-0/+5
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