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2021-04-21Fix clang warnings.Martin Liska1-4/+3
2021-04-21Remove TARGET_foo (ix86_tune == PROCESSOR_foo) macros.Martin Liska7-63/+23
2021-04-21Overhaul in isa_flags and handling it.Martin Liska2-461/+36
2021-04-21Generate PTA features from a def file.Martin Liska2-91/+128
2021-04-21aarch64: Avoid duplicating bti j insns for jump tables [PR99988]Alex Coplan1-0/+15
2021-04-21x86: Add -mmwait for -mgeneral-regs-onlyH.J. Lu8-16/+72
2021-04-21Remove DEF_ENUM from stringop.def.Martin Liska3-15/+0
2021-04-20x86: Use crc32 target option for CRC32 intrinsicsH.J. Lu4-16/+23
2021-04-20rs6000: Fix cpu selection w/ isel (PR100108)Segher Boessenkool1-1/+1
2021-04-19arm: partial revert of r11-8168 [PR100067]Richard Earnshaw1-3/+5
2021-04-19Fix another -freorder-blocks-and-partition glitch with Windows SEHEric Botcazou1-7/+9
2021-04-17d: Add TARGET_D_TEMPLATES_ALWAYS_COMDATIain Buclaw1-0/+5
2021-04-17d: Implement __traits(getTargetInfo, "objectFormat")Iain Buclaw11-0/+268
2021-04-16aarch64: Don't emit -Wpsabi note when ABI was never affected [PR91710]Jakub Jelinek1-9/+14
2021-04-16SVE: Fix wrong sve predicate split (PR100048)Tamar Christina3-5/+20
2021-04-16aarch64: Fix up 2 other combine opt regressions vs. GCC8 [PR100075]Jakub Jelinek1-0/+28
2021-04-15aarch64: Fix several *<LOGICAL:optab>_ashl<mode>3 related regressions [PR100056]Jakub Jelinek1-0/+53
2021-04-14aarch64: Handle more SVE vector constants [PR99246]Richard Sandiford1-0/+54
2021-04-14IBM Z: Fix error checking for immediate builtin operandsAndreas Krebbel2-35/+85
2021-04-14d: Add TARGET_D_REGISTER_CPU_TARGET_INFOIain Buclaw27-8/+311
2021-04-14d: Add TARGET_D_HAS_STDCALL_CONVENTIONIain Buclaw3-1/+23
2021-04-14arm: fix warning when -mcpu=neoverse-n1 is used with -mfpu=neon [PR100067]Richard Earnshaw1-11/+14
2021-04-13aarch64: Restore bfxil optimization [PR100028]Jakub Jelinek1-0/+32
2021-04-12IBM Z: Add alternative to *movdi_{31,64} in order to load a DFP zeroStefan Schulze Frielinghaus1-11/+14
2021-04-12Add rocketlake to gcc.Cui,Lili3-1/+14
2021-04-12Change march=alderlake ISA list and add m_ALDERLAKE to m_CORE_AVX2Cui,Lili2-4/+5
2021-04-10x86: Define _serialize as macroH.J. Lu1-6/+1
2021-04-09aarch64: Fix push/pop_options with --with-cpuRichard Sandiford1-2/+6
2021-04-09aarch64: Use x30 as temporary in SVE TLSDESC patternsRichard Sandiford1-3/+2
2021-04-08aix: revert TLS common changeDavid Edelsohn2-8/+8
2021-04-08VAX: Fix comment for `*bit<mode>' pattern's peepholeMaciej W. Rozycki1-1/+1
2021-04-08arm: Various MVE vec_duplicate fixes [PR99647]Alex Coplan2-21/+12
2021-04-06C-SKY: Describe ck802 bypass accurately.Xianmiao Qu1-2/+6
2021-04-06x86: Update memcpy/memset inline strategies for Skylake family CPUsH.J. Lu2-12/+18
2021-04-06arm: Fix PCS for SFmode -> SImode libcalls [PR99748]Alex Coplan1-0/+4
2021-04-03Darwin : Fix out-of-bounds access to df_regs_ever_live.Iain Sandoe1-2/+3
2021-04-03Darwin : Fix whitespace and delete unused code (NFC).Iain Sandoe1-20/+14
2021-04-03rs6000: Avoid -fpatchable-function-entry* regressions on powerpc64 be [PR98125]Jakub Jelinek1-0/+28
2021-03-31Update prefixed attribute for Power10.Pat Haugen4-25/+52
2021-03-31Handle CONST_POLY_INTs in CONST_VECTORs [PR97141, PR98726]Richard Sandiford2-10/+25
2021-03-31arm: Fix mult autovectorization patterm for iwmmxt (PR target/99786)Christophe Lyon1-1/+4
2021-03-31x86: Update memcpy/memset inline strategies for Ice LakeH.J. Lu5-7/+149
2021-03-31aarch64: Fix target alignment for SVE [PR98119]Richard Sandiford1-3/+4
2021-03-31aarch64: Fix up *add<mode>3_poly_1 [PR99813]Jakub Jelinek1-2/+2
2021-03-31i386, debug: Default to -gdwarf-4 on Windows targets with broken ld.bfd [PR98...Jakub Jelinek1-0/+7
2021-03-30aarch64: PR target/99820: Guard on available SVE issue info before usingKyrylo Tkachov1-1/+3
2021-03-30aarch64: PR target/99822 Don't allow zero register in first operand of SUBS/A...Kyrylo Tkachov1-1/+1
2021-03-30rs6000: Enable 32bit variable vec_insert [PR99718]luoxhu@cn.ibm.com6-26/+85
2021-03-30x86: Define __rdtsc and __rdtscp as macrosH.J. Lu1-12/+2
2021-03-30arm: Fix emission of Tag_ABI_VFP_args with MVE and -mfloat-abi=hard (PR targe...Christophe Lyon1-7/+4
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